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2018-03-30Merge git://git.denx.de/u-boot-marvellTom Rini
2018-03-30arm64: a37xx: dts: enable pcie portWilson Ding
This patch enabled PCIe port on both devel-board and espressobin board. Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Wilson Ding <dingwei@marvell.com> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: populate pcie memory regionWilson Ding
This patch added a new region of 32MiB AT 0xe800.0000 to Armada37x0's memory map. This region is supposed to be mapped in MMU in order to enable the access to the PCI I/O or MEM resources. Signed-off-by: Wilson Ding <dingwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38724 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Victor Gu <xigu@marvell.com> Signed-off-by: Ken Ma <make@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30Revert "arm64: a37xx: dts: Add pin control nodes to DT"Ken Ma
The commit "arm64: mvebu: Add pinctrl nodes for Armada 3700" has added new pinctrl nodes. This reverts commit f7cab0f95b05ec6a66fe4796b9ad44406d0cc864. Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: dts: Correct mpp definitionsKen Ma
This patch corrects below mpp definitions for armada 3720 DB board and ESPRESSOBin board: - "smi" pins group is added and "smi" function is set for eth0; - Now pcie pins are used as gpio to implement PCIe function in hardware, so "pcie" group function is changed to "gpio". Reviewed-on: http://vgitil04.il.marvell.com:8080/43287 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: dts: Fix the number of GPIO on south bridgeKen Ma
The number of pins in South Bridge is 30 and not 29. There is a fix for the driver for the pinctrl, but a fix is also need at device tree level for the GPIO. Reviewed-on: http://vgitil04.il.marvell.com:8080/43286 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: dts: Add additional pinctrl definitionKen Ma
Add mmc pins, pcie pins and sdio pins definition and do these pins' configuration for DB board and espressobin board; Add uart2 pins configuration for DB board. Reviewed-on: http://vgitil04.il.marvell.com:8080/40914 Reviewed-by: Wilson Ding <dingwei@marvell.com> Tested-by: Wilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: dts: Add pinctrl configuration for ESPRESSOBin boardKen Ma
Reviewed-on: http://vgitil04.il.marvell.com:8080/40913 Reviewed-by: Wilson Ding <dingwei@marvell.com> Tested-by: Wilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: dts: add gpio head file includingKen Ma
Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-28rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driverAlexander Kochetkov
Clean the iomux definitions at grf_rk3188.h, and move them into pinctrl-driver for resolving the compiling error of redefinition. Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-28rockchip: pinctrl: rk3036: Move the iomux definitions into pinctrl-driverAlexander Kochetkov
Clean the iomux definitions at grf_rk3036.h, and move them into pinctrl-driver for resolving the compiling error of redefinition. Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-28rockchip: pinctrl: rk3399: add support for I2C[123467]Philipp Tomsich
This adds support for the (to date unsupported) I2C controllers 1~4 and 6~7 (i.e. now all controllers except I2C5, which is not accessible on the RK3399-Q7, are supported by pinctrl). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-28rockchip: pinctrl: rk3399: fix GPIO2B1 and GPIO2B2 shift valuePhilipp Tomsich
The shift values for GPIO2B1 and GPIO2B2 had in fact referred to GPIO2B0 and GPIO2B1, respectively. This substitutes the correct values. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-23arm64: zynqmp: Add support for verifying secure imagesSiva Durga Prasad Paladugu
This patch adds new command "zynqmp" to handle zynqmp specific commands like "zynqmp secure". This secure command is used for verifying zynqmp specific secure images. The secure image can either be authenticated or encrypted or both encrypted and authenticated. The secure image is prepared using bootgen and will be in xilinx specific BOOT.BIN format. The optional key can be used for decryption of encrypted image if user key was specified while creation BOOT.BIN. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm64: zynqmp: Remove ep108 boardMichal Simek
ZynqMP Emulation board is no longer tested and there is no reason to keep maintaining it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm: zynq: Enable cadence driver on zc706Michal Simek
Enable watchdog with reset-on-timeout feature. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm: zynq: Wire watchdog internalsMichal Simek
Watchdog is only enabled in full u-boot. Adoption for SPL should be also done because that's the right place where watchdog should be enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm64: zynqmp: Enable newer pmufw versionsMichal Simek
As of now newer pmufw is keeping old interfaces. That's why permit u-boot to run on newer version. Recommended version will be setup later. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm64: zynqmp: Convert board to use zynqmp-clk driverMichal Simek
Use zynqmp clock driver instead of fixed clocks. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-22Merge git://git.denx.de/u-boot-netTom Rini
2018-03-22ARM: dts: da850-lcdk: Sync from Linux 4.16Lokesh Vutla
Sync dts from Linux 4.16 and also add u-boot specific dtsi for OMAPl138 board. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-03-22davinci: Enable DDR_INIT for DA8XXLokesh Vutla
Commit 6aa4ad8e3820 ("Convert CONFIG_SOC_DA8XX et al to Kconfig") converted SOC_DA8XX to Kconfig but missed enabling DDR_INIT for SOC_DA8XX, which broke OMAPL138 to boot. Commit 2e87980580d0 ("davinci: Fix omapl138_lcdk builds") disabled DDR_INIT for all DA850 SoCs. This failed all DA850 boards to boot as ddr is not being initialized. Enable SYS_DA850_DDR_INIT for DA8XX so that all DA850 and OMAPL138 will have ddr initialized Fixes: 2e87980580d0 ("davinci: Fix omapl138_lcdk builds") Fixes: 6aa4ad8e3820 ("Convert CONFIG_SOC_DA8XX et al to Kconfig") Reported-by: Sekhar Nori <nsekhar@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: David Lechner <david@lechnology.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-03-22armv8: layerscape: csu: enable ns access to PFE registersCalvin Johnson
Enable all types of non-secure access to PFE block registers. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-22armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECCCalvin Johnson
1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces to bufferable. 2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces. 3. Disable ECC detection for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-22armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structureCalvin Johnson
SoC specific PFE macros are defined and structure ccsr_scfg is updated with members defined for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-22armv8: fsl-layerscape: Add support of GPIO structurePrabhakar Kushwaha
Layerscape Gen2 SoC supports GPIO registers to control GPIO signals. Adding support of GPIO structure to access GPIO registers. Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-20Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2018-03-20armv8: ls1088aqds: Add IFC-NOR as boot source for LS1088Ashish Kumar
IFC-NOR and QSPI-NOR pins are multiplexed on SoC, so they cannot be accessed simultaneously. IFC-NOR can be accessed along with SD-BOOT. Ls1088aqds_sdcard_ifc_defconfig is default config for SD boot and IFC-NOR to be used as flash. This allows writing to IFC-NOR flash. QSPI and DSPI cannot be accessed in this defconfig. IFC-NOR image is generated using ls1088aqds_defconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-03-19Merge git://git.denx.de/u-boot-sunxiTom Rini
2018-03-19board: st: add generic board for STM32MP1 familyPatrick Delaunay
Add first support for STM32MP157C-ED1 board with "Basic" boot chain 1/ Boot Rom: load SPL with STM32 image header in SYSRAM 2/ SPL: power up and initialize the DDR and load U-Boot image from SDCARD in DDR 3/ U-Boot: search and load extlinux.conf in SDCARD (DISTRO activated) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19dts: add device tree for STM32MP157C-ED1 boardPatrick Delaunay
Add minimal devicetree for STM32MP157C-ED1 board, with only the devices to allow boot from SDCARD: - RCC for clock and reset - UART4 for console - I2C and PMIC - DDR - SDMMC0 for SDCard Waiting Kernel upstream for alignment. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19ram: stm32mp1: add driverPatrick Delaunay
Add driver and binding for stm32mp1 ddr controller and phy Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19arm: stm32: add new architecture for STM32MP familyPatrick Delaunay
- add new arch stm32mp for STM32 MPU/Soc based on Cortex A - support for stm32mp157 SOC - SPL is used as first boot stage loader - using driver model for all the drivers, even in SPL - all security feature are deactivated (ETZC and TZC) - reused STM32 MCU drivers when it is possible Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19arm: armv7: solve issue for timer_rate_hz in arch timerPatrick Delaunay
The current value timer_rate_hz causes a problem with function timer_get_us() from lib time and then an issue with readx_poll_timeout() function. With corrected value for tbclk() = timer_rate_hz = CONFIG_SYS_HZ_CLOCK the weak functions in lib timer can be used: - get_timer() - __udelay() So the specific function in this file are removed. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19sunxi: Add DRAM_SUN8I_A83T kconfig entryJagan Teki
Add proper and simple kconfig option for dram_sun8i_a83t.c instead of using MACH type on Makefile. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19sunxi: Add DRAM_SUN8I_A33 kconfig entryJagan Teki
Add proper and simple kconfig option for dram_sun8i_a33.c instead of using MACH type on Makefile. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19sunxi: Add DRAM_SUN8I_A23 kconfig entryJagan Teki
Add proper and simple kconfig option for dram_sun8i_a23.c instead of using MACH type on Makefile. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19sunxi: Add DRAM_SUN9I kconfig entryJagan Teki
Add proper and simple kconfig option for dram_sun9i.c instead of using MACH type on Makefile. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19sunxi: Add DRAM_SUN4I kconfig entryJagan Teki
Add proper and simple kconfig option for dram_sun4i.c instead of using MACH type on Makefile. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19sunxi: add DRAM_SUN6I kconfigJagan Teki
Add proper and simple kconfig option for dram_sun6i.c instead of using MACH type on Makefile. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19sunxi: Add AXP_PMIC_BUS kconfig entryJagan Teki
Add simple and meaningful kconfig option for pmic_bus.c instead of using MACH type on Makefile. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19sunxi: Add SUN8I_RSB kconfig entryJagan Teki
Add simple and meaningful kconfig option for rsb.c instead of using MACH type on Makefile. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19sunxi: Use SUN6I_PRCM if usedJagan Teki
SUN6I_PRCM is also used for SUN8I and SUN9I, so select the same on respective MACH types. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19sunxi: Add SUN6I_P2WI kconfig entryJagan Teki
Add simple and meaningful kconfig option for p2wi.c instead of using MACH type on Makefile. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19sunxi: Add SUN6I_PRCM kconfig entryJagan Teki
Add simple and meaningful kconfig option for prcm.c instead of using MACH type on Makefile. PRCM (Power/Reset/Clock Management) is considered as a Multi-Functional Device, so used the same on Kconfig definition. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19arm: dts: stm32: add display for STM32F746 disco boardyannick fertre
Enable the display controller, panel & backlight. Set panel display timings & set the RGB data bus. Signed-off-by: yannick fertre <yannick.fertre@st.com>
2018-03-19arm: dts: stm32: add ltdc for STM32F746Philippe CORNU
Add display controller node in device-tree. Signed-off-by: yannick fertre <yannick.fertre@st.com> [agust: rebased on master] Signed-off-by: Anatolij Gustschin <agust@denx.de>
2018-03-16Convert all of CONFIG_CONS_INDEX to KconfigTom Rini
This converts the following to Kconfig: CONFIG_CONS_INDEX We have existing entries for this option in a number of places, with different guards on them. They're also sometimes used for things not directly inside of the serial driver. First, introduce a new symbol to guard the use of CONFIG_CONS_INDEX, so that in the case where we don't need this for the serial driver, but for some other use, we can still do it. Next, consolidate all of these into the single entry in drivers/serial/Kconfig. Finally, introduce CONS_INDEX_[023456] so that we can imply a correct value here to make the defconfig side of this smaller. Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Rework a lot of the logic here, such that I took authorship from Adam, but kept his S-o-B line] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-03-16clk: at91: add USB Host clock driverWenyou Yang
Add USB clock driver to configure the input clock and the divider in the PMC_USB register to generate a 48MHz and a 12MHz signal to the USB Host OHCI. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2018-03-15Merge git://git.denx.de/u-boot-uniphierTom Rini
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