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2014-04-16tegra: usb: Fix device enumeration problem of USB1Jim Lin
tegra: usb: Fix device enumeration problem of USB1 A known hardware issue of USB1 port where bit 1 (connect status change) of PORTSC register will be set after issuing Port Reset (like "usb reset" in u-boot command line). This will be treated as an error and stops later device enumeration. Therefore we clear that bit after Port Reset in order to proceed later device enumeration. Signed-off-by: Jim Lin <jilin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-03-16colibri_t20: disable PMIC sleep mode on low supply voltageColibri_T30_LinuxImageV2.1Beta3_20140318Colibri_T20_LinuxImageV2.1Beta3_20140318Apalis_T30_LinuxImageV2.1Beta3_20140318Marcel Ziswiler
The Colibri T20's PMIC enters a sleep mode on low supply voltage < 3.0V ±2.5% (2.92...3.08V). Rising the main supply voltage again does not bring it back to regular operation. Not even a full reset does bring the module back. A full power cycle was required to reboot the system. A long positive pulse on the PMICs resume pin also reboots the system but this pin is only accessible as a test point on the module. This patch configures the PMIC through I2C to not enter this sleep mode plus force it to normal state upon sleep request exit should this ever happen.
2013-08-12apalis/colibri_t30: implement memory size auto detectionMarcel Ziswiler
In preparation for the new Apalis T30 SKUs implement memory size auto detection based on reading the aperture register set by boot ROM from BCT and a simple mirroring detection. Tested on initial samples of Apalis T30 1GB V1.0A, Apalis T30 2GB V1.0B, Apalis T30 2GB V1.0C and Colibri T30 V1.1C.
2013-05-09apalis/colibri_t30: increase CPU frequency at bootMarcel Ziswiler
Due to a unoptimised PLL X table we were only running at 400MHz during boot. Incorporated the PLL X table from NVIDIA's latest public U-Boot sources: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/u-boot.git;a=blob;f=arch/arm/cpu/arm720t/tegra-common/cpu.c;h=119342e9577f6b42f93d118b81c0e931c9c9423a;hb=chromeos/v2013.01.01-tegra114#l67 And actually set up the T30 PLLs regardless of slow flag as this is anyway exclusively used on T20. Issue report courtesy of Mariusz Bulkowski from Draminski.
2013-05-09apalis_t30: initial integrationMarcel Ziswiler
Add initial Apalis T30 support based off our current Colibri T30 implementation: - Updated machine ID. - USB host USBH2 and USBH3 support. Note: USBO1 support is currently broken. - Updated MMC and SD card support. - Adjusted available amount of memory.
2013-05-01colibri_t20/30: mmc: integrate NVIDIA partition table parsingMarcel Ziswiler
NVIDIA's MMC/SD layout includes a partition table that can be used to generically determine U-Boot environment, kernel, configuration block as well as GPT offsets. As an added benefit this is completely independent of the underlying MMC/SD card used which might differ with various future module versions or particularly cards used for T20 SD boot. Also handles the case of T20 SD boot where the configuration block is still taken from NAND flash while the rest resides on the SD card. Initial partition table parsing courtesy of Mitja Špes from LXNAV.
2013-01-11colibri_t30: migrate to proper machine typeMarcel Ziswiler
After having registered the following proper machine type migrate to actually using it. http://www.arm.linux.org.uk/developer/machines/list.php?id=4493 While at it clean-out some obsolete Cardhu specific device-tree nodes resp. properties and clean-up the mach-types header file as well.
2012-12-18T30: define USE_PRIVATE_LIBGCC, oe-core can't build withoutT20_LinuxImageV2.0Beta1_20121218Max Krummenacher
2012-11-28CPU reset bitfields: - fix bitpositions in ↵Max Krummenacher
CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0
2012-11-28ap20.c: - fix FLOW_MODE field location, is 31:29 according to register ↵Max Krummenacher
description in Android code. no bug visible as function is not called with run = 1
2012-11-28ap20.c: - fix use of interleaved use of struct pll vs. struct pll_simple ↵Max Krummenacher
here this use did not show any adverse effects
2012-10-30Merge branch 'chromeos-v2011.06' into colibriMarcel Ziswiler
Conflicts: arch/arm/cpu/armv7/tegra3/warmboot_avp.c arch/arm/include/asm/arch-tegra/clk_rst.h
2012-10-29tegra: add enterrcm commandStephen Warren
tegra: add enterrcm command Tegra's boot ROM supports a mode whereby code may be downloaded and flash programmed over a USB connection. On dev boards, this is typically entered by holding down a "force recovery" button and resetting the CPU. However, not all boards have such a button (one example is the Compulab Trimslice), so a method to enter RCM from software is useful. This change implements the command "enterrcm" to do this, and enables it for all Tegra boards by default. Even on boards other than Trimslice, controlling this over a UART may be useful, e.g. to allow simple remote control without the need for mechanical button actuators, or hooking up relays/... to the button. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-18colibri_t20: nand: change offset handlingMarcel Ziswiler
Rather than relying on hard-coded offsets actually make use of partition table parsing implementation.
2012-10-18colibri_t20: nand: integrate NVIDIA partition table parsingMarcel Ziswiler
NVIDIA's NAND layout includes a partition table that can be used to generically construct the mtdparts kernel boot argument. As an added benefit this is completely independent of the underlying NAND part used which differs with various module versions. It further allows our customer easy adoption to their own custom partition layout. Initial partition table parsing courtesy of Mitja Špes from LXNAV.
2012-10-18colibri_t20: add sanity check to board_query_sdram_size()Marcel Ziswiler
Colibri T20 does not use OdmData but rather relies on memory controller configuration done by boot ROM based on BCT information. Unfortunately it is possible to at least boot a 256 MB module with a 512 MB BCT therefore double check whether we really do have that.
2012-10-18tegra 30: PMIC init commentMarcel Ziswiler
Add comment concerning PMIC initialisation of VDD_CPU via VDDCtrl.
2012-08-22Initial Toradex Colibri T20 L4T R15 support.T20_LinuxImageV2.0Alpha1_20120808Marcel Ziswiler
2012-06-05arm: tegra3: Fix bootup up issuePuneet Saxena
At bootup time device enters in standby state as CLK_RST_CONTROLLER_SCLK_BURST_POLICY is not set correctly. This change correctly sets clock burst policy. BUG = None TEST= Build OK for Seaboard,Cardhu and Waluigi. Tested on Cardhu and waluigi. Device boots up. Change-Id: I598ca7bcfc4a39ecaa68c211d3439ac3569c6e44 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/24164 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Tested-by: Tom Warren <twarren@nvidia.com> Commit-Ready: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2012-02-27arm: tegra3: add warmboot code needed for LP0Varun Wadekar
BUG=chromium-os:23496 TEST=build and boot on Waluigi, Cardhu by enabling CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT. odification of the work done by: a. Jimmy Zhang <jimmzhang@nvidia.com> b. Yen Lin <yelin@nvidia.com> c. Wei Ni <wni@nvidia.com> Change-Id: If2fa63ccd23341694955bca25fb5cfc4a8a805ad Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13800
2012-02-24arm: tegra: move warmboot_avp.h over to common locationVarun Wadekar
warmboot_avp.h needs to be present in include/arch-tegra in order to use it for Tegra3. BUG=chromium-os:23496 TEST=build for Seaboard Change-Id: I3f369194e4002e8257c9d2ff37253bc20733138d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/15394
2012-02-24arm: tegra3: header file for the MC/EMC registersVarun Wadekar
BUG=chromium-os:23496 TEST=build for Cardhu, Waluigi and Seaboard Change-Id: I6d26502d1ecc393b266ffe06b540f59c595e19ae Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14811
2012-02-24arm: tegra3: header file for sdmmc controller registersVarun Wadekar
BUG=chromium-os:23496 TEST=build for Cardhu, Waluigi and Seaboard Change-Id: Ifa06f941798ff242197dcd31f4091567d91fe4b2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14810
2012-02-24arm: tegra3: add header for APB_MISC_GP and padctrl registersVarun Wadekar
BUG=chromium-os:23496 TEST=build for Cardhu, Waluigi and Seaboard Change-Id: I74bb2418ab996e362060351de3ba7efd538ffd87 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14809
2012-02-24arm: tegra3: add header file to describe the AHB controllerVarun Wadekar
BUG=chromium-os:23496 TEST=build for Cardhu, Waluigi and Seaboard Change-Id: I20ac75c71d86d65ff422ff3f4f966a69718f4f91 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14808
2012-02-24arm: tegra3: add PMC registersVarun Wadekar
These registers would be useful for the warmboot code. BUG=chromium-os:23496 TEST=build for Cardhu, Waluigi and Seaboard Change-Id: I58f52b6b8653d72b2e842ee44bdf3632eff304a2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14690
2012-02-24arm: tegra3: add AHB aperture base addressVarun Wadekar
Would be useful for the warmboot code. BUG=chromium-os:23496 TEST=build for Cardhu, Waluigi and Seaboard Change-Id: I271f6cdcc0248337e516c2c32014c6ec4f08fb15 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14689
2012-02-24arm: tegra3: add flow controller registersVarun Wadekar
These registers would be useful for the warmboot code. BUG=chromium-os:23496 TEST=build for Cardhu, Waluigi and Seaboard Change-Id: I8da1ed3a382e1b65247236cb19f527f81d8ecaac Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14688
2012-02-16arm: tegra: add chipid value to uniquely identify tegra3Varun Wadekar
BUG=chromium-os:23496 TEST=build for Cardhu, Waluigi Change-Id: Iacd6fdb178afbfdb978dbe53bbe2766916bf26f9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14685
2012-02-16arm: config: tegra: add bct offset addressVarun Wadekar
BUG=chromium-os:23496 TEST=build for Cardhu, Waluigi and Seaboard Change-Id: I32dbfa02ac1d6954b3a7e515914fbc0b6695f98b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14683
2012-02-14arm: tegra2: split LP0 code to help future chipsVarun Wadekar
split the LP0 code for tegra2 into common LP0 code and chip specific warm boot code BUG=chromium-os:23496 TEST=build for Seaboard Change-Id: Ie04bf9ac17482a37afd0f4515dc3aafeb4f48ae7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/15883
2012-02-08Revert "arm: tegra2: split LP0 code to help future chips"Brian Harring
This reverts commit 4c7502242627f64d91432cb4958be5f93f65fbff Don't think this is the cause of http://code.google.com/p/chromium-os/issues/detail?id=26116, but it was in the same batch so I'm reverting in the process. Change-Id: Icc013ced6c22e29d569ee4ca8ef73522154ec1a8 Reviewed-on: https://gerrit.chromium.org/gerrit/15561 Reviewed-by: Brian Harring <ferringb@chromium.org> Tested-by: Brian Harring <ferringb@chromium.org>
2012-02-08Revert "arm: tegra2: add .lds to calculate warm boot code size"Brian Harring
This reverts commit 9a3fbb5f0b02382c7abe0cf40a4f08abbf269d05 Broke tegra2: http://code.google.com/p/chromium-os/issues/detail?id=26116 Change-Id: I7d35211c6ebce7a10750cb1033c6f8ba9a0f63bc Reviewed-on: https://gerrit.chromium.org/gerrit/15560 Reviewed-by: Brian Harring <ferringb@chromium.org> Tested-by: Brian Harring <ferringb@chromium.org>
2012-02-08arm: tegra2: add .lds to calculate warm boot code sizeVarun Wadekar
move away from the current method, where we add wb_end() immediately after wb_start() and then use the function addresses to calculate the WB code size. Add a .lds script to expose __wb_end after wb_start() in the .text section and then reference this variable in the WB size calculation code. BUG=chromium-os:23496 TEST=build on Seaboard. Verified that uboot.map has the correct address assigned to __wb_end and that LP0 works reliably. Change-Id: I170277f00b450d38063018453faf44d5a38abaaa Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14682
2012-02-08arm: tegra2: split LP0 code to help future chipsVarun Wadekar
split the LP0 code for tegra2 into common LP0 code and chip specific warm boot code BUG=chromium-os:23496 TEST=build for Seaboard Change-Id: Id9756c08f61502affa8beee636d883d01468e6ec Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13799
2012-02-07video: tegra: Change the clock settings for LCD driverPuneet Saxena
As clock source for graphics related clocks is different for Tegra2 and Tegra3, define it under platform specific directories. BUG=chromium-os:23496 TEST=Build ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi. Original work by - Mayuresh Kulkarni <mkulkarni@nvidia.com> Change-Id: I6cee11df5e75eaf3836565c4fa4f3ab3e45d8cac Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14700
2012-02-07tegra: Change parent clock for Tegra2 and Tegra3Puneet Saxena
Set display parent clock separately for Tegra2 and Tegra3. BUG=chromium-os:23496 TEST=Built ok for Cardhu Walgui and Seaboard. Tested on Waluigi. Change-Id: Ie03d37b8dda77dcfcb72e70c34e769a23323e598 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14697
2012-02-07tegra: Extend support for RAM size as 2GBPuneet Saxena
Add a case for returning RAM size as 2GB by reading PMC scratch20 register. BUG=chromium-os:23496 TEST=Build ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi. Change-Id: I5dc8fdf7cd9718e5dd2ca24cd1f467c5b6e9a6aa Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14696
2012-02-07tegra: Move display.c & pwfm.c from tegra2 to tegra-commonPuneet Saxena
Move pwfm.c and display.c under common folder tegra-common. BUG=chromium-os:23496 TEST=Built ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi. Change-Id: I23c5f02270dde7bfdd6e1d26ed9984385986194e Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14694
2012-01-06CHROMIUM: Support vboot without a displaySimon Glass
This allows booting without a display, mostly as a way of calculating the time that LCD init and maintenance costs us. Perhaps we might integrate the lcd and video APIs within U-Boot - it would be a much nicer solution. With that in mind I feel it is not work refactoring this into three separate (lcd, video, none) files to implement the display API. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: Iea4656f8939f7f2fd78292827091de4ee379954b Reviewed-on: https://gerrit.chromium.org/gerrit/13369 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
2012-01-05hack: Change relocation over to use memset/memcpySimon Glass
While we wait for the new relocation stuff to come down from upstream, this uses memset/memcpy() to do the business. Saves about 20ms on boot. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: I958b9f53f27c67d4da2fa0f7a2148c59ed48f7aa Reviewed-on: https://gerrit.chromium.org/gerrit/13215 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-21arm: Implement CONFIG_DELAY_CONSOLESimon Glass
Delay serial console calls and do them later, to support the CONFIG_DELAY_CONSOLE option. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: Ie15a887843a8b5f29fce055f7a2e17b7fc1e614f Reviewed-on: https://gerrit.chromium.org/gerrit/13209 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-12-20tegra: Add debugging to display clocks during initSimon Glass
When DEBUG is enabled, display important clocks during init. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: Ic27e7d79bdcd9cf44d94ec25c52fc8776ddc7d04 Reviewed-on: https://gerrit.chromium.org/gerrit/13205 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-20Add a new boot stage to time relocationSimon Glass
Relocation takes about 40ms of the boot time, so add a timer to track it. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: If936bc8ff9a23f6dd885f60e845a597ac7edad97 Reviewed-on: https://gerrit.chromium.org/gerrit/13203 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-13tegra: USB: Add T30 USB header filesTom Warren
BUG=chromium-os:23496 TEST=built Seaboard and Waluigi OK Signed-off-by: Tom Warren <twarren@nvidia.com> Change-Id: I954cdb71eb80a3cf48f44b9a7183a2cafcb7755b Reviewed-on: https://gerrit.chromium.org/gerrit/12442 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-12-12tegra: Update clocks after fdt is availableSimon Glass
Some clocks cannot be set to the final value until we have the fdt and know what PLLP should be set to. For now the only example is coresight - so this adds a call to update this clock once the A9 is up and running with the fdt. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: I7a07306cfb0a24cec4dcdb08cac78659a1afc73f Reviewed-on: https://gerrit.chromium.org/gerrit/12251 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-12tegra: Remove CONFIG_SYS_PLLP_BASE_IS_408MHZSimon Glass
This setting is now in the fdt, so remove the CONFIG item. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: I336a6cc2140c725fdda85330efe617f82f205a90 Reviewed-on: https://gerrit.chromium.org/gerrit/12250 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-05Move fdt check earlier so that board_early_init_f() can use itSimon Glass
We want to use the fdt inside board_early_init_f(), so check for its presence earlier in the pre-reloc init sequence. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: I66fdaf976ddb419b754cc20374db4ffdcca16a09 Reviewed-on: https://gerrit.chromium.org/gerrit/12247 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-12-05tegra: Add a clock rate parameter to clock_early_init()Simon Glass
Since PLLP can be set to two different values, make it a parameter to the function that sets up the PLLs. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: I81ccc1cc3356796793ec2dd4ab22ed7fbd52f01d Reviewed-on: https://gerrit.chromium.org/gerrit/12245 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-02Adjust pllx_set_rate to remove delayBernie Thompson
This is using the latest patch recommendation from Dilan at Nvidia, we adjust the ordering to clear bypass earlier and remove the delay. This patch was run successfully for over 2000 reboots. BUG=chrome-os-partner:6145 TEST=Manual Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Change-Id: I9ef2f12d5c8abae86791f50b0f5e0e5a4249d947 Reviewed-on: https://gerrit.chromium.org/gerrit/12385 Reviewed-by: Micah Catlin <micahc@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org>
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