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2019-06-27mx6sl: hab: Fix pu_irom_mmu_enabled addressBreno Matheus Lima
According to hab.c code we have to notify the ROM code if the MMU is enabled or not. This is achieved by setting the "pu_irom_mmu_enabled" to 0x1. The current address in hab.c code is wrong for i.MX6SL, according to ROM map file the correct address is 0x00901c60. As we are writing in the wrong address the ROM code is not flushing the caches when needed, and the following HAB event is observed in certain scenarios: --------- HAB Event 1 ----------------- event data: 0xdb 0x00 0x14 0x41 0x33 0x18 0xc0 0x00 0xca 0x00 0x0c 0x00 0x01 0xc5 0x00 0x00 0x00 0x00 0x07 0xe4 STS = HAB_FAILURE (0x33) RSN = HAB_INV_SIGNATURE (0x18) CTX = HAB_CTX_COMMAND (0xC0) ENG = HAB_ENG_ANY (0x00) Update MX6SL_PU_IROM_MMU_EN_VAR to address this issue. Reported-by: Frank Zhang <frank.zhang@nxp.com> Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-06-26rockchip: rk3399: Enable TPL_BOARD_INITJagan Teki
Enable TPL_BOARD_INIT, this would help us to show TPL boot prints. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: rk3399: tpl: Mark printascii into debugJagan Teki
Now, we have spl_board_init which has TPL banner prints. So mark the 'U-Boot TPL board init' print into debug. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: rk3399: tpl: Add spl_board_initJagan Teki
Add spl_board_init for TPL, that have TPL banner will help to print tpl boot prints. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: rk3399: Enable SPL_BOARD_INITJagan Teki
Enable SPL_BOARD_INIT globally to rk3399, this would help to print the SPL banner during bootup. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: rk3399: Move u-boot, dm-pre-reloc of uart0, uart2Jagan Teki
u-boot,dm-pre-reloc for uart0, uart2 indeed u-boot specific properties. Move them into rk3399-u-boot.dtsi so the boards which enabled these node will available during SPL. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: rk3399: spl: Mark printascii into debugJagan Teki
Now, we have spl_board_init with preloader_console_init that indeed show SPL banner. So mark the 'U-Boot SPL board init' print into debug. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: rk3399: Support common spl_board_initJagan Teki
Support common spl_board_init by moving code from puma board file into, common rk3399-board-spl.c. Part of the code has sysreset-gpio, regulators_enable_boot_on but right now only puma board is using this with relevant config options rest remains common for all targets. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: rk3399: Get bl31.elf via BL31Jagan Teki
Right now rockchip platform need to copy bl31.elf into u-boot source directory to make use of building u-boot.itb. So, add environment variable BL31 like Allwinner SoC so-that the bl31.elf would available via BL31. If the builds are not exporting BL31 env, the make_fit_atf.py explicitly create dummy bl31.elf in u-boot root directory to satisfy travis builds and it will show the warning on console as WARNING: BL31 file bl31.elf NOT found, resulting binary is non-functional WARNING: Please read Building section in doc/README.rockchip Note, that the dummy bl31 files were created during not exporting BL31 case would be removed via clean target in Makefile. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-26rockchip: dts: rk3328: add rk3328-rock64.dtsMatwey V. Kornilov
rk3328-rock64.dts has been taken from Linux kernel commit cff6d1d6f88b ("arm64: dts: rockchip: enable HS200 for eMMC on rock64") with minor modifications (drop nodes not known by rk3328.dtsi). Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: Kconfig: enable SPL support for rk3328Kever Yang
Enable SPL support and some related option in Kconfig. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> [cherry picked from https://github.com/rockchip-linux/u-boot/commit/430b01462bf3f24aaf7920ae2587a6943c39ab5d with minor modifications] Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
2019-06-26rockchip: rk3328: add SPL board file supportKever Yang
rk3328 SPL is locate at dram, so do not have strict size limit, suppose to enable storage media controller driver, load ATF and U-Boot, then boot into ATF. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> [cherry picked from https://github.com/rockchip-linux/u-boot/commit/4ebe3968b683190cb8e5741aa7227b4fa7497874 with minor modifications] Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-20armv8: fix typo in LINUX_KERNEL_IMAGE_HEADER checkMian Yousaf Kaukab
Fixes: 8163faf952 ARMv8: add optional Linux kernel image header Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Andreas Färber <afaerber@suse.de>
2019-06-20Merge tag 'u-boot-stm32-20190619' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Update STM32MP entry in MAINTAINERS - Handle correctly binding for g-tx-fifo-size for USB DWC2 driver - Fix trusted STM32MP1 defconfig with correct ethernet driver
2019-06-19Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- LS1046AFRWY support - USB errata fix and secure boot defconfig support for LS1028A - Enabled SDHC and SATA for LX2160 - LS1046A serdes fixes - other minor fixes
2019-06-19ARM: dts: stm32mp1: remove override for g-tx-fifo-sizePatrick Delaunay
Remove the override for usbotg_hs on g-tx-fifo-size as the correct binding, used in the kernel device tree, is now supported in dwc2 device driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-06-19armv8: ls1046afrwy: Add support for LS1046AFRWY platformVabhav Sharma
LS1046AFRWY board supports LS1046A family SoCs. This patch add base support for this board. Board support's 4GB ddr memory, i2c, micro-click module,microSD card, serial console,qspi nor flash,ifc nand flash,qsgmii network interface, usb 3.0 and serdes interface to support two x1gen3 pcie interface. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19arm: ls1028a: define the integrated PCI bus (ECAM)Alex Marginean
LS1028A includes an integrated PCI bus with 11 PCI functions residing on bus 0. ECAM plus the device register space takes up 256MB of address space. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-lsch2: add clock support for the second eSDHCYinbo Zhu
Layerscape began to use two eSDHC controllers, for example, LS1012A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19arm: fsl-layerscape: add 0x3040 serdes1 settings for LS1046AMaciej Pijanowski
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Cc: piotr.krol@3mdeb.com Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19arm: fsl-layerscape: fix 0x3363 serdes1 settings for ls1046aMaciej Pijanowski
As per LS1046A hardware manual, SGMII.9 and SGMII.10 present on lane D and lane C respectively for 0x3363 protocol. So fix serdes1 settings for ls1046a. Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-layerscape: fix config dependency for layerscape pci codeAlex Marginean
Fixes a link error on layerscape platform, linking fails with CONFIG_PCI set and CONFIG_PCI_LAYERSCAPE unset. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-layerscape: Change bootcmd update logicPankit Garg
Change bootcmd update logic when CONFIG_ENV_ADDR is not defined Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-layerscape: Update qspi clk cfgPankit Garg
Update qspi clock configuration in TFABOOT in case of all boot sources except qspi boot source. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19ARM: dts: ls1021a: Fixed reg for sata nodePeng Ma
This patch is to fixed the reg read to "0" for armv7 architecture. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8/fsl-layerscape: Add loop to check L3 dcache statusMeenakshi Aggarwal
Flushing L3 cache may need variable time depending upon cache line allocation. Coming up with a proper timeout value would be best handled by simulations under multiple scenarios in your actual system. >From the purely HN-F point of view, the flush would take ~15 cycles for a clean line, and ~22 cycles for a dirty line. For the dirty line case, there are many variables outside the HN-F that will increase the duration per line. For example, a *DBIDResp from the SN-F/SBSX, memory controller latency, SN-F/SBSX RetryAck responses, CCN ring congestion, CCN ring hops, etc, etc. The worst-case timeout would have to factor in all of these variables plus the HN-F cycles for every line in the L3, and assuming all lines are dirty In case if L3 is not flushed properly, system behaviour will be erratic, so remove timeout and add loop to check status of L3 cache. System will stuck in while loop if there is some issue in L3 cache flushing. Signed-off-by: Udit Kumar <udit.kumar@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: lx2160aqds: Enable eSDHC controllersYinbo Zhu
This patch is to enable esdhc controllers for lx2160aqds Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: Add ecc address node for sata.Peng Ma
Move the ecc addr from driver to dts Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-lsch3: add clock support for the second eSDHCYangbo Lu
Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: lx2160aqds: Enable sataPeng Ma
Change sata node status to enable sata. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: Add other serdes protocal supportXiaowei Bao
Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: enable workaround for USB errarum A-009007Yinbo Zhu
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. So program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: enable workaround for USB erratum A-008997Ran Wang
Enable workaround for USB erratum A-008997. Here PCSTXSWINGFULL registers has been moved to DSCR as compared to other Layerscape SoCs where it was in SCFG. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-17Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
- Drop zipitz2 board (Tom) - Add DEPRECATED option (Tom) - Mark legacy or non-dm drivers as DEPRECATED (Jagan)
2019-06-14arm: socfpga: provide default SPL_SIZE_LIMIT for gen5Simon Goldschmidt
This provides an SPL_SIZE_LIMIT that makes the build check that the SPL binary loaded from flash fits into the SRAM (64 KiB) and leaves enough room for global data, heap and stack (512 bytes assumed stack usage). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-06-14arm: dts: Stratix10: Enable i2cLey Foon Tan
Enable i2c1 in Stratix 10 devkit. SOCFPGA_STRATIX10 # i2c bus Bus 0: i2c@ffc02900 SOCFPGA_STRATIX10 # i2c dev 0 Setting bus to 0 SOCFPGA_STRATIX10 # i2c probe Valid chip addresses: 14 4C 51 68 74 Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-06-13arm: Remove zipitz2 boardTom Rini
Per discussion on the list, drop this board again. Cc: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-12ARM: bcm283x: Fix definition of MBOX_TAG_TEST_PIXEL_ORDERBerkus Decker
The MBOX_TAG_TEST_PIXEL_ORDER define is incorrect. According to official documentation it has a slightly different numbering. Correct mailbox constants are defined in e.g. linux raspberry-firmware https://code.woboq.org/linux/linux/include/soc/bcm2835/raspberrypi-firmware.h.html#RPI_FIRMWARE_FRAMEBUFFER_TEST_PIXEL_ORDER These are obtained from the bcm2835 documentation e.g. https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface#test-pixel-order Fix the define to get us back in sync with the spec. Signed-off-by: Berkus Decker <berkus+github@metta.systems> [agraf: clarify subject, extend commit message] Signed-off-by: Alexander Graf <agraf@csgraf.de> [mb: updating email of agraf] Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-06-12fdt: update bcm283x device tree sources to Linux 5.1-rc6 stateHeinrich Schuchardt
Updating the bcm283x device tree sources adds the device trees for - Raspberry Pi 3 Model A+ - Raspberry Pi 3 Model B+ - Raspberry Pi Compute Module IO board rev1 - Raspberry Pi Compute Module 3 IO board V3.0 - Raspberry Pi Zero Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-06-11Merge tag 'u-boot-stm32-20190606' of https://github.com/pchotard/u-bootTom Rini
- Add Ethernet support for STM32MP1 - Add saveenv support for STM32MP1 - Add STM32MP1 Avenger96 board support - Add SPI driver suport for STM32MP1 - Add watchdog support for STM32MP1 - Update power supply check via USB TYPE-C for STM32MP1 discovery board
2019-06-11Merge tag 'u-boot-imx-20190612' of git://git.denx.de/u-boot-imxTom Rini
u-boot-imx-20190612 -------------------- - Board fixes: - imx6logic - wandboard - mx6sabre boots again - imx8qm_mek - pico-* boards - Toradex apalis / colibri - engicam imx6 (environment) - KP MX53 - opos6ul - Switch to DM: - vining2000 - dh MX6 - Toradex colibri i.MX7 - Novena - Security : fix CSF size for HAB - Other: - imx: fix building for i.mx8 without spl - pcie and switch to DM mx6sabreauto: Enable SPL SDP support
2019-06-11arm: dts: imx6qdl-u-boot: Alias usb0 to usbotgSjoerd Simons
All i.mx6 boards seems to have moved to DM_USB, however gadget support for mx6 is still pre-DM as CI_UDC isn't converted yet. To make this work the usb otg controller used for gadgets needs to be usb number 0. Add an alias for this directly in the main u-boot mx6qdl dtsi so it doesn't need to be done for each board separately. This fixes regressions wrt. usb gadget functionality in several boards that have gadget functions enabled in their config, but no usb0 alias in their device-tree. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
2019-06-11imx: define ARCH_MXC for i.MX8/8M/7ULPPeng Fan
Without this definition, fsl_esdhc will access reserved registers on i.MX chips, so define ARCH_MXC to fix it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-06-11imx: drop imx-regs.hPeng Fan
imx-regs.h under arch-imx has no user, drop it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-06-11imx8: cpu: get temperature when print cpu descPeng Fan
Read the temperature when print cpu inforation. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-06-11ARM: imx: vining2000: Convert MMC and block to DMMarek Vasut
Enable DM block and DM MMC support on iMX6SX VINING|2000 . Convert board code to match the DM support. This disables USB mass storage support due to missing DM USB, however that will be re-enabled in subsequent patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Stefano Babic <sbabic@denx.de>
2019-06-11ARM: dts: imx: vining2000: Import VINING|2000 DT from LinuxMarek Vasut
Import iMX6SX VINING|2000 device tree from Linux 5.1.1 b724e9356404 . Enable DT control in full U-Boot . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Stefano Babic <sbabic@denx.de>
2019-06-11ARM: imx: Rename VINING|2000Marek Vasut
The company Samtec was merged into Softing, migrate the board over to the new name and update copyright headers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Stefano Babic <sbabic@denx.de>
2019-06-11ARM: imx: Call imx_pcie_remove() only for non-DM PCI driverMarek Vasut
The DM iMX PCI driver has DM_FLAG_OS_PREPARE set and will call imx_pcie_remove() from the .remove callback. Do not call it from the architecture code again. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11imx: Extend PCL063 support for phyCORE-i.MX6ULL SOMParthiban Nallathambi
Extend PHYTEC phyBOARD-i.MX6UL for phyCORE-i.MX6UL SoM (PCL063) with eMMC on SoM. CPU: Freescale i.MX6ULL rev1.0 792 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 38C Reset cause: POR Model: Phytec phyBOARD-i.MX6ULL-Segin SBC Board: PHYTEC phyCORE-i.MX6ULL DRAM: 256 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial@02020000 Out: serial@02020000 Err: serial@02020000 Net: FEC0 Working: - Eth0 - i2C - MMC/SD - eMMC - UART (1 & 5) - USB (host & otg) Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
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