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For LD11 and LD20 SoCs, the System Bus and NAND are multiplexed
in the same I/O pins. When booting from a NAND device, pin-mux
for the System Bus must not be set-up because they are exclusive
with each other.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot
proper. Split the common code into pll-base-ld20.c for easier
re-use.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Use the pin-mux data in the pinctrl drivers by directly calling
pinctrl_generic_set_state().
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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The Boot ROM has enabled D-cache and MMU setting DDR memory area
as Normal Memory in its page table. Disable D-cache and MMU
before jumping to U-Boot proper.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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The System Bus is not available by default on the ROM boot mode of
PH1-LD20. To use devices connected to the System Bus, such as the
Micro Support Card, it is necessary to set up pin-muxing and some
System Bus Controller register.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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This is the first ARMv8 SoC from Socionext Inc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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