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2023-01-11Use `grep -E` or plain `grep` instead of `egrep`Ville Skyttä
`egrep` has been deprecated in GNU grep since 2007, and since 3.8 it emits obsolescence warnings: https://git.savannah.gnu.org/cgit/grep.git/commit/?id=a9515624709865d480e3142fd959bccd1c9372d1 Acked-by: Dhruva Gole <d-gole@ti.com>
2022-12-05global: Move remaining CONFIG_SYS_* to CFG_SYS_*Tom Rini
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*Tom Rini
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10global: Migrate CONFIG_HPS* symbols to the CFG namespaceTom Rini
Migrate all of CONFIG_HPS* to the CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-31Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASESimon Glass
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29treewide: Drop bootm_headers_t typedefSimon Glass
This is not needed and we should avoid typedefs. Use the struct instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-18cyclic: Use schedule() instead of WATCHDOG_RESET()Stefan Roese
Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
2022-07-01socfpga: arria10: Allow dcache_enable before relocationPaweł Anikiel
Before relocating to SDRAM, the ECC is initialized by clearing the whole SDRAM. In order to speed this up, dcache_enable is used (see sdram_init_ecc_bits). Since commit 503eea451903 ("arm: cp15: update DACR value to activate access control"), this no longer works, because running code in OCRAM with the XN bit set causes a page fault. Override dram_bank_mmu_setup to disable XN in the OCRAM and setup DRAM dcache before relocation. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01socfpga: arria10: Replace delays with busy waiting in cm_full_cfgPaweł Anikiel
Using udelay while the clocks aren't fully configured causes the timer system to save the wrong clock rate. Use sdelay and wait_on_value instead (the values used in these functions were found experimentally). Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-07-01config: Add Chameleonv3 configPaweł Anikiel
Add defconfig and Kconfig files for Google Chameleon V3 board Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-06-17arch: arm: socfpga: timer_s10: Override udelay for secure sectionDinesh Maniyam
Override __udelay() as 'always inlined' function so that PSCI code run in '__secure' section can call this delay function as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-05-23arm: socfpga: Add the terasic de10-standard boardHumberto Naves
Use the de10-nano files as templates for the de10-standard board. The files in qts directory are generated by quartus from the GHRD design. Signed-off-by: Humberto Naves <hsnaves@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de>
2022-04-12iopoll: Extend read_poll_timeout macro to support variable parametersAriel D'Alessandro
This macro currently supports only one parameter. Based on Linux iopoll, let's extend read_poll_timeout common API to allow multiple variable parameters. Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
2022-04-08spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to KconfigTom Rini
This is a little tricky since SoCFPGA has code to determine this as runtime. Introduce a guard variable for platforms to select if they have a static value to use. Then for ARCH_SOCFPGA, call cm_get_qspi_controller_clk_hz() and otherwise continue the previous behavior. Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-05Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
A big part is the DM pinctrl driver, which allows us to get rid of quite some custom pinmux code and make the whole port much more robust. Many thanks to Samuel for that nice contribution! There are some more or less cosmetic warnings about missing clocks right now, I will send the trivial fixes for that later. Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0 (secure images) support. Both features are unused at the moment, but I have an always-secure board that will use that once the DT lands in the kernel. On top of those big things we have some smaller fixes, improving the I2C DM support, fixing some H6/H616 early clock setup and improving the eMMC boot partition support. The gitlab CI completed successfully, including the build test for all 161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100 board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
2022-04-04spl: mmc: extend spl_mmc_boot_mode() to take mmc argumentAndre Przywara
Platforms can overwrite the weak definition of spl_mmc_boot_mode() to determine where to load U-Boot proper from. For most of them this is a trivial decision based on Kconfig variables, but it might be desirable the probe the actual device to answer this question. Pass the pointer to the mmc struct to that function, so implementations can make use of that. Compile-tested for all users changed. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Ley Foon Tan <ley.foon.tan@inte.com> (for SoCFPGA) Acked-by: Lokesh Vutla <lokeshvutla@ti.com> (for OMAP and K3) Reviewed-by: Simon Glass <sjg@chromium.org>
2022-04-01keymile: Move sourcing of common KconfigTom Rini
The way board/keymile/Kconfig is written protects the options there from being parsed on non-keymile platforms. We cannot however safely source this file from multiple locations. This does not manifest as a problem currently as there are no choice statements inside of this file (nor the sub-Kconfig files it sources). However, moving some target selection to one of these files exposes the underlying problem. Rework things so that we have this file sourced in arch/Kconfig. Cc: Holger Brunck <holger.brunck@hitachienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Holger Brunck <holger.brunck@hitachienergy.com>
2022-03-02armv8: Fix and simplify branch_if_master/branch_if_slaveAndre Przywara
The branch_if_master macro jumps to a label if the CPU is the "master" core, which we define as having all affinity levels set to 0. To check for this condition, we need to mask off some bits from the MPIDR register, then compare the remaining register value against zero. The implementation of this was slighly broken (it preserved the upper RES0 bits), overly complicated and hard to understand, especially since it lacked comments. The same was true for the very similar branch_if_slave macro. Use a much shorter assembly sequence for those checks, use the same masking for both macros (just negate the final branch), and put some comments on them, to make it clear what the code does. This allows to drop the second temporary register for branch_if_master, so we adjust all call sites as well. Also use the opportunity to remove a misleading comment: the macro works fine on SoCs with multiple clusters. Judging by the commit message, the original problem with the Juno SoC stems from the fact that the master CPU *can* be configured to be from cluster 1, so the assumption that the master CPU has all affinity values set to 0 does not hold there. But this is already mentioned above in a comment, so remove the extra comment. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-12-17arm: socfpga: arria10: Enable double peripheral RBF configurationTien Fong Chee
Double peripheral RBF configuration are needed on some devices or boards to stabilize the IO configuration system. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBFTien Fong Chee
This patch triggers warm reset to recover the MPFE NoC from corruption due to high frequency transient clock output from HPS EMIF IOPLL at VCO startup after peripheral RBF is programmed. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17arm: socfpga: arria10: Setting image magic value to romcode initswstate regTien Fong Chee
The romcode_initswstate register need to be set with FSBL_IMAGE_IS_VALID value if the current FSBL image is found valid, otherwise BootROM will look for next subsequent valid FSBL image when warm reset is triggered. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-30WS cleanup: remove SPACE(s) followed by TABWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-16Merge tag 'v2021.10-rc4' into nextTom Rini
Prepare v2021.10-rc4 Signed-off-by: Tom Rini <trini@konsulko.com> # gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # board/Arcturus/ucp1020/spl.c # cmd/mvebu/Kconfig # common/Kconfig.boot # common/image-fit.c # configs/UCP1020_defconfig # configs/sifive_unmatched_defconfig # drivers/pci/Kconfig # include/configs/UCP1020.h # include/configs/sifive-unmatched.h # lib/Makefile # scripts/config_whitelist.txt
2021-09-08lib: Drop SHA512_ALGO in lieu of SHA512Alexandru Gagniuc
SHA512_ALGO was used as a "either SHA512 or SHA384", although the implementations of these two algorithms share a majority of code. From a Kconfig interface perspective, it makes sense to present two distinct options. This requires #ifdefing out the SHA512 implementation from sha512.c. The latter doesn't make any sense. It's reasonable to say in Kconfig that SHA384 depends on SHA512, and seems to be the more polite way to handle the selection. Thus, automatically select SHA512 when SHA384 is enabled. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-09-04mmc: Rename MMC_SUPPORT to MMCSimon Glass
Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> [trini: Fixup some incorrect renames] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-25arm: socfpga: Enable Intel N5X device buildSiew Chin Lim
Add defconfig for N5X to support legacy, ATF and VAB boot flow. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25arm: socfpga: Add SPL for Intel N5X deviceSiew Chin Lim
Add SPL for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25ddr: altera: Add SDRAM driver for Intel N5X deviceTien Fong Chee
The DDR subsystem in Diamond Mesa is consisted of controller, PHY, memory reset manager and memory clock manager. Configuration settings of controller, PHY and memory reset manager is come from DDR handoff data in bitstream, which contain the register base addresses and user settings from tool. Configuration settings of memory clock manager is come from the HPS handoff data in bitstream, however the register base address is defined in device tree. The calibration is fully done in HPS, which requires IMEM and DMEM binaries loading to PHY SRAM for running this calibration, both IMEM and DMEM binaries are also part of bitstream, this bitstream would be loaded to OCRAM by SDM, and configured by DDR driver. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-25arm: socfpga: Changed misc_s10.c to misc_soc64.cSiew Chin Lim
Rename to common file name to used by all SOC64 devices. No functionality change. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25arm: socfpga: Add clock manager for Intel N5X deviceSiew Chin Lim
Add clock manager for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.hSiew Chin Lim
Move cm_get_mpu_clk_hz function declaration from individual device's clock manager header file to common clock_manager.h. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25arm: socfpga: Get clock manager base address for Intel N5X deviceSiew Chin Lim
Add N5X clock manager to socfpga_get_managers_addr function. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-24arm: socfpga: Add handoff data support for Intel N5X deviceTien Fong Chee
N5X support both HPS handoff data and DDR handoff data. Existing HPS handoff functions are restructured to support both existing devices and N5X device. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-24arm: socfpga: Add base address for Intel N5X deviceSiew Chin Lim
Reuse base_addr_soc64.h for Intel N5X device, the address is the same as Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-24arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.hSiew Chin Lim
Rename to common file name to used by all SOC64 devices and change "_S10_" to "_SOC64_" in base_addr_soc64.h. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-24arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux ↵Siew Chin Lim
function Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when OS booted from FIT image for Stratix 10 and Agilex. This flow is common for all Intel SOC64 devices. U-Boot will update 'fdt_addr' environment value based on FIT image in board_prep_linux function, and 'linux_qspi_enable' will refer to 'fdt_addr' environment value to retrieve the device tree node. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-02global: Convert simple_strtoul() with hex to hextoul()Simon Glass
It is a pain to have to specify the value 16 in each call. Add a new hextoul() function and update the code to use it. Add a proper comment to simple_strtoul() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-06-11common: fit: Update board_fit_image_post_process() to pass fit and node_offsetLokesh Vutla
board_fit_image_post_process() passes only start and size of the image, but type of the image is not passed. So pass fit and node_offset, to derive information about image to be processed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-05-24treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún
This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-08arm: socfpga: smc: Add function to get usercodeSiew Chin Lim
Add function to send mailbox command via SMC to get usercode from SDM. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08arm: socfpga: Changed to store QSPI reference clock in kHzSiew Chin Lim
Changed to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex. This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4 bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI reference clock. Due to limited bits, QSPI reference clock frequency is converted to kHz from Hz. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-04-08arm: socfpga: Move Stratix10 and Agilex clock manager common codeSiew Chin Lim
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08arm: socfpga: Restructure Stratix10 and Agilex handoff codeSiew Chin Lim
Restructure Stratix10 and Agilex handoff code to used by all SOC64 devices, in preparation to support handoff for Diamond Mesa. Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c which contains the generic function to parse the handoff data. Update system_manager_soc64.c to use generic handoff function in wrap_handoff_soc64.c. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08arm: socfpga: Rearrange sequence of macros in handoff_soc64.hSiew Chin Lim
Rearrange sequence of macros in handoff_soc64.h without any functionality change. In preparation for Stratix10 and Agilex handoff function restructuring. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.cSiew Chin Lim
Rename to common file name to used by all SOC64 devices. No functionality change. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.cSiew Chin Lim
Rename to common file name to used by all SOC64 devices. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08arm: socfpga: Rename Stratix10 and Agilex handoff common macrosSiew Chin Lim
Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from S10_HANDOFF to SOC64_HANDOFF. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08arm: socfpga: Move Stratix10 and Agilex SPL common codeSiew Chin Lim
Move Stratix10 and Agilex SPL common code to spl_soc64.c. We are in preparation for new n5x device support. No functional change in this patch. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-03-29Merge tag 'v2021.04-rc5' into nextTom Rini
Prepare v2021.04-rc5
2021-03-23arm: socfpga: Only do 'is OS booted from FIT' checking when VAB is enabledSiew Chin Lim
Check CONFIG_SOCFPGA_SECURE_VAB_AUTH before perform 'is OS booted from FIT' checking in board_prep_linux function. And, fix typo of CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE. CONFIG_FIT will be enabled in both ATF and VAB boot flow, thus, board_prep_linux function will always be called by both ATF and VAB boot flow. board_pre_linux function will do 'is OS booted from FIT' checking, and it will be called before board_fit_image_post_process function. VAB boot flow expects the OS is always booted from FIT and with VAB signed cerfiticate because the VAB authentication is implemented in board_fit_image_post_process function. So, VAB needs the 'is OS booted from FIT' checking in board_pre_linux function. However, for ATF boot flow, it is not a requirement that the OS must always booted from FIT. The OS can be booted from individual Image and kernel dtb file. Thus, we should not do 'if OS is booted from FIT' checking in board_prep_linux function. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-08-03 23:02:56 +0000