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commit 2764be4345 ("remoteproc: uclass: Add methods to load
firmware to rproc and boot rproc") selects FS_LOADER in Kconfig
and this breaks R5 build for some defconfigs across multiple platforms.
Enabling CONFIG_SPL_FS_LOADER does not help for all cases.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Tested-by: MD Danish Anwar <danishanwar@ti.com>
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AVS driver was getting probed with base device tree, which
leads i2c of derivative board (AM68) in bad state.
Moving AVS probe after detection of right device tree.
Fixes: eaa184009775 ("arm: k3: j721s2: Enable AVS")
Reported-by: Minas Hambardzumyan <minas@ti.com>
Cc: Manorit Chawdhry <m-chawdhry@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
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Enable probing of AVS node in R5 SPL.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
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On AM62A and AM62P devices, it is possible to route Main ESM error
events to MCU ESM. MCU ESM high error output can trigger the reset
logic to reset the device. So, for these devices we have Main ESM and
MCU ESM nodes in the device tree. Add functions to probe these nodes
if CONFIG_ESM_K3 is enabled.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
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Setup page table, data cache and reserve memory for SPL as a precursor
to enable splash screen for AM62P platform
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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The number of DDR controllers to be initialised and used should depend
on the device tree with the constraint of the maximum number of
controllers the device supports. Since J784S4 has multiple (4)
controllers, instead of hardcoding the number of probes, move to
depending on the device tree UCLASS_RAM nodes present.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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The number of DDR controllers to be initialised and used should depend
on the device tree with the constraint of the maximum number of
controllers the device supports. Since J721S2 has multiple (2)
controllers, instead of hardcoding the number of probes, move to
depending on the device tree UCLASS_RAM nodes present.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
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This adds FS and raw boot mode support similar to other K3 platforms
with the default boot mode being filesystem.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Enable Quality of Service blocks for Display Subsystem DSS0 and DSS1
and Main R5F core by servicing their traffic from RT queue.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Replace all the fsstub occurences with tifsstub to avoid new
terminology and resulting confusion.
Suggested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
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Entry for physical address 0x500000000 in memory map table for MMU
configuration is spilling over and inadvertently making DDR available at
higher address (above 4GB address space) get mapped as device memory
(nGnRnE).
Fix this by adjusting entry size. Tested on AM62A SK. Before this patch:
=> time crc32 0x881000000 0x20000000
crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca
time: 1 minutes, 14.716 seconds
After patch:
=> time crc32 0x881000000 0x20000000
crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca
time: 2.710 seconds
Acked-by: Andrew Davis <afd@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
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Adds the default config for K3_OPP_LOW in J7200
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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Adds a check for K3_OPP_LOW config and will change MPU freq/voltage
and msmc clock according to opp_low spec.
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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Update ARM64 MMU entries for J722S to support early remoteproc
boot requirements.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Introduce the basic files needed to support the TI J722S family of SoCs.
Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Introduce the basic functions and definitions needed to properly
initialize TI J722S family of SoCs.
Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Introduce support for J722S SoC.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Include the part number for TI's j722s family of SoC
to identify it during boot.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Read the max temperature for the SoC temperature grade from the hardware
and change the critical trip nodes on each thermal zone of FDT at
runtime so they are correct with the hardware value for its grade.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240208092951.11769-1-francesco@dolcini.it/#t]
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
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AM62x SoC is available in multiple temperature grade:
- Commercial: 0° to 95° C
- Industrial: -40° to 105° C
- Automotive: -40° to 125° C
Add a new function that returns the am62 max temperature value
accordingly to its temperature grade in Celsius.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240208092951.11769-1-francesco@dolcini.it/#t]
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
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Add two functions, one which returns the SoC speed grade and one
which returns the SoC operating temperature range.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240117101743.3955852-1-max.oss.09@gmail.com/T/#t]
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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mach-k3/am625_fdt.c does fdt fixup depending on fields in the device
identification register. Move the accessors to the device identification
register as inline functions into the am62_hardware.h header, so that
they can be used for other functionality.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240117101743.3955852-1-max.oss.09@gmail.com/T/#t]
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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RC Release 09.01.00.008
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Enable AVS in config and probing of AVS node.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
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RC Release 09.01.00.006
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After leaving the Partial-IO mode or other deep sleep states, the IO
isolation needs to be removed. This routine is shared by at least am62,
am62a and am62p.
The original function for testing was developed by
Akashdeep Kaur <a-kaur@ti.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
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AM642 SoC supports booting from GPMC NAND device.
Define boot device for it.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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Add spl_mmc_boot_mode() to help distinguish eMMC raw boot mode.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Change spl_enable_dcache so it also enable icache on SPL
initialization for the main domain part of the boot flow. This
improves bootloader booting time.
Upstream-Status: Submitted [https://lore.kernel.org/u-boot/20231113190721.1841748-1-jpaulo.silvagoncalves@gmail.com/]
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
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Introduce the basic files needed to support the am62px family of SoCs
Co-developed-by: Hari Hagalla <hnagalla@ti.com>
Signed-off-by: Hari Hagalla <hnagalla@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Introduce the basic functions and definitions needed to properly
initialize Ti's am62p family of SoCs
[bb@ti.com: rebased on TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Currently for the K3 generation of SoCs there are more SoCs that utilize
the split firmware approach than the combined DMSC firmware. Invert the
logic to avoid adding more and more SoCs to this list.
[bb@ti.com: rebased on TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Include the clock and lpsc tree files needed for the wkup spl to
initialize the proper PLLs and power domains to boot the SoC.
[bb@ti.com: rebased to TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Include the part number for TI's am62px family of SoCs so we can
properly identify it during boot
[bb@ti.com: rebased to TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
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BOOT_DEVICE_SPINAND and BOOT_DEVICE_UART have same index of 0x7, this
leads to attempting SPINAND boot during UART boot. Fix this by
allocating unique value to BOOT_DEVICE_SPINAND. While at that move it
out of unused list as SPINAND boot is very much supported on AM62x SoCs.
Fixes: 8c7827f522b0 ("arm: mack-k3: am62x: Add SPI NAND as a boot device")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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commit c97ed47b42364f6b8b387aac331ab111480a8075 upstream.
The following checks are more reasonable as the previous logs were a bit
misleading as we could still get the logs that the authetication is
being skipped but still authenticate. Move the debug prints and checks
to proper locations.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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commit 44dab785809ac1ef808eacf141abbc75ac89ddba upstream.
Fix regression occurred during refactoring for the mentioned commit.
Fixes: bd6a24759374 ("arm: mach-k3: security: separate out validating binary logic")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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commit bd6a247593742596a83d6e36bebb45cb78a4017e upstream.
K3 GP devices allows booting the secure binaries on them by bypassing
the x509 header on them.
ATF and OPTEE firewalling required the rproc_load to be called before
authentication. This change caused the failure for GP devices that
strips off the headers. The boot vector had been set before the headers
were stripped off causing the runtime stripping to fail and stripping
becoming in-effective.
Separate out the secure binary check on GP/HS devices so that the
boot_vector could be stripped before calling rproc_load. This allows
keeping the authentication later when the cluster is on along with
allowing the stripping of the binaries in case of gp devices.
Fixes: 1e00e9be62e5 ("arm: mach-k3: common: re-locate authentication for atf/optee")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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commit 1e00e9be62e54e87673ad03b77fb5ebe4ac270b1 upstream.
For setting up the master firewalls present in the K3 SoCs, the arm64
clusters need to be powered on.
Re-locates the code for atf/optee authentication.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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Enumerate SPI NAND as a boot device for j784s4 evm at 0x5.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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RC Release 09.00.00.008
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AM62x SoC is available in multiple variant:
- CPU cores (Cortex-A) AM62x1 (1 core), AM62x2 (2 cores), AM62x4 (4 cores)
- GPU AM625x with GPU, AM623x without GPU
- PRU (Programmable RT unit) can be present or not on AM62x2/AM62x4
Remove the relevant FDT nodes by reading the actual configuration
from the SoC registers, with that change is possible to have a single
dts/dtb file handling the different variant at runtime.
While removing GPU node and CPU nodes also the watchdog node
in the same Module Domain is removed.
A similar approach is implemented for example on i.MX8 and STM32MP1 SoC.
Upstream-Status: Backport [70aa5a94d451cc4beb7345f8fc1e777668acb816]
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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ft_system_setup cannot be enabled on SoC without msmc sram otherwise
fdt_fixup_msmc_ram function fails causing system reset.
Fix by moving fdt_fixup_msmc_ram to common_fdt.c file and creating
SoC (AM654, J721E and J721S2) specific files for fdt fixups.
This change was verified to not change anything on any existing board
(all the J721S2, AM654 and J721E boards requires it,
none of the remaining k3 boards require it).
Upstream-Status: Backport [7b7288df3415c7faa4a305b814bb8932876b2149]
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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This reverts commit a3c24a8e975102aec314dc44271e30dbe393f756.
Revert this patch because it was upstreamed in a slightly different way.
The upstreamed patch will be applied.
Upstream-Status: Inappropriate
Revert a downstream patch that will be substituted by an upstream patch
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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Add bitmasks and shifts for PRU and GPU.
Upstream-Status: Backport [de3db252314eaa942b7aa6abf37a62e866821fe5]
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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AM62x SoC is available in multiple variant with a different
amount of CPU cores (Cortex-A) available, AM62x1, AM62x2, AM62x4
have respectively 1, 2 or 4 cores.
Update the FDT with the actual core count as read from the SoC registers,
with that change is possible to have a single dts/dtb file handling
the different variant at runtime.
A similar approach is implemented for example on i.MX8 and STM32MP1 SoC.
Upstream-Status: Submitted [https://lore.kernel.org/all/20230712134730.30229-4-francesco@dolcini.it]
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
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Add register address and relevant bitmasks and shifts.
Allow reading these information:
- device identification
- number of cores (part of device identification)
- features (currently: PRU / no PRU)
- security
- functional safety
- speed grade
- temperature grade
- package
Upstream-Status: Submitted [https://lore.kernel.org/all/20230712134730.30229-3-francesco@dolcini.it]
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
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This adds initial support for the Toradex Verdin AM62 Quad 1GB WB IT
V1.0A module. They are strapped to boot from their on-module eMMC.
U-Boot supports booting from the on-module eMMC only, DFU support is
disabled for now due to missing AM62x USB support.
Boot sequence is:
SYSFW ---> R5 SPL (both in tiboot3.bin) ---> ATF (TF-A) ---> OP-TEE
---> A53 SPL (part of tispl.bin) ---> U-boot proper (u-boot.img)
Upstream-Status: Pending
V2 has been sent [1] and a re-based V3 will be sent once the upstream
TI stuff sufficiently stabilizes.
[1] https://lore.kernel.org/all/20230612205444.363727-4-marcel@ziswiler.com
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Fix second mux option of clkout0 which should really be
DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10
rather than twice the same according to [1].
[1] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html#clocks-for-board0-device
Upstream-Status: Submitted [https://lore.kernel.org/all/20230612205444.363727-3-marcel@ziswiler.com]
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
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K3 devices have some firewalls set up by ROM that we usually remove so
that the development is easy in HS devices.
While removing the firewalls disabling a background region before
disabling the foreground regions keeps the firewall in a state where all
the transactions will be blacklisted until all the regions are disabled.
This causes a race for some other entity trying to access that memory
region before all the firewalls are disabled and causes an exception.
Since there is no guarantee on where the background regions lie based on
ROM configurations or no guarantee if the background regions will allow
all transactions across the memory spaces, iterate the loop twice removing
the foregrounds first and then backgrounds.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Tested-by: Kamlesh Gurudasani <kamlesh@ti.com>
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