Age | Commit message (Collapse) | Author |
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BUG=chromium-os:23496
TEST=build and boot on Waluigi, Cardhu by enabling
CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT.
odification of the work done by:
a. Jimmy Zhang <jimmzhang@nvidia.com>
b. Yen Lin <yelin@nvidia.com>
c. Wei Ni <wni@nvidia.com>
Change-Id: If2fa63ccd23341694955bca25fb5cfc4a8a805ad
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13800
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warmboot_avp.h needs to be present in include/arch-tegra
in order to use it for Tegra3.
BUG=chromium-os:23496
TEST=build for Seaboard
Change-Id: I3f369194e4002e8257c9d2ff37253bc20733138d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/15394
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BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: I6d26502d1ecc393b266ffe06b540f59c595e19ae
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14811
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BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: Ifa06f941798ff242197dcd31f4091567d91fe4b2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14810
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BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: I74bb2418ab996e362060351de3ba7efd538ffd87
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14809
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BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: I20ac75c71d86d65ff422ff3f4f966a69718f4f91
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14808
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These registers would be useful for the warmboot code.
BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: I58f52b6b8653d72b2e842ee44bdf3632eff304a2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14690
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Would be useful for the warmboot code.
BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: I271f6cdcc0248337e516c2c32014c6ec4f08fb15
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14689
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These registers would be useful for the warmboot
code.
BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: I8da1ed3a382e1b65247236cb19f527f81d8ecaac
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14688
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BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi
Change-Id: Iacd6fdb178afbfdb978dbe53bbe2766916bf26f9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14685
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BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: I32dbfa02ac1d6954b3a7e515914fbc0b6695f98b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14683
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split the LP0 code for tegra2 into common
LP0 code and chip specific warm boot code
BUG=chromium-os:23496
TEST=build for Seaboard
Change-Id: Ie04bf9ac17482a37afd0f4515dc3aafeb4f48ae7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/15883
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This reverts commit 4c7502242627f64d91432cb4958be5f93f65fbff
Don't think this is the cause of http://code.google.com/p/chromium-os/issues/detail?id=26116, but it was in the same batch so I'm reverting in the process.
Change-Id: Icc013ced6c22e29d569ee4ca8ef73522154ec1a8
Reviewed-on: https://gerrit.chromium.org/gerrit/15561
Reviewed-by: Brian Harring <ferringb@chromium.org>
Tested-by: Brian Harring <ferringb@chromium.org>
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This reverts commit 9a3fbb5f0b02382c7abe0cf40a4f08abbf269d05
Broke tegra2: http://code.google.com/p/chromium-os/issues/detail?id=26116
Change-Id: I7d35211c6ebce7a10750cb1033c6f8ba9a0f63bc
Reviewed-on: https://gerrit.chromium.org/gerrit/15560
Reviewed-by: Brian Harring <ferringb@chromium.org>
Tested-by: Brian Harring <ferringb@chromium.org>
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move away from the current method, where we add wb_end() immediately
after wb_start() and then use the function addresses to calculate the
WB code size. Add a .lds script to expose __wb_end after wb_start() in
the .text section and then reference this variable in the WB size
calculation code.
BUG=chromium-os:23496
TEST=build on Seaboard. Verified that uboot.map has the correct address
assigned to __wb_end and that LP0 works reliably.
Change-Id: I170277f00b450d38063018453faf44d5a38abaaa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14682
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split the LP0 code for tegra2 into common
LP0 code and chip specific warm boot code
BUG=chromium-os:23496
TEST=build for Seaboard
Change-Id: Id9756c08f61502affa8beee636d883d01468e6ec
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13799
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As clock source for graphics related clocks is different
for Tegra2 and Tegra3, define it under platform specific
directories.
BUG=chromium-os:23496
TEST=Build ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi.
Original work by -
Mayuresh Kulkarni <mkulkarni@nvidia.com>
Change-Id: I6cee11df5e75eaf3836565c4fa4f3ab3e45d8cac
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14700
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This allows booting without a display, mostly as a way of calculating
the time that LCD init and maintenance costs us. Perhaps we might
integrate the lcd and video APIs within U-Boot - it would be a much
nicer solution. With that in mind I feel it is not work refactoring
this into three separate (lcd, video, none) files to implement the
display API.
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: Iea4656f8939f7f2fd78292827091de4ee379954b
Reviewed-on: https://gerrit.chromium.org/gerrit/13369
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
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BUG=chromium-os:23496
TEST=built Seaboard and Waluigi OK
Signed-off-by: Tom Warren <twarren@nvidia.com>
Change-Id: I954cdb71eb80a3cf48f44b9a7183a2cafcb7755b
Reviewed-on: https://gerrit.chromium.org/gerrit/12442
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
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Some clocks cannot be set to the final value until we have the fdt
and know what PLLP should be set to. For now the only example is
coresight - so this adds a call to update this clock once the A9
is up and running with the fdt.
BUG=chromium-os:23496
TEST=build and boot on Seaboard, T33, Kaen
Change-Id: I7a07306cfb0a24cec4dcdb08cac78659a1afc73f
Reviewed-on: https://gerrit.chromium.org/gerrit/12251
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Since PLLP can be set to two different values, make it a parameter
to the function that sets up the PLLs.
BUG=chromium-os:23496
TEST=build and boot on Seaboard, T33, Kaen
Change-Id: I81ccc1cc3356796793ec2dd4ab22ed7fbd52f01d
Reviewed-on: https://gerrit.chromium.org/gerrit/12245
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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This function is better off in architecture code than board code.
This is quite an invasive change unfortunately.
BUG=chromium-os:23496
TEST=build and boot on Seaboard, T33, Kaen
Change-Id: I17764b134c25b684666d2c0fae2d255ac80e61b1
Reviewed-on: https://gerrit.chromium.org/gerrit/12244
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
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Signed-off-by: Tom Warren <twarren@nvidia.com>
BUG=chromium-os:21033
TEST=built Seaboard & Waluigi OK. Booted my Waluigi to cmd prompt OK.
MMC, SPI and I2C still work fine, as does UART.
More can be done at a later date to cleanup AP20.c for T30 (and
rename/move it, since AP20 is a T2x name) and use new T30 V/W clock
enables/resets/sources/etc.
Change-Id: Ia3a86c519481fffde6926e1fece1dcf898d199c9
Reviewed-on: https://gerrit.chromium.org/gerrit/11911
Tested-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Tom Warren <twarren@nvidia.com>
BUG=chromium-os:21033
TEST=Built and booted OK on my Waluigi. UART is OK, mmc, spi, i2c OK.
Note that this is only valid with CONFIG_SYS_PLLP_BASE_IS_408MHZ.
No affect on Tegra2. Seaboard builds fine, BTW.
Change-Id: I05a367afd1e78a2170d7308a658ce64017850ca0
Reviewed-on: https://gerrit.chromium.org/gerrit/11811
Tested-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
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Signed-off-by: Tom Warren <twarren@nvidia.com>
BUG=none
TEST=built Seaboard and Waluigi AOK
Change-Id: Ia860abf5ef3af66b3a39d4c57192455986b7a4f4
Reviewed-on: https://gerrit.chromium.org/gerrit/11704
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
Commit-Ready: Doug Anderson <dianders@chromium.org>
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BUG=chromium-os:21033
TEST=run `sf erase, write` and then `sf read` on seaboard
verify the data it reads from SPI flash matches that it writes to
Change-Id: I1b04afa4b54738cd93be29b70f428bdc3e6b234f
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/11472
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
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BUG=chromium-os:21033
TEST=emerge-{tegra2_seaboard,waluigi} chromeos-u-boot
Change-Id: Icee2c26f36937e96c24318979179ba3a0cbfc09c
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/11597
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Signed-off-by: Tom Warren <twarren@nvidia.com>
BUG=none
TEST=built Seaboard and Waluigi OK. Booted Waluigi OK.
Change-Id: I1bfbe03945d7dae44e0840349b9698fc08cef07d
Reviewed-on: https://gerrit.chromium.org/gerrit/11504
Tested-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
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Signed-off-by: Tom Warren <twarren@nvidia.com>
BUG=none
TEST=build Seaboard and Waluigi AOK
Change-Id: Id8e7227de7898bb9d117bf8d0f293ee5da7dc501
Reviewed-on: https://gerrit.chromium.org/gerrit/11506
Tested-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
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Set CPU clock initially to 312Mhz; once CPU voltage is
raised, CPU clock will then be raied to 1.2GHz (for T25)
or 1.0GHz (for T20).
BUG=chrome-os-partner:5914
TEST=Build and test on Seaboard
Change-Id: I0c95a1df6b87c896daca8c03c9dc33b245764621
Reviewed-on: https://gerrit.chromium.org/gerrit/11199
Tested-by: Yen Lin <yelin@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Doug Anderson <dianders@chromium.org>
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BUG=chromium-os:21033
TEST=build seaboard successfully
Change-Id: Idbfbdbf0bdb1070f4a2b5f8205c1caff6ef0c811
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/11471
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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BUG=chromium-os:21540
TEST=Able to talk to MMC1 on Waluigi w/ future config changes.
Specifically:
1. mmcinfo 0 - works (shows info)
2. mmcinfo 1 - works (shows info)
3. mmc rescan 1; mmc part 1 - works (shows partitions)
Change-Id: I730d3b91088f20ccf7ca20f3f31f7d59514af243
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/10661
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Previously the exported function definitions for pmu.c were split
among board.h, emc.c, and the architecture specific pmu.h. Create a
non-architecture-specific pmu.h and put them there.
NOTE: The arch/pmu.h file should probably be removed
eventually in favor of the device tree, since it really
just defines how a particular PMU is used by a particular
family of board.
BUG=chromium-os:21540
TEST=Compiled for seaboard
Change-Id: Ia026e3ff3f1f465be629cc8a348879d2d1564686
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/10456
Reviewed-by: Tom Warren <twarren@nvidia.com>
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These two functions were only used in pmu.c, so there was no
reason for them to be in the header file. They probably should
be moved elsewhere eventually, but this is a better location
than they were.
BUG=None
TEST=Compiled
Change-Id: Ia13cfd0fd828589862bfd555c3a34d3b6b4bda1c
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/10455
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
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The GPIO definitions for Tegra2 were incorrectly matched up with Tegra2.
The layout is actually different, so GPIOs beyond port D do not work.
This separates out the GPIO headers again, so that Tegra2 and Tegra3 have
separate structure definitions.
BUG=None
TEST='vboot_test gpio' on Kaen; see that it responds to google rec, power, lid
correctly
Change-Id: I8540a87c8faa7179c8f0d44ef3f18b3c576392cc
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/9847
Reviewed-by: Bryan Freed <bfreed@chromium.org>
Tested-by: Bryan Freed <bfreed@chromium.org>
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The pinmux functions for Tegra3 are quite different from Tegra2, since
we can adjust the setting for each individual pin. We try to keep the
same top-level interface where possible.
(sjg@chromium.org tidied up for 80cols)
BUG=chromium-os:21033
TEST=build and boot on Seaboard
Change-Id: I5bb109e73dc69c3424fe71978417b3f2b210a540
Reviewed-on: http://gerrit.chromium.org/gerrit/8692
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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We need these functions to set up the power chip during low-level init.
BUG=chromium-os:21033
TEST=build and boot on Seaboard
Change-Id: I69b9d3c12581e0a71db39b031b9ea2ef4ec184bf
Reviewed-on: http://gerrit.chromium.org/gerrit/8696
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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This header supplies the necessary T30 parts for GPIO access. Since the
Tegra3 just adds new fields and they will use the same driver, we move
the structure into the common header.
BUG=chromium-os:21033
TEST=build and boot on seaboard
Change-Id: I3ebf128358d118fc43469ffff839af5027bc6472
Reviewed-on: http://gerrit.chromium.org/gerrit/8693
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Tegra3 has a number of additional registers in the clock/reset
controller.
BUG=chromium-os:21033
TEST=build and boot on Seaboard
Change-Id: I34b0e66b2843fd2c2d4ab29fa1b4247b5ead7abf
Reviewed-on: http://gerrit.chromium.org/gerrit/8697
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Change-Id: If944692337a24b1720b07460d1490b8cd15e7ef9
Reviewed-on: http://gerrit.chromium.org/gerrit/8703
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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The 216MHz PLLP is not always wanted - this adds support for 408MHz which
will be used on T30.
BUG=chromium-os:19004
TEST=build and boot on Seaboard
Change-Id: I4c053b5a9db4efb7b926ad2c9072f392d24033c9
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/8689
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
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This adds ap20_get_num_cpus() which returns the number of CPUs in the
system, and adjusts a clock function to use it.
BUG=chromium-os:19004
TEST=build and boot on Seaboard
Change-Id: If7b56a2cecfb3d856308cac43dfcb32d3f1fef14
Reviewed-on: http://gerrit.chromium.org/gerrit/8688
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Much of the GPIO header is common between T20 and T30, so move it into a common
file to avoid duplication.
BUG=chromium-os:19004
TEST=build and boot on seaboard
Change-Id: Id8ca0bad87f8b5b27f00acf31081a52d88f1d824
Reviewed-on: http://gerrit.chromium.org/gerrit/8679
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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The T20 and T30 i2c peripherals can use the same driver. This renames the
driver and puts the header file into the common arch-tegra directory.
BUG=chromium-os:19004
TEST=build and boot on seaboard
Change-Id: Iec76bb27340db037fdc67b3509fd35f7b5aaeb34
Reviewed-on: http://gerrit.chromium.org/gerrit/8643
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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The flow controller exists in both T20 and T30, so move it into the
tegra-common directory.
BUG=chromium-os:19004
TEST=build and boot on seaboard
Change-Id: If6b7fea7dc3969139dfeadcf856b8d43d7eb875a
Reviewed-on: http://gerrit.chromium.org/gerrit/8642
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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This is needed by both T2x and T3x.
BUG=chromium-os:19004
TEST=build and boot on seaboard
Change-Id: I896719336126346c540bbae0c0559302189460ef
Reviewed-on: http://gerrit.chromium.org/gerrit/8641
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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This is needed by both T2x and T3x.
BUG=chromium-os:19004
TEST=build and boot on seaboard
Change-Id: I71d2cb747d97d8bd4d6c8c03037bb94614a6017f
Reviewed-on: http://gerrit.chromium.org/gerrit/8640
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Allow redirection of console output prior to console initialisation to a
temporary buffer.
To enable this functionality, the board (or arch) must define:
- CONFIG_PRE_CONSOLE_BUFFER - Enable pre-console buffer
- CONFIG_PRE_CON_BUF_ADDR - Base address of pre-console buffer
- CONFIG_PRE_CON_BUF_SZ - Size of pre-console buffer (in bytes)
The pre-console buffer will buffer the last CONFIG_PRE_CON_BUF_SZ bytes
Any earlier characters are silently dropped.
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Change-Id: I3c4caad276b9e981ebea0a0fb79d85ee3a3bcb7d
Reviewed-on: http://gerrit.chromium.org/gerrit/8686
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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This is needed by both T2x and T3x.
BUG=chromium-os:19004
TEST=build and boot on seaboard
Change-Id: I27113943da1e2dd3045f139938bc0c45998a0170
Reviewed-on: http://gerrit.chromium.org/gerrit/8639
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org>
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