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The i.MX 7 detection taken from upstream U-Boot adds a new macro
MXC_CPU_MX7S. The downstream U-Boot still has one runtime occurence
which currently checks for MXC_CPU_MX7D only. Fix this SoC detection
to detect MXC_CPU_MX7S too.
Note: While the GPT timer is available on i.MX 7, it is currently
not configured (CONFIG_GPT_TIMER). Instead, the CPU internal
syscounter timer is currently used (CONFIG_SYSCOUNTER_TIMER).
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Read the number of cores in the fuses to distinguish between
the dual and solo versions.
Tested on a mx7d sabresd and on a mx7solo warp7.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit e25a0656bac63c5fcd20ef4313dc09c409fc512d)
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add the peripherals/masters definitions and registers base addresses
for mx7d RDC. Enable the RDC driver by setting CONFIG_MXC_RDC.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Code mostly ported from imx-kobs-5.3.
MTD partitioning is set accordingly.
writebcb: Write Boot Control Block (FCB and DBBT)
writeboot: Write bootloadder
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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This reverts commit 3b548a3ddf03dcbb646912ef7bbdd3cdb2daf81a.
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Add the peripherals/masters definitions and registers base addresses
for mx7d RDC. Enable the RDC driver by setting CONFIG_MXC_RDC.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Remove PCIe, xPU power, PL310 L2 Cache for MX6UL.
Update FEC MAC address, WDOG settings, USDHC clock rate.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Since the system counter driver will also be used by mx6ul, move
this timer driver to imx-common and rename it as syscounter.c
For mx6ul and mx7, configurations are used for choose the GPT timer
or system counter timer (default).
GPT timer: CONFIG_GPT_TIMER
System counter timer: CONFIG_SYSCOUNTER_TIMER
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime.
The 0x64 is defined as i.MX6Ul CPU type value in RM, but the value
has been occupied by i.MX6D as a dummy CPU type.
So we also need change i.MX6D to a invalid value 0x67.
Signed-off-by: Ye.Li <B37916@freescale.com>
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* Correct daisy chain settings for LPSR iomux controller
* Add IOMUX_LPSR_SEL_INPUT_OFS only when pad is identified
to be part of lpsr-iomuxc domain
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
(cherry picked from commit e4fd6550b3e5458aaf5049a7e6a12d6e4443c53a)
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* For IOMUXC LPSR pads when daisy chain register needs to be set the
result offsets for sel_input register is incorrect as base address is
0x302C0000 and the passed offset does not resolve to the intended input
sel pad register; input sel base offset should start in 0x30330000.
* Add an addiotional fixed offset of 0x70000 to address the
input sel offset:
INPUT_SEL = 0x302C0000 + 0x70000 + sel_input_ofs.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 5d4612613eb2e85f1929d8cf5cb6aac6ba9e5fd7)
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is_mx6dqp should be only applied for MX6
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit d860559f7913f16f7cb248f7b44140e8c1aa3ee9)
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We should print "MX6QP Rev1.0", but not "MX6Q Rev2.0".
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 64b2be69835af80e0dbc151175617942683a3167)
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Add thermal driver for mx7
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add i2c support for i.MX7D.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit b52cb9d40e71305b7a11b0bbc68fddd8e84e3b17)
Conflicts:
drivers/i2c/mxc_i2c.c
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Modify the GPT common platform driver for mx7 which only use 24Mhz
OSC as clock source.
Note: at default, the mx7d will use system counter as timer. The GPT
is disabled.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 6e250796d6a07d84093eeae96e5a6e4c593cdb0b)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Since mx7d introduces some LPSR IOMUX pins, add new base to IOMUX v3
driver for these LPSR pins.
This patch also include commit
b83bb7b6cf26a4bb8983ae89c284fb4018c89870
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 8aa92b831955c968f802286de561825227e761ce)
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Introduce a new cpu type MXC_CPU_MX7D and relevant functions for mx7d.
Implement the soc.c for various system level functions like:
temperature check, arch init, get mac fuse, boot mode get/apply, etc.
Additional, enable building imx common platform files for mx7d.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 47d65aa6bdd109fd9141b5a5d64ab9deeb9dd2b3)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
Makefile
arch/arm/cpu/armv7/Makefile
arch/arm/imx-common/cpu.c
arch/arm/include/asm/arch-imx/cpu.h
arch/arm/include/asm/imx-common/boot_mode.h
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From i2c spec, if device pull down the SDA line that causes
i2c bus dead, host can send out 9 clock to let device release
SDA.
But for some special device like pfuze100, it pull down SDA line
and the solution cannot take effort.
The patch just add NACK and STOP signal after 8 dummy clock, and pmic
can release SDA line after the recovery. Test case catch 375 times of
i2c hang, and all are recovered.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit 53118db42d201d36ca9067b4bb0e2702399e100b)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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The kernel may break the display pipeline at boot stage and
introduce various display artifacts, so let's disable mxsfb
in uboot when necessary.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 539b8416299ec1ae3f57f866dd3f016bdfaa6875)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add gis module, current gis is support vadc input.
Add power down function to lcdif driver.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit a007b00dd8ef9f773dfdebef0b1deb0990281793)
Conflicts:
drivers/video/Makefile
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The RDC driver provides interfaces for setting peripherals and masters
at BSP initialization, before using the peripherals driver. Another
interfaces for lock/unlock RDC semaphore and permission check.
The driver assumes boot CPU which runs u-boot is in Domain 0
(default setting on boot). Users should not set it to other domains.
The peripherals ID and masters ID may change on different chip, each
should provide definitions of the IDs and be included in "imx-rdc.h".
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 964b2672bfbec14629f5767e59e73fd3bb185e3a)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
arch/arm/imx-common/Makefile
arch/arm/include/asm/arch-mx6/imx-regs.h
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Debug monitor will print out last failed AXI access info when
system reboot is caused by AXI access failure, only works when
debug monitor is enabled.
Enable this module on i.MX6SX.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit df6ac8531d498021ed379c74fc1847bd2cec7179)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
arch/arm/include/asm/arch-mx6/imx-regs.h
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This patch is from two commits:
1.
748eac71fde78aa0c2e8cb3a3bab94bd994c06f5
ENGR00315499-5: Support i.MX6 1.2GHz via LDO bypass
Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz,
enable LDO bypass and setup PMIC voltages. LDO bypass is dependent
on the flatten device tree file.
2.
93d457e4c601ee5266bc30b7dfa5fa1bbfa8500a
MLK-9891-1: ARM: imx6: split WDOG_B setting from set_anatop_bypass() function
We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now
on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to
reboot whole board, so split these code to independent function so that board file
can call it freely.
Board code is not included, board ldo bypass code will be in bsp update code.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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The environment variable was called bootargsm4, which is somewhat
incongruent with the boot command name "m4boot". Rename the bootargs
environment variable for Cortex-M4 to m4bootargs.
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Allow to boot eCos, MQX and bare-metal firmwares to boot on the
secondary Cortex-M4. The boot code is equal for all those firmware
types, the argument register will be set to 0 and the code will
jump to the specified entry point directly.
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Move entry point is Thumb2 check just after reading the entry point
from the FIT image.
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Include vf610m4bootldr, a mini boot loader for the Cortex-M4 CPU
inside Freescale Vybrid SoC. The mini loader enables caches and
copies the pointer to the device tree from the platform specific
argument register (PERSISTENT_ARG1) to the Cortex-M4 r2 register,
where the Linux kernel expects the pointer. The mini loader hence
essentially takes over the parts of the m4boot command which can
not be done from the Cortex-A5 main CPU.
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Add m4boot command which allows to boot FIT images on the Cortex-M4
kernel. The command currently only supports FIT image, which allows
to provide entry point and load addresses for all boot artifacts.
Currently, the Cortex-M4 mini loader needs to be loaded manually
to Kernel loadaddr - 0x80 (e.g. 0x8f000000, if kernel is loaded at
0x8f000080).
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The ipu has two display interfaces. Make the used one a parameter
in struct display_info_t instead of using unconditionally DI0.
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Add GPIO support to Freescale VF610
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
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Add writebcb command which creates a NAND Boot Configuration Block
(BCB) at the beginning of the active flash device. The BCB stores
the information for the SoC internal boot ROM where the application
with a valid IVT header can be found on the NAND device. The first
two argument of the command need an offset of the NAND device where
the primary and secondary application can be found.
Typically, U-Boot is the application which gets loaded by the boot
ROM. Hence, the offset address need to be the address where U-Boot
(u-boot.imx along with a 0x400 long prefix) is stored on the device.
At least one location is mandatory.
Currently only the FCB (Firmware Configuration Block) is written to
the device. The DBBT (Discovered Bad Block Table) is optional and
not created by writebcb currently.
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Add an additional target which prepends the u-boot.imx image with
0x400 padding bytes. On Vybrid, this is required for NAND boot
devices. The configuration CONFIG_IMX_NAND enables this image
for a board.
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In order to avoid code duplication, move the DDR3 initialization to the
common place under imx-common. Currently ROW_DIFF and COL_DIFF can be
chosen from the board file. The JEDEC timings are specified using a
common ddr3_jedec_timings structure.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
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IMX_CONFIG is currently passed via the SYS_EXTRA_OPTIONS which is marked
as deprecated.
Add a new Kconfig file under arch/arm/imx-common and define the
IMX_CONFIG Kconfig in there.
Each board is supposed to provide a default value pointing to the
appropriate imximage.cfg file.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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Freescale's SEC block has built-in Data Encryption
Key(DEK) Blob Protocol which provides a method for
protecting a DEK for non-secure memory storage.
SEC block protects data in a data structure called
a Secret Key Blob, which provides both confidentiality
and integrity protection.
Every time the blob encapsulation is executed,
a AES-256 key is randomly generated to encrypt the DEK.
This key is encrypted with the OTP Secret key
from SoC. The resulting blob consists of the encrypted
AES-256 key, the encrypted DEK, and a 16-bit MAC.
During decapsulation, the reverse process is performed
to get back the original DEK. A caveat to the blob
decapsulation process, is that the DEK is decrypted
in secure-memory and can only be read by FSL SEC HW.
The DEK is used to decrypt data during encrypted boot.
Commands added
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dek_blob - encapsulating DEK as a cryptgraphic blob
Commands Syntax
---------------
dek_blob src dst len
Encapsulate and create blob of a len-bits DEK at
address src and store the result at address dst.
Signed-off-by: Raul Cardenas <Ulises.Cardenas@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Ulises Cardenas <ulises.cardenas@freescale.com>
Signed-off-by: Ulises Cardenas-B45798 <Ulises.Cardenas@freescale.com>
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Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
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The malloc() calls are unnecessary, just allocate the stuff on stack.
While at it, reorder the code a little, so that only one variable is
used for the text, use snprintf() instead of sprintf() and use %01d
as a formatting string to avoid any possible overflows.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
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Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
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- fix crash when sata device is not initialized
- remove disable_sata_clock() since it is not clear which clock for which
device should be disabled here
- call disable_sata_clock() for mx6 in preboot_os instead
Signed-off-by: Soeren Moch <smoch@web.de>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
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Ideally, the Linux kernel should get the hardware in its most
untouched state. For the most part, U-Boot does not reset the various
subsystems it touches before boot, and usually Linux deals with it, but
on some boards (cm_fx6) the Linux kernel fails to detect the ssd
correctly if sata is used by U-Boot.
Power off sata on OS boot so that Linux will have a clean state to work
with.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
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Add imx6 thermal device to mx6 soc file. Read the cpu temperature
using this device to access onchip thermal sensor.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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Move MX5 specific set_chipselect_size function into generic i.MX part,
such that MX6 based boards are able to use this function as well.
While doing this the iomuxc gpr member needed to be consolidated between
MX5 and MX6.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Many boards use a minimal .cfg file in the SPL case.
Introduce spl_sd.cfg so that we can reuse it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
Cc: Stefano Babic <sbabic@denx.de>
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The bmode command forces the SoC to use a specific boot device
by writing its boot mode into SRC_GPR9, and notifying the SoC of
the change using SRC_GPR10[28] bit: if the bit is on, bootROM
uses the value in SRC_GPR9 instead of SRC_SMBR1 to determine
the boot device.
SPL on the other hand is oblivious to this distinction, so once
the bootROM loads SPL from the device configured in SRC_GPR10,
SPL will attempt to load U-Boot from the device configured in
SRC_SMBR1, which is not updated by the bootROM to the value in
SRC_GPR9.
The result is that the selected boot device is not used across all
the boot stages.
Update spl_boot_device() to look at gpr9 when necessary.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
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On mx6 sabreauto board, there are two USB ports:
0: OTG
1: HOST
The EHCI driver is enabled for this board, but the IOMUX and VBUS power
control is not implemented, which cause both USB port failed to work.
This patch fix the problem by adding the board support codes.
Since the power control uses the GPIO pin from port expander MAX7310,
the PCA953X driver is enabled for accessing the MAX7310.
The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting
its daisy chain. Add a new function "imx_iomux_set_gpr_register" to
handle GPR register setting.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Introduce a new configuration "CONFIG_MXC_GPT_HCLK". When it is set,
the GPT will select a high frequency clock as clock source.
Otherwise, the GPT will stay to use 32Khz OSC as clock source.
In the implementation, since only the GPT on i.MX6 series provide the
clock source option for 24Mhz OSC. For others (only i.MX5 and i.MX6
compile the driver), if the configuration is set, the perclk will be
selected as clock source.
MX6Q/D Rev 1.0 and MX6SL are special in the implementation, because they
don't have the 24Mhz OSC clock source option, so also select the perclk
for them. For MX6SL, we will set the OSC 24Mhz to perclk in CCM, so
eventually the clock comes from OSC 24Mhz.
Signed-off-by: Ye.Li <B37916@freescale.com>
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