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Enable microtips mf101hie OLDI panel and link it with DSS ports to
enable splash screen on AM62x LP SK.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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The default DM firmware path is non-optional as of now. Make it
optional so that users that choose to provide DM via TI_DM argument
instead of BINMAN_INDIRS can do so without build errors.
Cc: Chirag Shilwant <c-shilwant@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Tested-by: Chirag Shilwant <c-shilwant@ti.com>
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Move bus-width property to *main.dtsi, above the OTAP/ITAP
delay values. While there is no error with where it is
currently at, it is easier to read the MMC node if the
bus-width property is located above the OTAP/ITAP delay
values consistently across MMC nodes.
Add missing bus-width DTS property for sdchi2 in k3-am62-main.
Signed-off-by: Judith Mendez <jm@ti.com>
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Move ti,clkbuf-sel property above the OTAP/ITAP delay values.
While there is no error with where it is currently at, it is
easier to read the MMC node if ti,clkbuf-sel is located above
the OTAP/ITAP delay values consistently across MMC nodes.
Add missing ti,clkbuf-sel DTS property for sdhci0 in k3-am64-main.
Signed-off-by: Judith Mendez <jm@ti.com>
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Remove DLL properties which are not applicable for soft PHYs
since these PHYs do not have a DLL to enable.
Signed-off-by: Judith Mendez <jm@ti.com>
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Update MMC OTAP/ITAP values according to the datasheet
[0], refer to Table 7-79 for MMC0 and Table 7-97 for MMC1/MMC2.
[0] https://www.ti.com/lit/ds/symlink/am62p.pdf
Signed-off-by: Judith Mendez <jm@ti.com>
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Update MMC0/MMC1 OTAP/ITAP delay values according to the
datasheet [0], refer to Table 7-79 for MMC0 and Table 7-97
for MMC1.
[0] https://www.ti.com/lit/ds/symlink/am62a7.pdf
Signed-off-by: Judith Mendez <jm@ti.com>
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Update MMC0/MMC1 OTAP/ITAP values according to the datasheet
[0], refer to Table 7-68 for MMC0 and Table 7-77 for MMC1.
Move ITAPDLY values after OTAPDLY values to make MMC
nodes more uniform across devices.
[0] https://www.ti.com/lit/ds/symlink/am6442.pdf
Signed-off-by: Judith Mendez <jm@ti.com>
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Add sdhci2 DT node in k3-am62a-main for mmc2. Add otap/itap
values according to the datasheet[0], Refer to Table 7-97.
[0] https://www.ti.com/lit/ds/symlink/am62a3.pdf
Signed-off-by: Judith Mendez <jm@ti.com>
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Nothing much has changed between the versions of the emif output. Some
changes to the PHY_PAD_CAL_IO_CFG_0, PHY PAD RST DRIVE, and
PHY_CAL_CLK_SELECT_0 should add some minor stability improvements.
Nonetheless, update to the latest characterization developments.
Signed-off-by: Bryan Brattlof <bb@ti.com>
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On AM69 board, build image was going beyond wrt defined
offsets.
So increasing offset for eMMC and OSPI boot. Along with
update in corresponding device tree.
Cc: Neha Francis <n-francis@ti.com>
Cc: Vaishnav Achath <vaishnav.a@ti.com>
Cc: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Tested-by: Beleswar Padhi <b-padhi@ti.com>
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The output from the emif tool hasn't changed for a while now, however
there is still a difference from what we use.
Signed-off-by: Bryan Brattlof <bb@ti.com>
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The output from the emif tool hasn't changes in a long while however
there are some differences. Update to these latest settings.
Signed-off-by: Bryan Brattlof <bb@ti.com>
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After a little debugging on the am62px some of these values will need to
be changed. Update to these new values to improve stability at higher IO
voltages.
Signed-off-by: Bryan Brattlof <bb@ti.com>
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After a little bit of debugging and characterization at different IO
voltages, some of these values will need to change. Update to these
latest settings to improve stability at higher IO voltages.
Signed-off-by: Bryan Brattlof <bb@ti.com>
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ICSSG1 provides dual Gigabit Ethernet support.
Add ICSSG1 ethernet node to am64x device tree.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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The ICSSG IP on AM64x SoCs have two Industrial Ethernet Peripherals (IEPs)
to manage/generate Industrial Ethernet functions such as time stamping.
Each IEP sub-module is sourced from an internal clock mux that can be
derived from either of the IP instance's ICSSG_IEP_GCLK or from another
internal ICSSG CORE_CLK mux. Add both the IEP nodes for both the ICSSG
instances. The IEP clock is currently configured to be derived
indirectly from the ICSSG_ICLK running at 250 MHz.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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Add ICSSG2 overlay and configuration to tispl and u-boot images.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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ICSSG2 provides dual Gigabit Ethernet support.
Add ICSSG2 ethernet node to an overlay k3-am654-icssg2.dts
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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The ICSSG IP on AM65x SoCs have two Industrial Ethernet Peripherals (IEPs)
to manage/generate Industrial Ethernet functions such as time stamping.
Each IEP sub-module is sourced from an internal clock mux that can be
sourced from either of the IP instance's ICSSG_IEP_GCLK or ICSSG_ICLK.
Add the IEP nodes for all the ICSSG instances.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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There are a few missing registers ranges in the udmap nodes
need to properly setup DMA for the am65x.
A fix has been added to the Linux kernel [0] to add these ranges and
merged. To keep DMA operational until the next DT sync from Linux, these
ranges were added to the *-u-boot.dtsi in the upstream u-boot [1].
Porting these DMA changes to ti-u-boot as these are needed for ICSSG
Ethernet driver to work.
And additional config register was added to the ringacc node in upstream
u-boot as part of DT sync from linux 6.7-rc1 [2]. Porting those changes
as well to ti-u-boot as those are also needed for ICSSG Ethernet driver to
work.
[0] https://lore.kernel.org/r/20231213135138.929517-2-vigneshr@ti.com
[1] https://source.denx.de/u-boot/u-boot/-/commit/5e00547e583f6d4349f3908d3491bf6ce0a8818c
[2] https://source.denx.de/u-boot/u-boot/-/commit/4dbdc84754ea2ad392ef7328da6d429cd8fd3c0a
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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Update the USB0, USB1 nodes and enable them.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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USB1 controller on J722S and AM62P are from different vendors.
Redefine the USB1 node description for J722S by deleting the
node inherited from AM62P dtsi.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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Add SERDES0 and its wrapper description to support USB3
and SGMII interfaces.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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Add AVS and Tulip TPS62873 regulator node.
Signed-off-by: Keerthy <j-keerthy@ti.com>
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Remove 'reserved' status for MCU ESM node in AM62P device tree
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
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Add Main ESM and MCU ESM nodes to the AM62A device tree.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
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Add ss_cfg memory region which maps the DDRSS configuration region
for the memory controller node.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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Add the bootph-pre-ram property to the memory node so that it can be
accessed by FDT functions at R5 stage.
The fdt_setup_mem*() functions require the memory node to be able to
initialize and set the size of the DRAM banks. For this purpose, make
sure all memory nodes are present and standardized, and add them if not.
Also make sure they have bootph-pre-ram property so that it can be
accessible at R5 SPL stage.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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Update the delay values for various speed modes supported, based on
the revised august 2021 J721E Datasheet [1].
[1] https://www.ti.com/lit/ds/symlink/tda4vm.pdf,
(SPRSP36J - FEBRUARY 2019 - REVISED AUGUST 2021)
- Table 7-77. MMC0 DLL Delay Mapping for All Timing Modes and
- Table 7-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
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For R5 SPL, we include the NAND support in the board DTS file
(k3-am642-r5-evm.dts) as there is no way to use overlay in
BootROM at the moment.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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- Enable splash screen for AM62P using DSS0 instance and microtips
mf101hie OLDI panel.
- As DSS0 instance has same register space , video ports and video
planes as AM62x use the same compatible as AM62x.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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Enable eMMC support by adding sdhci0 node.
Add cma node and led node as well.
Also add missing bootph-all flag for main_i2c0 node.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Add DMSC child node sysreset-controller for uboot reset.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
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Add Main-R5F and C7x nodes to the SOC file and keep them disabled.
Rename the firmwares for MCU and WKUP R5F cores.
Enable IPC support for main, mcu and wakeup R5F and C7x cores
with memory craveouts and mailboxes.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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K3 R5 remoteproc driver requires reserved memory carveouts and mailbox
configuration to instantiate the cores successfully. Since this is a
board level resource dependency, keep the R5 subsystem disabled at SoC
level and enable them at EVM where the dependencies are met.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Replace all the fsstub occurences with tifsstub to avoid new
terminology and resulting confusion.
Suggested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
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Firewalling IP has 3 permissions slots for slave and DRU firewalls. Each
permission slot can be populated with different accesses to different
privIDs.
Configuring a background firewall with an allow all permission
(0xc3ffff) in just one slot doesn't work as intendted as the other
permission slots which are essentially 0x0000 act as a block all
transaction for privID 0.
Explicitly fill all the permission registers of background firewall
regions to allow all transactions to go through including privID 0.
Foreground firewalls are intendted to block privID 0 as well so they are
not touched.
[ AM68-SK CSI Test ]
Tested-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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DDR50 speed mode is enabled for MMCSD in J784s4 but its Itap Delay
Value is not present in the device tree. Thus, add Itap Delay Value
for MMCSD Ultra High Speed DDR which is DDR50 speed mode for J784s4 SoC
according to datasheet for J784s4 [1].
[1] Refer to : section 6.10.5.17.2 MMC1/2 - SD/SDIO Interface, in
J784s4 datasheet
- https://www.ti.com/lit/ds/symlink/tda4vh-q1.pdf
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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DDR50 speed mode is enabled for MMCSD in J721s2 but its Itap Delay
Value is not present in the device tree. Thus, add Itap Delay Value
for MMCSD Ultra High Speed DDR which is DDR50 speed mode for J721s2 SoC
according to datasheet for J721s2 [1].
[1] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in
J721s2 datasheet
- https://www.ti.com/lit/ds/symlink/tda4vl-q1.pdf
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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DDR52 speed mode is enabled for eMMC in J7200 but its Itap Delay Value
is not present in the device tree. Thus, add Itap Delay Value for eMMC
High Speed DDR which is DDR52 speed mode for J7200 SoC according to
datasheet for J7200 [1].
[1] Refer to : section 7.9.5.16.1 MMCSD0 - eMMC Interface, in
J7200 datasheet
- https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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SK-AM64B boot is broken. The main_i2c0 node is
left disabled in r5-evm.dts preventing
proper board detection. Explicitly enable
the main_i2c0 node in r5-evm.dts.
Fixes boot and below error message:
"Reading on-board EEPROM at 0x51 failed -19"
Fixes: cc471479d3850: ("arm: dts: k3-am642: main_i2c0 cleanup")
Reported-by: Andreas Dannenberg <dannenberg@ti.com>
Suggested-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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Upstream u-boot changed to using the ti,j7200-vtm compatible with
the Linux 6.6 DT sync, so using the same here
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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The J7200 SoC supports MPU core voltage of 760mv
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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Define the MSMC clk in the a72 node
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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commit 3ef977e085767df31e42262f15837a66558052db upstream
Move the DM entry in tispl.bin FIT image from default fetching an
external blob entry to fetching using ti-dm entry type. This way, the
DM entry will be populated by the TI_DM pathname if provided. Else it
will resort to the ti-dm.bin file.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
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Sync with Linux device-tree w.r.t. CPSW3G.
With this, MAC Port 1 of the CPSW3G instance of CPSW Ethernet Switch
is functional in RGMII-RXID mode of operation.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Include the uboot device tree files needed to boot the board.
Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Pull in the device tree source files for TI's J722S SoCs needed to boot
the board from v6.6-rc5. These are an early release with only the
peripherals to boot the board via UART boot.
Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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The lowest speed grade of Toradex AM62 SoMs is K speed, resulting in a
max value of 800MHz for the CPU operating frequency. A solution with
runtime selection of the CPU frequency is already planned to avoid these
kinds of problems in the future.
Upstream-Status: Submitted [https://lore.kernel.org/u-boot/20240319140427.73721-1-jpaulo.silvagoncalves@gmail.com/T/#u]
Fixes: 8fb8a6d49977 ("arm: dts: k3-am625-verdin-r5:Change CPU
frequency to 1000MHz")
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
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