Age | Commit message (Collapse) | Author |
|
It was decided to get rid of the extra capacitor on the reset line
so this is no longer needed
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
|
|
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
|
|
This adds the possibility to add a delay after a reset in DT.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
|
|
Initial board support for Apalis iMX8QXP using a copy of Colibri iMX8QXP.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
|
|
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
Clean-up device tree syncing with Linux one as well.
Delete nodes not used by U-Boot.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
Change the top-level compatible to use common toradex,apalis-imx8 notation.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
Adjust copyright/licensing headers e.g. universally using SPDX license
identifier.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
Fix Ethernet functionality. The FEC clock on i.MX 8X really has an
additional by 2 divider plus our design requires the ENET0_RCLK50M_OUT
on the ENET0_RGMII_TXC pin to be turned on for the Micrel PHY.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
|
Fix USB device aka UMS as well as USB host functionality.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
|
Clean-up device tree syncing with Linux one as well.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
|
Fix top-level compatible to use common toradex,colibri-imx8qxp notation.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
|
Adjust copyright/licensing headers e.g. universally using SPDX license
identifier.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
|
This also enables pullups on the uart forceoff pins.
The UART transceivers on an Iris carrier board can be disabled by
controlling SODIMM pins 102 and/or 104. Make sure that the pins by
default have pullups to have the debug UART working.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit 969f430f983d602afd83b6dd75b299e51463eae9)
(cherry picked from commit 2963361493e0f3df76f3a25202a56a76e69fd63f)
|
|
Initial board support for Colibri iMX8QXP using a copy of Apalis iMX8.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit 62f0f03e1acb4bb6b0fcca8d4e9bd4d2df04ad33)
(cherry picked from commit be14c3ea1850e2614883c86b62fd1c3a1828eac2)
|
|
NXP LPUART1 is used as Apalis UART1, which is the main console
on our Linux BSP.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit 360629c1fd6187de19d0f50feb85c725995e49cc)
(cherry picked from commit 63030dac6afc51d17b04d23ce41af4788f03717e)
(cherry picked from commit 7bbe1708e0cebf3432c234ea74f8d6fb632a023b)
(cherry picked from commit d58fa8f3247edc18bdbf716fa9a45bcf5fce9cb8)
|
|
The Apalis iMX8 module does not have PCA9557 GPIO controllers
on the module.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit c80b3bfbe693d5a8851129f4878d0cd3a7325d13)
(cherry picked from commit 898ae105703cd0019a542bc0a17649339c934fa6)
(cherry picked from commit 69d385444efa79d2909f772c4a4b404d1bd7274d)
(cherry picked from commit 0f5887d5b80f8535a7f422b73d7a0bf4a4e445af)
|
|
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit 6c6ac6c8a0107947a9c0952eee65a015c66043a0)
(cherry picked from commit 41602d51fd56396a2647734c530a389d099ee47b)
(cherry picked from commit 73fe13597170f39d943d5dbc67c2416506cf7997)
(cherry picked from commit b8fbd7377cc6e38a90793b01c2a085f85d54a6fa)
|
|
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit fa3d4f980a515b135778a74ce1b7476f61ef20d0)
(cherry picked from commit 2ee92bc1dd56b44343079a5474d0fc4e79f28f4a)
(cherry picked from commit 649afbe0aec4089112772a49a7e6f7d34c3741a7)
(cherry picked from commit 81591346d11ffdf9a2442ad976390ffe0e61abda)
|
|
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit aa830cb6a7c953ce85232b2ae951543ab1060948)
(cherry picked from commit f6c37cdf31633a541078d0813ab4f59f6b80babb)
(cherry picked from commit ae70d02213beabcd60853f655e2ff9849375c45c)
(cherry picked from commit ba629689c627a571d5902a1c50fe9927424b45c6)
|
|
iMX8DX MEK board has similar design with 8QXP MEK. The major changes are
1. DDR changed to 16bits 1GB DDR part
2. USB3.0 is removed and only support OTG on typec port. (No SW change needed)
This patch adds new defconfigs and DTS file for this new board.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 5efb4275f6cfefb5dd342f2e498834b40b989883)
|
|
When trying to remove "CONFIG_USB_TCPC=y" to avoid ramdom issue of
synchronous abort when enter fastboot, evk_8mm and evk_8mn can't
enter fastboot mode, it's because init_type of the usb udevice private
data is host if tcpc configuration is removed, if this init_type is
host/peripheral, then the usb is forced to be this mode, can not be
initialized as another.
init_type of the usb udevice private data is firstly set based on the
"dr_mode" in dtb, if "dr_mode" is not set, it will be set by other ways.
here set the "dr_mode" property for the usb device to be "otg", then the
device can be configured as either host or peripheral.
Change-Id: Idadab7bb07e74bfc1f8768490c07127a35a02572
Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
|
|
Both imx8mn/imx8mm EVK boards have eMMC 5.1 chip and support SD3.0
So we enable the HS400ES and UHS configs to enhance eMMC/SD access.
The change also needs to set usdhc clock to 400Mhz and update compatible
string to fsl,imx8mm-usdhc
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
|
|
iMX8MQ EVK board has a eMMC5.0 chip and supports SD3.0, so enable the UHS
and HS400 configs to enhance the eMMC/SD access.
The change also needs to set usdhc clock to 400Mhz, and add the off-on-delay-us
to SD reset pin, otherwise some SD cards will fail to select UHS mode in
re-initialization.
Signed-off-by: Ye Li <ye.li@nxp.com>
|
|
Add the "DDR4" to board name to distinguish with LPDDR4 board.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
|
|
Add support for iMX8MN LPDDR4 EVK board which uses 2GB LPDDR4 and
PCA9450B PMIC.
Signed-off-by: Ye Li <ye.li@nxp.com>
|
|
There is an divider on imx8mn will always divide 2 to flexspi root clock.
So actual SCLK output to device is 50Mhz on imx8mn not 100Mhz.
After changing the root clock setting to configure SCLK to 100Mhz, found
the read data is not correct. Must enable the internal DQS pad loopback
to fix the problem.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
|
|
Add the board DTS file for iMX8MN EVK. The base board re-use base board
of iMX8MM EVK. The CPU board has most of same design with iMX8MM CPU
board, except DDR4 and some PMIC power rails.
Signed-off-by: Ye Li <ye.li@nxp.com>
|
|
Add soc DTSi and clock/pinctrl binding files. The pinctrl binding
file is v0.03 generated by tool
Signed-off-by: Ye Li <ye.li@nxp.com>
|
|
Enable i2c2 and i2c3 for AIY.
Change-Id: I984e2e76e7c8929cc62088b6838c81f5dc838568
|
|
We are currently using SC_R_LAST as a marker for imx8 power domain tree
nodes without a resource attached. This value is compiled into dtb as
part of the linux build and used by uboot.
The SC_R_LAST constant changes frequently as SCFW resources are added
(by design) and every time we need to update linux and uboot headers
together or boot can fail.
Fix this by replacing SC_R_LAST usage with a new constant SC_R_NONE
defined to be 0xFFF0.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
|
|
To U-Boot on DomU, the lpuart0 is replaced with a xen paravirtual
consol driver, but reused the previous lpuart node. However
there is an power-domains entry in lpuart0 which will call
power_domain_on and failed to probe xen paravirtual driver,
because of recent change:
commit 8524ca764d8f("MLK-20945-2 dm: device: Check the power up result in probe ")
So remove the power-domains entry in lpuart0 to let DomU U-Boot could
output again.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
|
|
Add compatible strings and properties to i2c1 node for using virtual
i2c and i2c mux drivers
Signed-off-by: Ye Li <ye.li@nxp.com>
|
|
We use MU8 and MU9 to communicate with M4_0 and M4_1 in u-boot. Add
relevant nodes for the MU driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
|
|
There are two new validation boards: LPDDR4 board (30123) and DDR3L board (30010)
for imx8x family 17x17 chips. These two boards have same design except the DDR.
Since SCFW is resposible for DDR initialization, U-boot could use one build to
cover two boards.
The 8DX 17x17 DDR3L ARM2 has been added into u-boot before, so we rename the config
CONFIG_TARGET_IMX8DX_DDR3_ARM2 to CONFIG_TARGET_IMX8X_17X17_VAL to cover DDR3L and
LPDDR4.
Considering 8DX and 8QXP 17x17 may solder to the boards, we create two defconfig:
one for DX and another for 8qxp to share with the CONFIG_TARGET_IMX8X_17X17_VAL
but with different FDTs.
Signed-off-by: Ye Li <ye.li@nxp.com>
|
|
Add i2c gpio pinctrl settings and properties to enable i2c force idle.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
|
|
Add i2c gpio pinctrl settings and properties to enable i2c force idle.
Avoid any i2c bus not released by device during reboot.
Signed-off-by: Ye Li <ye.li@nxp.com>
|
|
Add support for new target imx8mq_aiy.
Test: build and boot ok on imx8mq_aiy.
Change-Id: I7bb8b66e5235a7122073dcfb4cdc7f165036b9a6
Signed-off-by: Ji Luo <ji.luo@nxp.com>
|
|
Some platforms don't have alias for usb1 device, so when initialize the
second controller, its seq is allocated by u-boot automatically.
This introduces a problem if the initialization of first controller is failed,
for example nothing connect to first controller, then the seq allocated
for second controller is 0 not 1. EHCI driver uses the seq as index for
USB controller and phy, so it will cause initialization problem for second
controller.
Fix the issue by adding the usb1 alias for second USB controller.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
|
|
Enable dm usb using the base board otg usb port for fastboot usage
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
|
|
Enable dm serial for xen uboot.
Log as below:
#xl console 1
MMC: FSL_SDHC: 0
Loading Environment from <NULL>... *** Warning - bad CRC, using default environment
Failed (-5)
In: serial@5a060000
Out: serial@5a060000
Err: serial@5a060000
flash target is MMC:0
Fastboot: Normal
Normal Boot
=>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
|
|
Align the new pinfunc names with header file for all iMX7ULP EVK and ARM2
DTS files.
Also update the EVK DTS files to align with kernel for Rev A3
board. Removed the extcon node for USB ID, since A3 board uses USB ID pin
not GPIO.
Signed-off-by: Ye Li <ye.li@nxp.com>
|
|
i.MX7ULP B0 silicon has below updates in iomux
- GPIO function input buffer enable (IBE)/output buffer enable (OBE) is
now controlled by RGPIO module. IOMUXC IBE/OBE is used as an override.
- LPUART2_TX (I/O) to PTB12 (ALT4)
- LPUART2_RX (I) to PTB13 (ALT4)
- USB0_ID (I) to PTC13 (ALT11), PTC18 (ALT11) and PTC19 (ALT10)
- VIU_DE (I) to PTC18 (ALT12), PTC19 (ALT12) and PTE5 (ALT12)
- RTC_CLKOUT (O) to PTB5 (ALT11) and PTB14 (ALT11)
- SEC_VIO_B (I) to PTB4 (ALT11)
- Added new Input Selection Registers
PSMI1_USB0_ID Address: 0x40ac_0338 To select USB_ID input pad/source
PSMI1_VIU_DE Address: 0x40ac_033c To select VIU_DE input pad/source
Copy the imx7ulp-pinfunc.h from latest kernel dts
(commit 18cdeadfe1967ea33d3bdfc7ccead6d6d06a98a6), and update
the mx7ulp-pins.h accordingly.
Signed-off-by: Ye Li <ye.li@nxp.com>
|
|
Add DDR3 init codes, board codes, defconfig and DTS into u-boot.
Basic modules are ready: SD, UART, I2C, USB host and NAND.
There is a FPGA on this board. It controls WDOG_B, and ENET PHY RESET.
So reset and ethernet won't work at default.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
|
|
add config for emmc, nand and qspi boot
Signed-off-by: Robby Cai <robby.cai@nxp.com>
|
|
Add i.MX6ULZ support. the i.MX6ULZ is SW compatible
with i.MX6ULL. so most code of i.MX6ULL can be reused
by i.MX6ULZ.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
|
|
Default address of earlycon parameter is not correct,
use correct value for imx7ulp_evk.
Test: imx7ulp_evk boots ok.
Change-Id: I2cecb6bfacca573013313ba4ae3783784ccfd506
Signed-off-by: Luo Ji <ji.luo@nxp.com>
|
|
Android Auto need different bootargs for imx8q, override default
dts node "/chosen/bootargs" to change the bootargs.
Change-Id: I32f741624b7d3ed7e91f36a466ae641fe11dfe8e
Signed-off-by: Luo Ji <ji.luo@nxp.com>
|