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path: root/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
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2021-11-30stm32mp1: ram: remove the support of calibration resultPatrick Delaunay
The support of a predefined DDR PHY tuning result is removed for STM32MP1 driver because it is not needed at the supported frequency when built-in calibration is executed. The calibration parameters were provided in the device tree by the optional node "st,phy-cal", activated in ddr helper file by the compilation flag DDR_PHY_CAL_SKIP and filled with values generated by the CubeMX DDR utilities. This patch - updates the binding file to remove "st,phy-cal" support - updates the device trees and remove the associated defines - simplifies the STM32MP1 DDR driver and remove the support of the optional parameter "st,phy-cal" After this patch, the built-in calibration is always executed and the calibration registers are moved in the phy dynamic part; that allows manual tests. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-02-09ARM: dts: stm32: Fix cosmetic typo: use 'kHz' as kilohertz abbreviationFabrice GIRARDOT
The kilohertz unit abbreviation should read 'kHz'. Note to STM32 team: modified files were generated, it may be worth to fix STM32CubeMX tool. Signed-off-by: Fabrice GIRARDOT <fabrice.girardot@flowbird.group> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2020-05-14ARM: dts: stm32mp15: use DDR3 files generated by STM32CubeMXPatrick Delaunay
Use the DDR3 dtsi files generated by STM32CubeMX 5.6.0 Speed Bin Grade = using DDR3-1066G / 8-8-8 and all others parameters at default value. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14ARM: dts: stm32: Rework DDR DT inclusionMarek Vasut
Adjust the DDR configuration dtsi such that they only generate the DRAM configuration node, the DDR controller node is moved into the stm32mp157-u-boot.dtsi itself. This permits including multiple DDR configuration dtsi files in board DT. Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2019-08-27ARM: dts: stm32mp1: DDR config v1.45Patrick Delaunay
Update DDR configuration with the latest update: - Change DQSGE to 1 for DDR3, to cure missing DQS preamble. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23ARM: dts: stm32mp1: DDR config v1.44Patrick Delaunay
Update DDR configuration with the latest update: - PUBL_regs: DXnGCR[0]= according to ddr_width to disable Byte lane 2/3 in 16bit - fix LPDDR2/3 timing_calc to step RL/WL in relaxed timings mode - remove LPDDR3 RL3 (optional) support vs MR0[7] because MR0[7] can't be read instead always apply worse RL/WL for LPDDR3 when freq < 166MHz) - change MR3 to 48ohm drive for LPDDR2/3 - change default ZPROG[7:4] = 0x1 for LPDDR2/3 , '0' is not allowed even when ODT not used - use DQSTRN for LPDDR2/3 (it was not set in PIR) - LPDDR3: set dqsge/dwsgx gate extension to 2,2 like LPDDR2 -DDRCTRL.dfitmg0: + for LPDDR3 tphy_wrlat = WL (as LPDDR2) + improvement for relaxed mode vs RL/Wl at corner case. For example @533MHz RL/WL (relaxed) = 9/5 for LPDDR2/3 and correction to MR2 accordingly - DDR_PCFGQOS1_1: port1 timeout relaxed from 0x00 to 0x40, for LTDC. - DDR_PCFGWQOS0_0: change vpr level from 11 to 12 in order to include the CPU on the variable priority queue. - DDR_SCHED: fix to consider 13 levels (13 levels - 1 = 0xC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: ram: change ddr speed to kHzPatrick Delaunay
Allow fractional support in DDR tools. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-05-07SPDX: Convert all of our multiple license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have multiple licenses (in these cases, dual license) declared in the SPDX-License-Identifier tag. In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B" as per the Linux Kernel style document. Note that parenthesis are allowed so when they were used before we continue to use them. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2018-03-19dts: add device tree for STM32MP157C-ED1 boardPatrick Delaunay
Add minimal devicetree for STM32MP157C-ED1 board, with only the devices to allow boot from SDCARD: - RCC for clock and reset - UART4 for console - I2C and PMIC - DDR - SDMMC0 for SDCard Waiting Kernel upstream for alignment. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>