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Add the bootph-pre-ram property to the memory node so that it can be
accessed by FDT functions at R5 stage.
The fdt_setup_mem*() functions require the memory node to be able to
initialize and set the size of the DRAM banks. For this purpose, make
sure all memory nodes are present and standardized, and add them if not.
Also make sure they have bootph-pre-ram property so that it can be
accessible at R5 SPL stage.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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Enable Octal DTR mode for SPI NAND under OSPI0 after the cadence qspi
driver is modified to accommodate multiple flashes under a single OSPI
instance.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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For achieving higher clocks speeds (greater than 25 MHz DDR) with OSPI,
OSPI PHY needs to be enabled and calibrate, add the necessary property
to enable PHY.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
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J721S2 has an OSPI NAND flash on its SOM connected the OSPI0 instance,
add dts node for the flash. This NAND flash is muxed with OSPI NOR flash
through a physical switch (SW3.1). SW3.1 when set as 1 connects the NAND
flash to the SoC.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a
QSPI NOR flash on the common processor board connected to the OSPI1
instance. Add support for the same and enabled them in SPL and U-Boot.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
[Add partitions information and rebase]
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
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Two carveout reserved memory nodes each have been added for each of the
R5F and C71x remote processor devices/DSP/DSPs within both the MCU and
MAIN domains for the TI J721S2 EVM boards. These nodes are assigned to
the respective rproc device nodes as well. The first region will be used
as the DMA pool for the rproc device, and the second region will furnish
the static carveout regions for the firmware memory.
The current carveout addresses and sizes are defined statically for each
device. The R5F processors do not have an MMU, and as such require the
exact memory used by the firmwares to be set-aside. The firmware images
do not require any RSC_CARVEOUT entries in their resource tables either
to allocate the memory for firmware memory segments.
The C71x DSP processor does support a MMU called CMMU, but is not
currently supported and as such requires the exact memory used by the
firmware to be set-aside.
Note that the R5F1 carveouts are needed only if the R5F cluster is running
in Split (non-LockStep) mode. The reserved memory nodes can be disabled
later on if there is no use-case defined to use the corresponding
remote processor.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
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A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed
components necessary for functionality. Therefore, add support for the
components present on the SoM.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
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