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path: root/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
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2023-10-18arm: dts: k3-j721e-r5-common-proc-board: Fix OSPI spi-tx-bus-widthApurva Nandan
spi-tx-bus-width is set as 8 in SoM dtsi, but set to 1 in R5 common proc board dts, which seems wrong. SPI NOR requires a 8D reset before probe starts using 0x66+0x99 op, but that will fail if the flash tx width is set as 1. Set spi-tx-bus-width to 8 in R5 common proc board dtsi also. Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>
2023-09-29arm: dts: k3-j721e-r5*: Add registers for vtm ipUdit Kumar
Add missing register support for VTM IP, which are needed for thermal shutdown programming. Signed-off-by: Udit Kumar <u-kumar1@ti.com> Signed-off-by: Neha Francis <n-francis@ti.com>
2023-07-06arm64: dts: k3-j721e-*: Enable OSPI PHY modeVaishnav Achath
For achieving higher clocks speeds (greater than 25 MHz DDR) with OSPI, OSPI PHY needs to be enabled and calibrate, add the necessary property to enable it and also while at it remove the deprecated legacy partition description support for OSPI. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
2023-06-07arm: dts: k3-j721e-r5-common-proc-board: Set parent clock for clock ID 342Apurva Nandan
This virtual clock mux configuration enables the use of dynamic frequency scaling on A72 clock ID 202 by setting up the required register. Signed-off-by: Apurva Nandan <a-nandan@ti.com>
2023-06-01arm64: dts: k3-j721e-*: Add flash partition informationVaishnav Achath
Describe flash partition information in device tree for J721E EVM and SK, this helps to remove the legacy mtdparts configuration and also helps to keep Kernel and U-boot DT in sync. Also enable OSPI PHY calibration pattern partition during SPL stage. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
2023-05-25j721e: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.imgNeha Malcom Francis
By providing entries in the binman node of the device tree, binman will be able to find and package board config artifacts generated by TIBoardConfig with sysfw.bin and generate the final image sysfw.itb. It will also pick out the R5 SPL and sign it with the help of TI signing entry and generate the final tiboot3.bin. Entries for A72 build have been added to k3-j721e-binman.dtsi to generate tispl.bin and u-boot.img. Support has been added for both HS-SE(SR 1.1), HS-FS(SR 2.0) and GP images In HS-SE, the encrypted system firmware binary must be signed along with the signed certificate binary. tiboot3.bin and sysfw-j721e_sr1_1-hs.itb: For HS-SE devices tiboot3.bin_fs and sysfw-j721e_sr2-hs-fs.itb: For HS-FS devices tiboot3.bin_unsigned and sysfw-j721e-gp-evm.itb: For GP devices <filename>.bin/img: For HS devices <filename>.bin_unsigned/img_unsigned: For GP devices Intention of patch is to move signing and packaging to binman, thus making makefile target only if binman is not enabled. It is to be noted that the bootflow followed by J721E requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs sysfw.itb: * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OPTEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-25arm: dts: k3-j721e: Refine MAIN domain ESM supportNeha Malcom Francis
MAIN domain ESM support was already added for J721E to configure main domain watchdog interrupts to generate ESM pin events. Move the main_esm node to be in sync with kernel dts. Also add register mapping for ESM in J721E. Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-05-09arm: dts: k3-j721e-r5: add a72 cluster power domain nodeManorit Chawdhry
[ upstream commit bdbd6688534cd998edc7dc057b67a70c5a5eeccb ] adds a72 cluster to control from the rproc driver Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-12dm: dts: Convert driver model tags to use new schemaSimon Glass
Now that Linux has accepted these tags, move the device tree files in U-Boot over to use them. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-06-10arm: dts: k3-j721e-r5-common-proc-board: Add HyperFlash nodeVaishnav Achath
J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node for the same. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
2022-02-21arm: dts: k3-j721e-r5-common-proc-board: tps659413: Correct the min/max ↵Keerthy
voltages of VDD_CPU Correct the min/max voltages of VDD_CPU. As per data sheet the VDD_CPU minimum voltage is .6V & maximum voltage is .9V. Correct the same. While at it fix the comment to reflect VDD_CPU instead of VDD_MPU. Data Sheet Link: https://www.ti.com/lit/gpn/dra829v Signed-off-by: Keerthy <j-keerthy@ti.com>
2022-02-16arm: dts: k3-j721e-r5-common-proc-board: Do not use power-domains for I2CSinthu Raja
Board ID I2C EEPROM will be probed before SYSFW is available. So drop the power-domains property for wakup_i2c0 on which board ID EEPROM is connected. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-08arm: dts: k3-j721e: Add support for multilink PCIe + QSGMIIAswath Govindraju
Add support for QSGMII multilink configuration. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0Aswath Govindraju
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the function device_probe, the corresponding clocks are probed before calling the device's probe. The PLL_CMNLC mux clock can only be created after the device's probe. Therefore, move assigned-clocks and assigned-clock-parents to the link nodes in U-Boot device tree file. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-09-10arm: dts: k3-j721e-r5-*.dts: Fix clock-names property in the usb0 instanceAswath Govindraju
In the cdns3 usb driver, the clock name looked for is ref. Therefore, fix the clock-names property in usb0 instance for proper initialization of cdns3 usb gadget driver. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-07-27arm: dts: k3-j721e-r5: Remove MAIN R5FSS0 cluster from SPLSuman Anna
The MAIN R5FSS0 cluster and corresponding nodes are no longer required to be enabled in R5 SPL after removing the support for booting any core from this cluster on R5 SPL. So, remove these from the relevant dts files. This is essentially a revert of the additions done in commit 2984b82b3b76 ("arm: dts: k3-j721e-r5: Enable r5fss0 cluster in SPL"). Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210726211311.5977-5-s-anna@ti.com
2021-06-11ARM: dts: j72xx-r5-common-proc-board: Add DM firmware nodeVignesh Raghavendra
Add DM firmware node which will provide DM services during R5 SPL stage. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210607141753.28796-5-vigneshr@ti.com
2021-02-04arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-BootLokesh Vutla
Sync all J721e related v5.11-rc6 Linux kernel dts into U-Boot. HBMC nodes are not yet added in Linux kernel yet but were added in U-Boot. In order to avoid any regressions, hbmc nodes are kept intact. These will be added in kernel in future. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-01-12arm: dts: k3-*-r5-*-board: Add GTC clockNishanth Menon
Add GTC Clock definition as index 0 clock so that we can use the clock node in the driver later on. Signed-off-by: Nishanth Menon <nm@ti.com>
2021-01-12arm: dts: k3-j721e: ddr: Update to 0.5.0 version of DDR config toolPraneeth Bajjuri
Update the ddr settings to use the DDR reg config tool rev 0.5.0. This enables 4266MTs DDR configuration. Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Kevin Scholz <k-scholz@ti.com>
2020-04-14arm: dts: k3-j721e: Increase OSPI default frequency to 50MHzVignesh Raghavendra
In 1 bit mode OSPI can work at upto 50MHz, this provides better write performance. Therefore increase frequency from 40MHz to 50MHz Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-03-17Merge tag 'ti-v2020.07-next' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next K3 J721E: * OSPI boot support * Support for loading remote cores in R5 SPL * PMIC ESM Support * Minor fixes for R5F and C7x remoteproc drivers K3 AM654: * Update AVS class 0 voltages. * Add I2C nodes DRA7xx/AM57xx: * Fixed Android boot on AM57xx AM33/AM43/Davinci: * switch to driver model for the net and mdio driver for baltos * Add DM/DTS support for omap video driver * Enable fastboot on am335x-evm
2020-03-09arm: dts: k3-j721e-r5-common-proc-board: Use unique names for dummy clocksFaiz Abbas
Update the dummy clock names to use unique identifiers. Otherwise the previous node just gets overwitten by the next one with the same name. This fixes eMMC boot not working on J721e-evm. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-03-06arm: dts: k3-j721e-r5-common-proc-board: Add ospi1 flash nodeKeerthy
Add ospi1 flash node required for QSPI boot. Signed-off-by: Keerthy <j-keerthy@ti.com>
2020-03-06arm: dts: k3-j721e: Enable ospi1/qspiKeerthy
Enable the ospi1/qspi for both r5 and a72 configurations. Signed-off-by: Keerthy <j-keerthy@ti.com>
2020-03-03arm: dts: k3-k721e: Add Main domain ESM supportTero Kristo
Main domain ESM support is needed to configure main domain watchdogs to generate ESM pin events by default. On J7 processor board these propagate to the PMIC to generate a reset when watchdog expires. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-03arm: dts: k3-j721e-r5: Enable r5fss0 cluster in SPLKeerthy
Enable MAIN domain r5fss0 cluster and its core0 in R5 spl. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-03-03ARM: dts: k3-j721e: Add OSPI DT nodesVignesh Raghavendra
Add OSPI DT nodes to enable OSPI at U-Boot prompt and also to support OSPI boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-02-13arm: dts: k3-j721e-r5-common-proc-board: Disable power-domains for mcu uartLokesh Vutla
mcu uart will be used during uart boot for loading sysfw.itb. Since sysfw is not yet available during uart load, power-domain cannot be enabled. We need to rely on ROM for doing that, so disable power-domains and clocks for mcu uart. Also fix the mcu uart frequency. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04arm: dts: k3-j721e-common-proc-board: Enable I2C expander for SPLVignesh Raghavendra
IO expanders are required to power cycle SD card. So enable the same Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04arm: dts: k3-j721e-common-proc-board: Enable USB0 in peripheral modeVignesh Raghavendra
Enable USB0 in peripheral mode so that it be used for DFU Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20arm: dts: k3-j721e-common-proc-board: Add pinmux for SD cardFaiz Abbas
Add pinmux for sdhci1 node connected to the SD card. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20arm: dts: k3-j721e: Add DT nodes for USBVignesh Raghavendra
J721e has two instances of Cadence USB3 controller. Add DT nodes for the same. USB0 is configured to device mode and USB1 is configured to host mode. For now only high speed mode is supported. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-11-07arm: dts: k3-j721e-r5-common-proc-board: Hook buck12_reg to vtm supplyKeerthy
Hook buck12_reg to vtm avs supply Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: dts: k3-j721e-r5-common: Add tps65941 node and dependent wkup_i2c0 nodeKeerthy
Add tps65941 node and dependent wkup_i2c0 node needed for AVS class 0 support Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: dts: k3-j721e-r5-common-proc-board: Add VTM nodeKeerthy
Add VTM node for voltage and thermal management. For u-boot, this is needed for supporting AVS class 0, as the efuse values for the OPPs are stored under the VTM. Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-10-25arm: dts: k3-j721e: Add ddr nodeLokesh Vutla
Use the 3733MTs DDR configuration that is auto generated from DDR_Regconfig tool. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Kevin Scholz <k-scholz@ti.com>
2019-07-26arm: dts: k3-j721e: Add r5 specific dt supportLokesh Vutla
Add initial support for dt that runs on r5. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
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