Age | Commit message (Collapse) | Author |
|
|
|
BUG=chromium-os:23496
TEST=build and boot on Waluigi, Cardhu by enabling
CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT.
odification of the work done by:
a. Jimmy Zhang <jimmzhang@nvidia.com>
b. Yen Lin <yelin@nvidia.com>
c. Wei Ni <wni@nvidia.com>
Change-Id: If2fa63ccd23341694955bca25fb5cfc4a8a805ad
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13800
|
|
warmboot_avp.h needs to be present in include/arch-tegra
in order to use it for Tegra3.
BUG=chromium-os:23496
TEST=build for Seaboard
Change-Id: I3f369194e4002e8257c9d2ff37253bc20733138d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/15394
|
|
BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi
Change-Id: Iacd6fdb178afbfdb978dbe53bbe2766916bf26f9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14685
|
|
split the LP0 code for tegra2 into common
LP0 code and chip specific warm boot code
BUG=chromium-os:23496
TEST=build for Seaboard
Change-Id: Ie04bf9ac17482a37afd0f4515dc3aafeb4f48ae7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/15883
|
|
This reverts commit 4c7502242627f64d91432cb4958be5f93f65fbff
Don't think this is the cause of http://code.google.com/p/chromium-os/issues/detail?id=26116, but it was in the same batch so I'm reverting in the process.
Change-Id: Icc013ced6c22e29d569ee4ca8ef73522154ec1a8
Reviewed-on: https://gerrit.chromium.org/gerrit/15561
Reviewed-by: Brian Harring <ferringb@chromium.org>
Tested-by: Brian Harring <ferringb@chromium.org>
|
|
This reverts commit 9a3fbb5f0b02382c7abe0cf40a4f08abbf269d05
Broke tegra2: http://code.google.com/p/chromium-os/issues/detail?id=26116
Change-Id: I7d35211c6ebce7a10750cb1033c6f8ba9a0f63bc
Reviewed-on: https://gerrit.chromium.org/gerrit/15560
Reviewed-by: Brian Harring <ferringb@chromium.org>
Tested-by: Brian Harring <ferringb@chromium.org>
|
|
move away from the current method, where we add wb_end() immediately
after wb_start() and then use the function addresses to calculate the
WB code size. Add a .lds script to expose __wb_end after wb_start() in
the .text section and then reference this variable in the WB size
calculation code.
BUG=chromium-os:23496
TEST=build on Seaboard. Verified that uboot.map has the correct address
assigned to __wb_end and that LP0 works reliably.
Change-Id: I170277f00b450d38063018453faf44d5a38abaaa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14682
|
|
split the LP0 code for tegra2 into common
LP0 code and chip specific warm boot code
BUG=chromium-os:23496
TEST=build for Seaboard
Change-Id: Id9756c08f61502affa8beee636d883d01468e6ec
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13799
|
|
As clock source for graphics related clocks is different
for Tegra2 and Tegra3, define it under platform specific
directories.
BUG=chromium-os:23496
TEST=Build ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi.
Original work by -
Mayuresh Kulkarni <mkulkarni@nvidia.com>
Change-Id: I6cee11df5e75eaf3836565c4fa4f3ab3e45d8cac
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14700
|
|
Set display parent clock separately for Tegra2 and Tegra3.
BUG=chromium-os:23496
TEST=Built ok for Cardhu Walgui and Seaboard. Tested on Waluigi.
Change-Id: Ie03d37b8dda77dcfcb72e70c34e769a23323e598
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14697
|
|
Add a case for returning RAM size as 2GB by reading
PMC scratch20 register.
BUG=chromium-os:23496
TEST=Build ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi.
Change-Id: I5dc8fdf7cd9718e5dd2ca24cd1f467c5b6e9a6aa
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14696
|
|
Move pwfm.c and display.c under common folder tegra-common.
BUG=chromium-os:23496
TEST=Built ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi.
Change-Id: I23c5f02270dde7bfdd6e1d26ed9984385986194e
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14694
|
|
While we wait for the new relocation stuff to come down from upstream,
this uses memset/memcpy() to do the business. Saves about 20ms on boot.
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: I958b9f53f27c67d4da2fa0f7a2148c59ed48f7aa
Reviewed-on: https://gerrit.chromium.org/gerrit/13215
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
When DEBUG is enabled, display important clocks during init.
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: Ic27e7d79bdcd9cf44d94ec25c52fc8776ddc7d04
Reviewed-on: https://gerrit.chromium.org/gerrit/13205
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
Some clocks cannot be set to the final value until we have the fdt
and know what PLLP should be set to. For now the only example is
coresight - so this adds a call to update this clock once the A9
is up and running with the fdt.
BUG=chromium-os:23496
TEST=build and boot on Seaboard, T33, Kaen
Change-Id: I7a07306cfb0a24cec4dcdb08cac78659a1afc73f
Reviewed-on: https://gerrit.chromium.org/gerrit/12251
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
This setting is now in the fdt, so remove the CONFIG item.
BUG=chromium-os:23496
TEST=build and boot on Seaboard, T33, Kaen
Change-Id: I336a6cc2140c725fdda85330efe617f82f205a90
Reviewed-on: https://gerrit.chromium.org/gerrit/12250
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
Since PLLP can be set to two different values, make it a parameter
to the function that sets up the PLLs.
BUG=chromium-os:23496
TEST=build and boot on Seaboard, T33, Kaen
Change-Id: I81ccc1cc3356796793ec2dd4ab22ed7fbd52f01d
Reviewed-on: https://gerrit.chromium.org/gerrit/12245
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
This is using the latest patch recommendation from Dilan at Nvidia, we adjust
the ordering to clear bypass earlier and remove the delay.
This patch was run successfully for over 2000 reboots.
BUG=chrome-os-partner:6145
TEST=Manual
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Change-Id: I9ef2f12d5c8abae86791f50b0f5e0e5a4249d947
Reviewed-on: https://gerrit.chromium.org/gerrit/12385
Reviewed-by: Micah Catlin <micahc@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
|
|
This function is better off in architecture code than board code.
This is quite an invasive change unfortunately.
BUG=chromium-os:23496
TEST=build and boot on Seaboard, T33, Kaen
Change-Id: I17764b134c25b684666d2c0fae2d255ac80e61b1
Reviewed-on: https://gerrit.chromium.org/gerrit/12244
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
|
|
intermittent hang
Currently with 200uS delay after PLL for stability.
BUG=chrome-os-partner:6145
TEST=None
Originaly-Reviewed-on: https://gerrit.chromium.org/gerrit/11091
Originaly-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Originaly-Tested-by: Bernie Thompson <bhthompson@chromium.org>
Originaly-Commit-Ready: Katie Roberts-Hoffman <katierh@chromium.org>
Originaly-Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Change-Id: Idcb95d4698ea856785be8a8232c08c89309af887
Reviewed-on: https://gerrit.chromium.org/gerrit/12158
|
|
Signed-off-by: Tom Warren <twarren@nvidia.com>
BUG=chromium-os:21033
TEST=built Seaboard & Waluigi OK. Booted my Waluigi to cmd prompt OK.
MMC, SPI and I2C still work fine, as does UART.
More can be done at a later date to cleanup AP20.c for T30 (and
rename/move it, since AP20 is a T2x name) and use new T30 V/W clock
enables/resets/sources/etc.
Change-Id: Ia3a86c519481fffde6926e1fece1dcf898d199c9
Reviewed-on: https://gerrit.chromium.org/gerrit/11911
Tested-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
|
|
U-Boot Makefiles contain a number of tests for compiler features etc.
which so far are executed again and again. On some architectures
(especially ARM) this results in a large number of calls to gcc.
This patch makes sure to run such tests only once, thus largely
reducing the number of "execve" system calls.
Example: number of "execve" system calls for building the "P2020DS"
(Power Architecture) and "qong" (ARM) boards, measured as:
-> strace -f -e trace=execve -o /tmp/foo ./MAKEALL <board>
-> grep execve /tmp/foo | wc -l
Before: After: Reduction:
==================================
P2020DS 20555 15205 -26%
qong 31692 14490 -54%
As a result, built times are significantly reduced, typically by
30...50%.
Change-Id: I6e8c7c37cd13c56cb64d0a410514f2b9dc2d5adb
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Albert Aribaud <albert.aribaud@free.fr>
cc: Graeme Russ <graeme.russ@gmail.com>
cc: Mike Frysinger <vapier@gentoo.org>
(cherry picked from commit 77d94d2d86c055f015734cc4cd972a5de30fc5a2)
Reviewed-on: https://gerrit.chromium.org/gerrit/11806
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
|
|
Signed-off-by: Tom Warren <twarren@nvidia.com>
BUG=chromium-os:21033
TEST=Built and booted OK on my Waluigi. UART is OK, mmc, spi, i2c OK.
Note that this is only valid with CONFIG_SYS_PLLP_BASE_IS_408MHZ.
No affect on Tegra2. Seaboard builds fine, BTW.
Change-Id: I05a367afd1e78a2170d7308a658ce64017850ca0
Reviewed-on: https://gerrit.chromium.org/gerrit/11811
Tested-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
|
|
Signed-off-by: Tom Warren <twarren@nvidia.com>
BUG=none
TEST=built Seaboard and Waluigi AOK
Change-Id: Ia860abf5ef3af66b3a39d4c57192455986b7a4f4
Reviewed-on: https://gerrit.chromium.org/gerrit/11704
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
Commit-Ready: Doug Anderson <dianders@chromium.org>
|
|
Signed-off-by: Tom Warren <twarren@nvidia.com>
BUG=none
TEST=built Seaboard and Waluigi OK. Booted Waluigi OK.
Change-Id: I1bfbe03945d7dae44e0840349b9698fc08cef07d
Reviewed-on: https://gerrit.chromium.org/gerrit/11504
Tested-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
|
|
Set CPU clock initially to 312Mhz; once CPU voltage is
raised, CPU clock will then be raied to 1.2GHz (for T25)
or 1.0GHz (for T20).
BUG=chrome-os-partner:5914
TEST=Build and test on Seaboard
Change-Id: I0c95a1df6b87c896daca8c03c9dc33b245764621
Reviewed-on: https://gerrit.chromium.org/gerrit/11199
Tested-by: Yen Lin <yelin@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Doug Anderson <dianders@chromium.org>
|
|
This adds support for T30 init to ap20.c, and modifies the board file
to cope with it also. The only thing missing at this point is the
pinmux setup.
BUG=chromium-os:21033
TEST=build and boot on Seaboard
Change-Id: I3e75245c1fdb99bc15eadcf60b173e6f0d9bb56c
Reviewed-on: http://gerrit.chromium.org/gerrit/8704
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
The pinmux functions for Tegra3 are quite different from Tegra2, since
we can adjust the setting for each individual pin. We try to keep the
same top-level interface where possible.
(sjg@chromium.org tidied up for 80cols)
BUG=chromium-os:21033
TEST=build and boot on Seaboard
Change-Id: I5bb109e73dc69c3424fe71978417b3f2b210a540
Reviewed-on: http://gerrit.chromium.org/gerrit/8692
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
Rather than hard-code this, we find out the amount of DRAM we have
using the official function.
BUG=chromium-os:21033
TEST=build and boot on Seaboard
Change-Id: Ibb20f1babc149457857292336ac588cf97fe35fa
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/8702
|
|
We will want arch_cpu_init() for both T20 and T30, so move it into the
common area.
BUG=chromium-os:19004
TEST=build and boot on seaboard
Change-Id: I5d3a1d59da9f8f2300ddce46469fe55caf27b482
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/8691
|
|
This comment is no longer needed
BUG=chromium-os:19004
TEST=build and boot on Seaboard
Change-Id: Icd2f92f293551173b134d300c8443a6efac63405
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/8690
|
|
The 216MHz PLLP is not always wanted - this adds support for 408MHz which
will be used on T30.
BUG=chromium-os:19004
TEST=build and boot on Seaboard
Change-Id: I4c053b5a9db4efb7b926ad2c9072f392d24033c9
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/8689
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
|
|
This adds ap20_get_num_cpus() which returns the number of CPUs in the
system, and adjusts a clock function to use it.
BUG=chromium-os:19004
TEST=build and boot on Seaboard
Change-Id: If7b56a2cecfb3d856308cac43dfcb32d3f1fef14
Reviewed-on: http://gerrit.chromium.org/gerrit/8688
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
The Tegra family has an ARMv4T chip which runs board_init_f(). It does not
support the BLX instruction which the init_sequence function table generates.
The easiest fix is to build this file for ARMv4T on Tegra.
The alternative is to move the arch_cpu_init() call out of the init
sequence. But that fix would not make the reason for the change so obvious.
There is no code size impact.
BUG=chromium-os:19353
TEST=build and boot on Seaboard
Change-Id: Idb0ab17bd0839c472cda7bf4940522245792e328
Reviewed-on: http://gerrit.chromium.org/gerrit/8684
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
In board_init_f() the gd->bd pointer is not valid when dram_init() is called.
This only avoid dying because DRAM is at zero. The common ARM routine sets
up the banks in the same way anyway, so we can just remove this code.
BUG=chromium-os:19353
TEST=build and boot on Seaboard
Change-Id: I81660e67d265031a73b416beaba64ba5a9cbc99d
Reviewed-on: http://gerrit.chromium.org/gerrit/8681
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
The flow controller exists in both T20 and T30, so move it into the
tegra-common directory.
BUG=chromium-os:19004
TEST=build and boot on seaboard
Change-Id: If6b7fea7dc3969139dfeadcf856b8d43d7eb875a
Reviewed-on: http://gerrit.chromium.org/gerrit/8642
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
This is needed by both T2x and T3x.
BUG=chromium-os:19004
TEST=build and boot on seaboard
Change-Id: I896719336126346c540bbae0c0559302189460ef
Reviewed-on: http://gerrit.chromium.org/gerrit/8641
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
This is needed by both T2x and T3x.
BUG=chromium-os:19004
TEST=build and boot on seaboard
Change-Id: I27113943da1e2dd3045f139938bc0c45998a0170
Reviewed-on: http://gerrit.chromium.org/gerrit/8639
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
This is needed by both T2x and T3x.
BUG=chromium-os:19004
TEST=build and boot on seaboard
Change-Id: I89c132f9d857a76ee03f24ec910619df00a6d4ac
Reviewed-on: http://gerrit.chromium.org/gerrit/8638
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
This is needed by both T2x and T3x.
BUG=chromium-os:19004
TEST=build and boot on seaboard
Change-Id: Idc12f106caaaf7601de8e66d8440840375eb9c42
Reviewed-on: http://gerrit.chromium.org/gerrit/8637
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
This is needed by both T2x and T3x.
BUG=chromium-os:19004
TEST=build and boot on seaboard
Change-Id: I03cb8e7b189cae0efb58d1ceed55a1e0dcd57c7f
Reviewed-on: http://gerrit.chromium.org/gerrit/8636
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
This adds the most basic Tegra30 support to U-Boot, by making use of
existing tegra2 code and adding what is necessary to build.
BUG=chromium-os:19004
TEST=build and boot on T30 board
Change-Id: If75599b2e76dbec3281fffb8a244b6145e9648cc
Reviewed-on: http://gerrit.chromium.org/gerrit/7130
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
Rather than __bss_end, define a new symbol which sets the end boundary of
code to be relocated by relocate_code(). This allows us to add code after
the BSS section which is still relocatable.
BUG=chromium-os:17053
TEST=build and boot U-Boot on seaboard
Change-Id: Ice784ee65ab8cbb7d2b996dc53c722c5dd9315c0
Reviewed-on: http://gerrit.chromium.org/gerrit/7660
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
Change tegra2 to tegra to make it more generic.
BUG=chromium-os:19004
TEST=build and boot on Seaboard
Change-Id: Iad6de3bb6cc6031167862054b78a57f66dea9cd5
Reviewed-on: http://gerrit.chromium.org/gerrit/7127
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
BUG=chromium-os:19004
TEST=build and boot on Seaboard
Change-Id: I4ed198fe5a6cc920634c21039d29ab98bcb9f49c
Reviewed-on: http://gerrit.chromium.org/gerrit/7126
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
This moves everything except the query_sdram_size() function into a common
board.c file.
BUG=chromium-os:19004
TEST=build and boot on Seaboard
Change-Id: I4578f08cd4cfde5e9e28ff800d7a12dbb8e13841
Reviewed-on: http://gerrit.chromium.org/gerrit/7125
Reviewed-by: Yen Lin <yelin@nvidia.com>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
This code is required for Tegra30 also, so we move it into a common
directory.
BUG=chromium-os:19004
TEST=build and boot on Seaboard
Change-Id: I9af13892861f54c0d7da6d4f9ee0715bc5ab6357
Reviewed-on: http://gerrit.chromium.org/gerrit/7124
Reviewed-by: Yen Lin <yelin@nvidia.com>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
|
|
We want to move to the idea of drivers and boards using generic tegra
include files, and have these include files deal with the tegra2/3
differences. This will make it easier to share code between tegra2/3.
BUG=chromium-os:19004
TEST=build and boot on Seaboard
Change-Id: I9c4eec30707e41678fb307982a34fe383694ba16
Reviewed-on: http://gerrit.chromium.org/gerrit/7000
Reviewed-by: Yen Lin <yelin@nvidia.com>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
|
|
Previously we ran the T25 at 1.2GHz before increasing the voltage
to the required level. This change starts up the PLLX at 1.0GHz and then
increases it later after the i2c and pmc init.
BUG=chromium-os:18706
TEST=build and boot on Aebl; verify that the time for board_init_r()
is more now, but from then on the times equalize:
Old:
Timer summary in microseconds:
Mark Elapsed Stage
0 0 reset
298,296 298,296 arch_cpu_init AVP
302,655 4,359 arch_cpu_init A9
302,697 42 arch_cpu_init done
302,699 2 board_init_f start
363,154 60,455 board_init_r start
612,030 248,876 main_loop
612,260 230 do_vboot_twostop
614,534 2,274 twostop_init
637,085 22,551 twostop_select_and_set_main_firmware
905,883 268,798 twostop_main_firmware
1,345,804 439,921 bootm_start
1,504,462 158,658 start_kernel
New:
Timer summary in microseconds:
Mark Elapsed Stage
0 0 reset
298,326 298,326 arch_cpu_init AVP
302,686 4,360 arch_cpu_init A9
302,730 44 arch_cpu_init done
302,732 2 board_init_f start
364,922 62,190 board_init_r start
613,893 248,971 main_loop
614,127 234 do_vboot_twostop
616,402 2,275 twostop_init
638,970 22,568 twostop_select_and_set_main_firmware
910,145 271,175 twostop_main_firmware
1,350,278 440,133 bootm_start
1,508,911 158,633 start_kernel
Change-Id: Ie5fea5fd02ef706d1b81b6a181510769a568fdd6
Reviewed-on: http://gerrit.chromium.org/gerrit/6130
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|