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2014-11-27arm: vf610: improve evaluation of reset sourceStefan Agner
Improve the evaluation of the reset source. Bit description according to latest reference manual rev. 7.
2014-10-23arm: vf610: add SoC detectionStefan Agner
Vybrid product family consists of several rather similar SoC which can be determined by softare during boot time. This allows to use the variable ${soc} for Linux device tree files.
2014-10-23arm: vf610: enable cachesStefan Agner
Enables caches which provides a rather huge speedup of the boot loader. Also mark the on-chip RAM as cachable since this is the area U-Boot runs from.
2014-10-23vf610: improve CPU type detectionStefan Agner
Detect VF5xx CPU's by reading the CPU count register. Also we can guess the second number of the CPU type (VF6x0) which indicates the presence of a L2 cache.
2014-10-14Merge tag 'v2014.10' into 2014.10-toradex-nextMarcel Ziswiler
Prepare v2014.10
2014-10-11Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-10-11ARM: cache_v7: Various minor cleanupsThierry Reding
Remove two gratuituous blank lines, uses u32 (instead of int) as the type for values that will be written to a register, moves the beginning of the variable declaration section to a separate line (rather than the one with the opening brace) and keeps the function signature on a single line where possible. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-10-10ARM: OMAP5+: sata: Move scsi_scan() to the right placeRoger Quadros
scsi_scan() must be called as part of scsi_init() and not as part of sata_init(). Signed-off-by: Roger Quadros <rogerq@ti.com>
2014-10-10OMAP5+: sata/scsi: Implement scsi_init()Roger Quadros
On OMAP platforms, SATA controller provides the SCSI subsystem so implement scsi_init(). Get rid of the unnecessary sata_init() call from dra7xx-evm and omap5-uevm board files. Signed-off-by: Roger Quadros <rogerq@ti.com>
2014-10-10Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-10-09arm: tegra: initial support for apalis t30Marcel Ziswiler
This patch adds board support for the Toradex Apalis T30 a computer on module which can be used on different carrier boards. For the sake of ease of use we do not distinguish between different carrier boards for now as the base module features are deemed sufficient enough for regular booting. The following functionality is working so far: - eMMC boot and environment storage - Gigabit Ethernet (once Thierry's PCIe as well as my E1000 resp. i210 fixes hit mainline) - MMC/SD cards (both 8-bit as well as 4-bit slot) - USB client/host (dual role port as client e.g. for DFU/UMS, other two ports as host) Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit 90a565acf3a18c61170ec0e0b2046c98cb7ecc85)
2014-10-09arm: rmobile: r8a7794: Skip initialize L2 cacheNobuhiro Iwamatsu
rmobile/lowlevel_init_ca15.S are common in r8a7790, r8a7791 and r8a7794 of rmobile SoCs. The initialize L2 cache in lowlevel_init_ca15.S only needed for Cortex-A15. The r8a7794 is Cortex-A7, not Cortex-A15. This adds Skip to initialize L2 cache when r8a7794. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-10-09arm: rmobile: r8a7791: Fix initialize L2 cacheNobuhiro Iwamatsu
rmobile/lowlevel_init_ca15.S are common in r8a7790 and r8a7791 of rmobile SoC. But L2 cache of r8a7791 does not use L2CTLR[5]. This adds fix to set L2CTLR [5] only when the r8a7790. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-10-09arm: rmobile: Remove unnecessary initialization for l2ctlrNobuhiro Iwamatsu
This removes duplicate initialization of l2ctlr. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-10-08Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD
The single file conflict below is actually trivial. Conflicts: board/boundary/nitrogen6x/nitrogen6x.c
2014-10-08armv7: s5pc1xx: improve cache handlingRobert Baldyga
Move cache handling code to C file, and add enable_caches() and disable_caches() functions. Signed-off-by: Robert Baldyga <r.baldyga@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-10-08samsung: Enable device tree for smdkc100Simon Glass
Change this board to add a device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-10-08samsung: Enable device tree for s5p_goniSimon Glass
Change this board to add a device tree. This also adds a pinmux header file although it is not used as yet. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-10-08config: Move smdkv310 to use common exynos4 fileSimon Glass
Most of the smdkv310 features are common with other exynos4 boards. To permit easier addition of driver model support, use the common file and add a device tree file. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-10-07Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2014-10-06arm: socfpga: Add command to control HPS-FPGA bridgesMarek Vasut
Add command to enable and disable the bridges between HPS and FPGA. This patch does have a checkpatch issue with the assembler portion, checkpatch correctly complains that there should be no whitespace before quoted newline. I do not agree that fixing this specific checkpatch issue will improve the readability, thus this one is not addressed. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de>
2014-10-06arm: socfpga: Move cache_enable to CPU codeMarek Vasut
Move icache_enable() and dcache_enable() function calls from board code into the CPU code and into the enable_caches() function. This is how the cache enabling code was designed to work. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: nic301: Add NIC-301 configuration codePavel Machek
Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA . The code sets the access permissions for the CPU to the AMBA slaves such that the CPU can access them in both secure and non-secure mode. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: pl310: Map SDRAM to 0x0Marek Vasut
Configure the PL310 address filter to make sure DRAM is mapped to 0x0. This code also configures the "remap" register of NIC-301 and sets the required 'mpuzero' bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: sysmgr: Add FPGA bits into system managerMarek Vasut
Add missing system manager bits from Altera U-Boot to make the code comparable. These are the bits which depend on the FPGA manager. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: reset: Add function to reset FPGA bridgesMarek Vasut
Add function to enable and disable FPGA bridges. This code is used by the FPGA manager to disable the bridges before programming the FPGA and will later be also used by the initialization code for the chip to put the chip into well defined state during startup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: fpga: Add SoCFPGA FPGA programming interfacePavel Machek
Add code necessary to program the FPGA part of SoCFPGA from U-Boot with an RBF blob. This patch also integrates the code into the FPGA driver framework in U-Boot so it can be used via the 'fpga' command. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move the not-CPU specific stuff into drivers/fpga/ and base this on the cleaned up altera FPGA support.
2014-10-06arm: socfpga: misc: Align print_cpuinfo() outputPavel Machek
Cosmetic change to the print_cpuinfo() function output. Align the output with the rest of initial output produced by U-Boot. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: misc: Add SD controller initPavel Machek
Add CPU function to register and initialize the dw_mmc SD controller. This allows us to use the HPS SDMMC block. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: misc: Add proper ethernet initializationPavel Machek
Add function to initialize the EMAC blocks upon board startup. The preprocessor guards against building on SoCFPGA-VT and against SPL build are not needed as those are handled implicitly via both SPL framework and the socfpga_cyclone5.h config file, which will not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: reset: Add EMAC reset functionsMarek Vasut
Add functions to reset the EMAC ethernet blocks. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: timer: Pull the timer reload value from config fileMarek Vasut
The timer reload value is a property of the timer hardware and there is no reason for this to be configurable. Place this into the timer driver just like on the other hardware. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: clock: Sync with reference codeMarek Vasut
Add the missing pieces from the reference clock code from Altera. This puts the code on par with the Altera U-Boot fork for all but the SDRAM self-refresh bits, which are not part of this patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: clock: Clean up bit definitionsMarek Vasut
Clean up the clock code definitions so they are aligned with mainline standards. There are no functional changes in this patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: clock: Trim down code duplicationMarek Vasut
Pull out functions to read frequency of Main clock VCO and PLL clock VCO as the code is duplicated multiple times. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: clock: Add code to read clock configurationPavel Machek
Add the entire bulk of code to read out clock configuration from the SoCFPGA CPU registers. This is important for MMC, QSPI and UART drivers as otherwise they cannot determine the frequency of their upstream clock. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Fixed the L4 MP clock divider and synced the clock code with latest rocketboards codebase (thanks Dinh for pointing this out)
2014-10-06arm: socfpga: clock: Drop nonsense inlining from clock manager codeMarek Vasut
The inlining is done by GCC when needed, there is no need to do it explicitly. Furthermore, the inline keyword does not force-inline the code, but is only a hint for the compiler. Scrub this hint. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: sysmgr: Clean up system managerMarek Vasut
Clean up the system manager register definition and add the missing register definitions in place. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: Add watchdog disable for socfpgaPavel Machek
This adds watchdog disable. It is neccessary for running Linux kernel. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)
2014-10-05ARM: UniPhier: add Kconfig and defconfigMasahiro Yamada
This commit allows to build Panasonic UniPhier family: PH1-LD4, PH1-Pro4, PH1-sLD8 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-10-05ARM: UniPhier: add UniPhier SoC support codeMasahiro Yamada
These are used by Panasonic UniPhier SoC family. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-29imx: mx6: Checking PLL2 PFD0 and PFD2 for periph_clk before PFD resetYe.Li
Checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source, do not reset this PFD to avoid system hang. Customers may set this in DDR script or use BT_FREQ to select low freq boot. Signed-off-by: Ye.Li <B37916@freescale.com>
2014-09-25kconfig: move CONFIG_OF_* to KconfigMasahiro Yamada
This commit moves: CONFIG_OF_CONTROL CONFIG_OF_SEPARATE CONFIG_OF_EMBED CONFIG_OF_HOSTFILE Because these options are currently not supported for SPL, the "Device Tree Control" menu does not appear in the SPL configuration. Note: zynq-common.h should be adjusted so as not to change the default value of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2014-09-24cosmetic: replace MIN, MAX with min, maxMasahiro Yamada
The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-22imx: Support i.MX6 High Assurance Boot authenticationNitin Garg
When CONFIG_SECURE_BOOT is enabled, the signed images like kernel and dtb can be authenticated using iMX6 CAAM. The added command hab_auth_img can be used for HAB authentication of images. The command takes the image DDR location, IVT (Image Vector Table) offset inside image as parameters. Detailed info about signing images can be found in Freescale AppNote AN4581. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
2014-09-21Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-09-19ARM: atmel: use pcr to enable or disable peripheral clockBo Shen
When use pcr (peripheral control register), then we won't need to care about the peripheral ID. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-17ARM: keystone: ddr3: workaround for ddr3a/3b memory issueMurali Karicheri
This patch implements a workaround to fix DDR3 memory issue. The code for workaround detects PGSR0 errors and then preps for and executes a software-controlled hard reset.In board_early_init, where logic has been added to identify whether or not the previous reset was a PORz. PLL initialization is skipped in the case of a software-controlled hard reset. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Keegan Garcia <kgarcia@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-09-17Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2014-09-13kconfig: remove redundant "string" type in arch and board KconfigsMasahiro Yamada
Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME} are specified in arch/Kconfig. We can delete the ones in arch and board Kconfig files. This commit can be easily reproduced by the following command: find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e ' /config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ { N s/\n[[:space:]]*string// } ' Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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