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The full range of LPC controllers should be accepted by u-boot when
looking for the SPI controller. The values come from Intel's
Panther_Point_EDS_v072.pdf (document #472178).
BUG=chrome-os-partner:7734
TEST=manual
. program the new image on the target
. reboot it and observe coming up to ChromeOS login screen
Change-Id: Id8f7068c3b48885f868a1f30e7927e678d2154b6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/19147
Reviewed-by: Jon Salz <jsalz@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/19310
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
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Link's MRC produces significantly more training data than
the one used on Stumpy/Lumpy.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
BUG=none
TEST=boot tested on Link
Change-Id: I9310c3bcc77fb4318db0635b97b115ab0eb7e5ec
Reviewed-on: https://gerrit.chromium.org/gerrit/18748
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Cardhu boards can use Atmel and Winbond SPI flash
parts - support both in one binary.
BUG=chromium-os:23496
TEST=build all OK, test on Cardhu.
'sf probe 0' returns:
SF: Detected AT25DF321A with page size 256, total 4 MiB.
sf read/write/erase all work OK.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Change-Id: I7df3abb030a49b572e1172ca77227cd4d63e0c21
Reviewed-on: https://gerrit.chromium.org/gerrit/18539
Reviewed-by: Mike Frysinger <vapier@chromium.org>
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BUG=none
TEST=check fmap on generated binary for unique names
Change-Id: Id1ac5cf223ec6a333fc8f4c587e972afd087f90d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/18435
Reviewed-by: Stefan Reinauer <reinauer@google.com>
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This saves 500ms in the RW BIOS path and still leaves 130K
overhead from the current U-boot size (372K) which should be
more than enough for any future updates on stumpy/lumpy.
This should be re-visited if/when vboot is smart enough to
just read+validate the actual binary within the section.
BUG=chrome-os-partner:8518
TEST=boot lumpy/stumpy through RW BIOS path and gather
timestamps to see 500ms improvement.
Change-Id: Ia714b4b95245f02f6e781247f820ca915bb403f5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/18372
Reviewed-by: Stefan Reinauer <reinauer@google.com>
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When U-boot is loaded via verified boot it starts at the
_x86boot_start entry point and promptly disables caching,
resulting in about a 500ms hit to boot time.
BUG=chrome-os-partner:8518
TEST=boot on lumpy with RW BIOS and gather timestamps
to observe 500ms less time spent in u-boot init.
Change-Id: I4eb1ad5ebcb20a156fef77452030e47a5e510115
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/18371
Reviewed-by: Stefan Reinauer <reinauer@google.com>
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For some still unknown reason writes to localtion 0xcf9 do not cause
the Link to reboot, they cause it to shut down instead. While this
will have to be investigated and fixed, this change modifies the code
to use the keyboard controller (implemented by the EC on Link) to
restart the system.
Once the 0xcf9 problem is resolved, this change could be reverted.
BUG=chrome-os-partner:8397
TEST=manual
. when u-boot tires restarting the system it now reboots. before
this change it would just shut down.
Change-Id: I8076f897304f705e20ec8f2e30cce17d7fdd31c4
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/18332
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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The code in this file tries to print an LBA using the format specifier
"%10ld", but when CONFIG_SYS_64BIT_LBA is turned on, the argument passed in
this position is a 64 bit value and isn't compatible. This change selects the
appropriate format specifier, the original or "10lld", based on whether
CONFIG_SYS_64BIT_LBA is turned on.
BUG=chrome-os-partner:8180
TEST=Built for Stumpy with BUILD_PART_FS_STUFF turned on and
CONFIG_SYS_64BIT_LBA enabled and disable, and saw the compile errors go away.
Change-Id: Ib80b1567ce07673aea2b47dfba9b3526b32f9de5
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/18219
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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BUG=chromium-os:23496
TEST=build on Waluigi, Seaboard, Cardhu
Change-Id: I9ccd3085fb551e9887815592e9b518b6944beda7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14474
Reviewed-by: Simon Glass <sjg@chromium.org>
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In the structure returned by the ATA identify device command, there are two
fields which describe the device capacity. One is a 32 bit data type which
reports the number of sectors as a 28 bit LBA, and the other is a 64 bit data
type which is for a 48 bit LBA. If the device doesn't support 48 bit LBAs,
the small value is the only value with the correct size. If it supports more,
if the number of sectors is small enough to fit into 28 bits, both fields
reflect the correct value. If it's too large, the smaller field has 28 bits of
1s, 0xfffffff, and the other field has the correct value.
The AHCI driver is implemented by attaching to the generic SCSI code and
translating on the fly between SCSI binary data structures and AHCI data
structures. It responds to requests to execute specific SCSI commands by
executing the equivalent AHCI commands and then crafting a response which
matches what a SCSI disk would send.
The AHCI driver now considers both fields and chooses the correct one when
implementing both the SCSI READ CAPACITY (10) and READ CAPACITY (16) commands.
BUG=chrome-os-partner:8180
TEST=Built and booted to ChromeOS with this code on a CRB with a 250 GB drive
and a Stumpy with a 16 GB drive. Checked the serial output to make sure U-Boot
reported the correct size. Forced the READ CAPACITY (10) command to saturate
so that the READ CAPACITY (16) command would be used and verified that that
also booted correctly on a CRB.
Change-Id: I31b662498f4c9657d70bb90400032c83e9d9c8da
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/18061
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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The generic SCSI code in U-Boot was only aware of the READ CAPACITY (10) SCSI
command which can detect the size of disks up to 2TB in size. If that size is
exceeded, it should then try the READ CAPACITY (16) command which returns a
64 bit block count value.
BUG=chrome-os-partner:8180
TEST=In conjunction with the next change, built and booted into ChromeOS on
the Emerald Lake 2 CRB with a 250 GB SSD. Did the same but forced the READ
CAPACITY (10) command to saturate and the code to fall back to READ CAPACITY
(16). Note that this code has not be tested with a real SCSI disk, just the
AHCI code pretending to be a SCSI disk as it historically has.
Change-Id: Ia0ee3fa1264649f25065658d5d368101d39ce614
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/18060
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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BUG=chrome-os-partner:8180
TEST=Built and booted on emeraldlake2 and Stumpy.
Change-Id: If14ff4930015fae36d421fd30ab5bd126c464db9
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/18059
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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These drivers wouldn't compile when the CONFIG_SYS_64BIT_LBA option is turned
on because the used fixed size data types in their exported functions when they
should have used lbaint_t for the block count parameter. That meant that when
the sizes happened to be the same, when using a 28 bit LBA, the driver would
build, but when it wasn't, a 48 bit LBA, things broke.
This change adjusts the signatures to use the right type and makes small
adjustments in the affected functions.
BUG=chrome-os-partner:8180
TEST=Built for emeraldlake2 with the CONFIG_SYS_64BIT_LBA option enabled and
saw its compile errors go away.
Change-Id: I7443b5976d3d06b82070344011fba46a28bd77de
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/18058
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
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BUG=chrome-os-partner:8180
TEST=Built u-boot for emeraldlake2.
Change-Id: Iae62f047ddc102fbf530e1f8f9af34939971a6a3
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/18057
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This uses a format which is not supported by the upstream dtc, so
remove this.
BUG=chromium-os:23249
TEST=emerge-tegra2_kaen chromeos-u-boot with new dtc
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I18b9420dbee20c2d115cc5ff1b13425faffe2a3e
Reviewed-on: https://gerrit.chromium.org/gerrit/17630
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In bug reports with screen shots of the firmware screens with tab
pressed, it would be extremely useful to see the version of the
currently running firmware and the read-only firmware, so output
this information.
BUG=none
TEST=press TAB at dev screen, see firmware versions printed on the
screen.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: If91d4b1da8a7f69ff797b0b00c507248139601cd
Reviewed-on: https://gerrit.chromium.org/gerrit/17002
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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cold_reboot() should wait until the reset kicks in, instead of
returning and continuing in an undefined code path. Without this
patch, vboot_twostop will return, and secure_boot() will start
printing an error message, which results in a sporadic # on
the screen when pressing space or ESC on the dev screen in order
to go to recovery mode.
BUG=chrome-os-partner:7683
TEST=boot to dev screen on lumpy, press ESC or space. Observe
there is no # character printed before going to recovery
mode.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ic2ee570032686e48603f0fb3b1ec9cbfae9451bc
Reviewed-on: https://gerrit.chromium.org/gerrit/17007
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
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This will trigger setting gbb.flags to 1 in cros_bundle_firmware so the
factory time is reduced.
GBB.flags will be changed in the factory process.
Also needs https://gerrit.chromium.org/gerrit/#change,16845
BUG=chrome-os-partner:7671
TEST=manual
emerge-stumpy chromeos-bootimage
gbb_utility -g --flags /build/stumpy/firmware/image.bin
Should report "flags: 0x00000001"
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ie05433ad737005bd5dcca2f88232b0a5bbd00df9
Reviewed-on: https://gerrit.chromium.org/gerrit/16113
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
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enable CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT
BUG=chromium-os:23496
TEST=build and boot on Cardhu
Change-Id: If21303468193c7f5f6ba1c0c0b7cd0ccb5a08c0e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13801
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enable CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT
BUG=chromium-os:23496
TEST=build and boot on Waluigi
Change-Id: I622d228d02767954ffa7e101ad6f5f5fb1146702
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13802
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BUG=chromium-os:23496
TEST=build and boot on Waluigi, Cardhu by enabling
CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT.
odification of the work done by:
a. Jimmy Zhang <jimmzhang@nvidia.com>
b. Yen Lin <yelin@nvidia.com>
c. Wei Ni <wni@nvidia.com>
Change-Id: If2fa63ccd23341694955bca25fb5cfc4a8a805ad
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13800
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warmboot_avp.h needs to be present in include/arch-tegra
in order to use it for Tegra3.
BUG=chromium-os:23496
TEST=build for Seaboard
Change-Id: I3f369194e4002e8257c9d2ff37253bc20733138d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/15394
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BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: I6d26502d1ecc393b266ffe06b540f59c595e19ae
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14811
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BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: Ifa06f941798ff242197dcd31f4091567d91fe4b2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14810
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BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: I74bb2418ab996e362060351de3ba7efd538ffd87
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14809
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BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: I20ac75c71d86d65ff422ff3f4f966a69718f4f91
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14808
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These registers would be useful for the warmboot code.
BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: I58f52b6b8653d72b2e842ee44bdf3632eff304a2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14690
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Would be useful for the warmboot code.
BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: I271f6cdcc0248337e516c2c32014c6ec4f08fb15
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14689
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These registers would be useful for the warmboot
code.
BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: I8da1ed3a382e1b65247236cb19f527f81d8ecaac
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14688
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We were not searching on the last PCI bus.
Fix the loop to go up to pci_last_busno() included.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run on Link with only one PCI bus active, see we can detect the
EHCI controllers.
Change-Id: Icdcd19df0c622039f56e7403c2616348b5d8b7d6
Reviewed-on: https://gerrit.chromium.org/gerrit/16481
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
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It turns out that running 'vbexport_test display' on coreboot
platforms fails to display bitmap images, sometimes reporting memory
corruption and rebooting the system.
The problem was twofold:
- the gbb pointer is not properly initialized (as it is supposed to
when CONFIG_HARDWARE_MAPPED_SPI is defined).
- the bitmap images block includes an element which in fact is not a
bitmap. When scanning the block, the test tried displaying all
elements, generating an error when this one-off element is
encountered.
This change fixes both issues.
BUG=chromium-os:26586
TEST=manual
. build a new chromeos-bootimage
. reboot the system stopping it in u-boot console dialogue
. run `vbexport_test display' command from the console
The test was failing before this change, it is passing now.
Change-Id: Iee9491d150b9ce5513f7446ab4df806d23e6d4d8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/16206
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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When a USB card reader is empty, it will return "Not Ready - medium not
present" as Key Code Qualifier. In that situation, it's useless waiting
for the full timeout since the result won't change until the user
inserts a card.
U-Boot mass storage returns empty mass storage devices with a size of 0,
skip them in the VBoot devices enumeration.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=On Link, run without a MMC card.
Change-Id: Iac37887742e5738e249f595e0413eec16b391fae
Reviewed-on: https://gerrit.chromium.org/gerrit/15582
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi
Change-Id: Iacd6fdb178afbfdb978dbe53bbe2766916bf26f9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14685
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BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: I32dbfa02ac1d6954b3a7e515914fbc0b6695f98b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14683
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USB keyboard initialization was added in twostop_boot as a hack.
However, if u-boot is running from one of the RW sections, twostop_boot
is never executed, instead the code proceeds to
twostop_readwrite_main_firmware() which was lacking the USB keyboard
initialization.
This patch adds USB keyboard initialization to the RW code path.
BUG=chrome-os-partner:7940
TEST=boot from RW section in dev mode, observe that USB keyboard is
working. (stumpy)
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ie49d14680a72c2216b4a68091ae6e6adcca91242
Reviewed-on: https://gerrit.chromium.org/gerrit/15913
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
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Add this special handle of Ctrl-Enter, which is converted into '\n'
by i8042 driver.
BUG=chrome-os-partner:6759
TEST=compile the firmware and update it to Lumpy; during the dev screen,
press Ctrl-Enter to trigger USB boot.
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Change-Id: Ifde312f4ef6de9b328dc22b96ca02a2a9ccf6068
Reviewed-on: https://gerrit.chromium.org/gerrit/15805
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Wai-Hong Tam <waihong@chromium.org>
Commit-Ready: Tom Wai-Hong Tam <waihong@chromium.org>
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Make Ctrl-Enter act like LF (Line Feed) such that u-boot can differentiate
it from pure Enter key. There are other Ctrl-(numeric keypad key)'s,
like Ctrl-[ for ESC (Escape) key, but they are not useful yet in current
u-boot. So keep the Ctrl-(key) and non-Ctrl-(key) tables the same except Enter.
This change is together with https://gerrit.chromium.org/gerrit/15749
BUG=chrome-os-partner:6759
TEST=compile the firmware and update it to Lumpy; during the dev screen,
press Ctrl-Enter to trigger USB boot.
Change-Id: Ie3197f7ba93ed63c851bdfb918c8e384c90977dd
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/15750
Reviewed-by: Simon Glass <sjg@chromium.org>
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split the LP0 code for tegra2 into common
LP0 code and chip specific warm boot code
BUG=chromium-os:23496
TEST=build for Seaboard
Change-Id: Ie04bf9ac17482a37afd0f4515dc3aafeb4f48ae7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/15883
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This reverts commit 4c7502242627f64d91432cb4958be5f93f65fbff
Don't think this is the cause of http://code.google.com/p/chromium-os/issues/detail?id=26116, but it was in the same batch so I'm reverting in the process.
Change-Id: Icc013ced6c22e29d569ee4ca8ef73522154ec1a8
Reviewed-on: https://gerrit.chromium.org/gerrit/15561
Reviewed-by: Brian Harring <ferringb@chromium.org>
Tested-by: Brian Harring <ferringb@chromium.org>
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This reverts commit 9a3fbb5f0b02382c7abe0cf40a4f08abbf269d05
Broke tegra2: http://code.google.com/p/chromium-os/issues/detail?id=26116
Change-Id: I7d35211c6ebce7a10750cb1033c6f8ba9a0f63bc
Reviewed-on: https://gerrit.chromium.org/gerrit/15560
Reviewed-by: Brian Harring <ferringb@chromium.org>
Tested-by: Brian Harring <ferringb@chromium.org>
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move away from the current method, where we add wb_end() immediately
after wb_start() and then use the function addresses to calculate the
WB code size. Add a .lds script to expose __wb_end after wb_start() in
the .text section and then reference this variable in the WB size
calculation code.
BUG=chromium-os:23496
TEST=build on Seaboard. Verified that uboot.map has the correct address
assigned to __wb_end and that LP0 works reliably.
Change-Id: I170277f00b450d38063018453faf44d5a38abaaa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14682
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split the LP0 code for tegra2 into common
LP0 code and chip specific warm boot code
BUG=chromium-os:23496
TEST=build for Seaboard
Change-Id: Id9756c08f61502affa8beee636d883d01468e6ec
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13799
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As clock source for graphics related clocks is different
for Tegra2 and Tegra3, define it under platform specific
directories.
BUG=chromium-os:23496
TEST=Build ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi.
Original work by -
Mayuresh Kulkarni <mkulkarni@nvidia.com>
Change-Id: I6cee11df5e75eaf3836565c4fa4f3ab3e45d8cac
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14700
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Assert occurs due to LCD max height was bigger than default
Maximum LCD height, causing 'panel_info' is not initialized.
Increase default Max LCD height as Waluigi has LCD height in
pixel more than 768.
Initialize global variable 'lcd_line_length' correctly.
'lcd_line_length' was not initialized before use, causing
initialization of dependent variables wrongly.
BUG=chromium-os:23496
TEST=Build ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi.
Change-Id: I24a9fc54541c861c48fd885e2d58d32786c31bf8
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14699
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For Waluigi, existing frame buffer address does not fall
under external memory map.
Setting it to the location set as per the default initialization.
BUG=chromium-os:23496
TEST=Build ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi.
Change-Id: I2284d43c11f4d6622344429508b1f99e30929f19
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14698
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Set display parent clock separately for Tegra2 and Tegra3.
BUG=chromium-os:23496
TEST=Built ok for Cardhu Walgui and Seaboard. Tested on Waluigi.
Change-Id: Ie03d37b8dda77dcfcb72e70c34e769a23323e598
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14697
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Add a case for returning RAM size as 2GB by reading
PMC scratch20 register.
BUG=chromium-os:23496
TEST=Build ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi.
Change-Id: I5dc8fdf7cd9718e5dd2ca24cd1f467c5b6e9a6aa
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14696
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For Tegra2, pinmuxing is done in each driver, For Tegra3
it is done at boot up time.
Handling it conditionally for Tegra2 and Tegra3.
BUG=chromium-os:23496
TEST=Build ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi.
Change-Id: I95e2dc4d46c0c47037611ff9177f2d8823c11d1f
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14695
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Move pwfm.c and display.c under common folder tegra-common.
BUG=chromium-os:23496
TEST=Built ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi.
Change-Id: I23c5f02270dde7bfdd6e1d26ed9984385986194e
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14694
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