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The 85xx code now relies on CONFIG_HAS_ETH0 to determine whether
to update TSEC1's device-tree node, so we need to add it
to all the boards with TSECs. Do this for 83xx and 86xx, too,
since they will eventually do something similar.
Signed-off-by: Andy Fleming <afleming@freescale.com>
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The PCIe bus that the ULI M1575 is connected to has no possible way of
needing more than the fixed amount of IO & Memory space needed by the ULI.
So make it use far less IO & memory space and have it use the shared LAW. This
free's up a LAW for PCIe1 IO space. Also reduce the amount of IO space needed
by each bus.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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It looks like we had a merge issue that duplicated a bit of code
in ft_board_setup. Also, we need to set CONFIG_HAS_ETH0 to get
the MAC address properly set in the device tree on boot for TSEC1
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Forgot to cast of_flat_tree to ulong.
Signed-off-by: Andy Fleming <afleming@freescale.com>
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The TSEC driver's PHY code waits a long time for autonegotiation to
complete, even if the link is down. The PHY knows the link is
down or up before autonegotiation completes, so we can short-circuit
the process if the link is down.
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Actually, fixed a large bug in the UEC for *all* platforms.
How did this ever work?
uec_init() did not follow the spec for eth_init(), and returned
0 on success. Switch it to return the link like tsec_init()
(and 0 on error)
The immap for the 8568 was defined based on MPC8568, rather than
CONFIG_MPC8568
CONFIG_QE was off
CONFIG_ETHPRIME was set to "Freescale GETH". Now is "FSL UEC0"
Fixed a comment about the ranges for CONFIG_ETHPRIME if TSEC_ENET is
enabled
Signed-off-by: Andy Fleming <afleming@freescale.com>
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The tsec_info structure and array has a "flags" field for each
ethernet controller. This field is the only reason there are
settings. Switch to defining TSECn_FLAGS for each controller
in the config header, and we can greatly simplify the array, and
also simplify the addition of future boards.
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Changes to the TSEC driver affect almost all 83xx, 85xx, and 86xx boards.
Now we can do a MAKEALL test on all of them!
Signed-off-by: Andy Fleming <afleming@freescale.com>
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The fix, "Fix where the #ifdef CFG_BOOTMAPSZ is placed"
neglected to *also* put the code inside the similar #ifdef
for CONFIG_OF_FLAT_TREE.
Signed-off-by: Andy Fleming <afleming@freescale.com>
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bzip2 requires a significant chunk of malloc space, and there isn't
enough room on mpc885ads (with only 8MB RAM) for both bzip2's malloc area
and a downloaded image at 0x400000.
Signed-off-by: Scott Wood <scottwood@freescale.com>
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microblaze CPU have problem with bios_emulator code.
Microblaze toolchain doesn't support PRAGMA PACK.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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This small CPCI750 update extends the board specific command
"show_config" to display the Marvell strapping registers and
extends the PCI IDE controller.
Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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Remove a leftover in net/tftp.c while we're at it.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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Minor path corrections needed to ensure buildability.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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Remove a leftover in net/tftp.c while we're at it.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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Commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924 "Fix initrd/dtb
interaction" put the new code outside of the #if defined(CONFIG_OF_LIBFDT)
when it should have gone inside of the conditional. As a result, it
broke non-LIBFDT board builds.
Also added a missing "not." to the comment.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
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Typically this causes scsi init to corrupt the
devlist and break the coninfo command.
Fix a compiler size warning.
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
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Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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The original code would wrongly relocate the blob to be right before
the initrd if it existed. The blob *must* be within CFG_BOOTMAPSZ,
if it is defined. So we make two changes:
1) flag the blob for relocation whenever its address is above BOOTMAPSZ
2) If the blob is being relocated, relocate it before kbd, not initrd
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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When CFG_POST_ETHER_EXT_LOOPBACK is defined, the ethernet POST
is not done using an internal loopback connection, but by assuming
that an external loopback connector is plugged into the board.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Merge to two at45.c files into a common file, split to at45.c and spi.c
Fix spelling error in DM9161 PHY Support.
Initialize at91rm9200 board (and set LED).
Add PIO control for at91rm9200dk LEDs and Mux.
Change dataflash partition boundaries to be compatible with Linux 2.6.
Signed-off-by: Peter Pearse <peter.pearse@arm.com>
Signed-off-by: Ulf Samuelsson <ulf@atmel.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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The PCI ID select values on the Arcadia main board differ depending
on the version of the hardware. The standard configuration supports
Rev 3.1. The legacy target supports Rev 2.x.
Signed-off-by Randy Vinson <rvinson@mvista.com>
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Author: Randy Vinson <rvinson@linuxbox.(none)>
Enable the PCI-to-ISA bridge in the VIA Southbridge located on the
Arcadia main board.
Signed-off-by: Randy Vinson <rvinson@mvista.com>
Signed-off-by: York Sun <yorksun@freescale.com>
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Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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This patch is against u-boot-mpc85xx.git of www.denx.com
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
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