| Age | Commit message (Collapse) | Author |
|---|
|
When ICSSG driver is enabled (CONFIG_TI_ICSSG_PRUETH=y) set
fw_storage_interface and fw_dev_part env variables.
These variables need be set appropriately in order to load differnet
ICSSG firmwares needed for ICSSG driver. By default the storage
interface is mmc and the partition is 1:2. User can modify this based on
their needs.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
When CONFIG_TI_ICSSG_PRUETH is enabled, add config name check for the
icssg2 overlay in board_fit_config_match() API.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
We want SPL to apply DTB overlays (e.g. ICSSG2 overlay) so enable
SPL_LOAD_FIT_APPLY_OVERLAY.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
Enable ICSSG driver in am65x_evm_a53_defconfig
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
Add ICSSG2 overlay and configuration to tispl and u-boot images.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
ICSSG2 provides dual Gigabit Ethernet support.
Add ICSSG2 ethernet node to an overlay k3-am654-icssg2.dts
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
The ICSSG IP on AM65x SoCs have two Industrial Ethernet Peripherals (IEPs)
to manage/generate Industrial Ethernet functions such as time stamping.
Each IEP sub-module is sourced from an internal clock mux that can be
sourced from either of the IP instance's ICSSG_IEP_GCLK or ICSSG_ICLK.
Add the IEP nodes for all the ICSSG instances.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
There are a few missing registers ranges in the udmap nodes
need to properly setup DMA for the am65x.
A fix has been added to the Linux kernel [0] to add these ranges and
merged. To keep DMA operational until the next DT sync from Linux, these
ranges were added to the *-u-boot.dtsi in the upstream u-boot [1].
Porting these DMA changes to ti-u-boot as these are needed for ICSSG
Ethernet driver to work.
And additional config register was added to the ringacc node in upstream
u-boot as part of DT sync from linux 6.7-rc1 [2]. Porting those changes
as well to ti-u-boot as those are also needed for ICSSG Ethernet driver to
work.
[0] https://lore.kernel.org/r/20231213135138.929517-2-vigneshr@ti.com
[1] https://source.denx.de/u-boot/u-boot/-/commit/5e00547e583f6d4349f3908d3491bf6ce0a8818c
[2] https://source.denx.de/u-boot/u-boot/-/commit/4dbdc84754ea2ad392ef7328da6d429cd8fd3c0a
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
The binding represents the MDIO controller as a child device tree
node of the MAC device tree node.
The U-Boot driver mostly ignores that child device tree node and just
hardcodes the resources it uses to support both the MAC and MDIO in a
single driver.
However, some resources like pinctrl muxing states are thus ignored.
This has been a problem with some device trees that will put some
pinctrl states on the MDIO device tree node.
Let's rework the driver a bit to create a dummy MDIO driver that we will
then get during our initialization to force the core to select the right
muxing.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
ICSSG firmware supports FDB commands. Add support to send FDB commands
from driver. Once rx_flow_id is obtained from dma, let firmware know that
we are using this rx_flow_id by sending a FDB command.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
This is the PURSS Ethernet driver for TI AM654 Sr2.0 and laterSoCs with
the ICSSG PRU Sub-system running EMAC firmware. This driver caters to
either of the slices of the icssg subsystem.
One and exactly one of the slices is supported as the u-boot ethernet
supports probing one interface at a time.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
Add icssg_queue.c file. This file introduces macros and APIs related to
ICSSG queues. These will be used by ICSSG Ethernet driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
Add icssg_config.h / .c and icssg_classifier.c files. These are firmware
configuration and classification related files. Add MII helper APIs and
MACROs. These APIs and MACROs will be later used by ICSSG Ethernet driver.
Also introduce icssg_prueth.h which has definition of prueth related
structures.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
Add firmware interface related headers and macros for ICSSG Ethernet
driver. These macros will be later used by the ICSSG ethernet driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
Add APIs to set a firmware_name to a rproc and boot the rproc with the
same firmware.
Clients can call rproc_set_firmware() API to set firmware_name for a rproc
whereas rproc_boot() will load the firmware set by rproc_set_firmware() to
a buffer by calling request_firmware_into_buf(). rproc_boot() will then
load the firmware file to the remote processor and start the remote
processor.
Also include "fs-loader.h" and make remoteproc driver select FS_LOADER in
Kconfig so that we can call request_firmware_into_buf() from remoteproc
driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
The fs-loader driver reads env storage_interface and uses it to load
firmware file into memory using the medium set by env. Update the driver
to use env fw_storage_interface as this variable is only used to load
firmwares. This is to keep all variables used by fs-loader driver with
'fw_' prefix. All other variables have 'fw_' prefix except for
storage_interface.
The env storage_interface will act as fallback so that the
existing implementations do not break.
Also update the FS Loader documentation accordingly.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
Use ring_idx to pair rings. ring_idx will be same as tx flow_id for all
non-negative flow_ids. For negative flow_ids, ring_idx will be tchan->id
added with bchan_cnt.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
Update rm-cfg.yaml and tifs-rm-cfg.yaml to account for the
latest changes added in the K3 Resource Partitioning Tool.
The change enables resource sharing between A72_2 and MAIN_0_R5_0
for the BCDMA CSI RX and TX channels, J784S4 supports upto 12
CSI cameras and 16 channels would not be enough for all such use
cases for RTOS and Linux, thus sharing of resources in needed.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
|
|
Add config fragment to enable USB MSC boot.
USB Host boot is supported only from USB0 port. By default USB0
is configured in peripheral mode to support DFU. Inorder to support
USB Host boot, "dr_mode" property needs to be changed from "peripheral"
to "host" in the device tree.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
|
|
Add config fragment to enable USB DFU support
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
|
|
Update the USB0, USB1 nodes and enable them.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
|
|
USB1 controller on J722S and AM62P are from different vendors.
Redefine the USB1 node description for J722S by deleting the
node inherited from AM62P dtsi.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
|
|
Add SERDES0 and its wrapper description to support USB3
and SGMII interfaces.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
|
|
Enable CONFIG_BOARD_HAS_32K_RTC_CRYSTAL to enable 32k crystal.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
|
|
Currently, the rtc clock is being set to 32552 instead of exact 32k.
Enable the 32k crystal and setup debounce conf registers by invoking
board_rtc_init call so that rtc clock is set accurately to 32768.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
|
|
Include the header file instead of c file.
Fixes: d36ad81d25a9 ("board: ti: common: add rtc setup to common folder")
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
|
|
Add the header file for rtc with the macros and declarations to avoid
including '.c' file in the platform evm.c files.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
|
|
With the latest TIFS firmware, an additional virtual interrupt and
event is reserved for TIFS usage on am62x, am62ax and am62px devices.
Update the rm-cfg to reflect this new reservation.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
|
|
Enable AVS and TPS6287X configs
Signed-off-by: Keerthy <j-keerthy@ti.com>
|
|
Add driver for TPS6287x step down convertors
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
|
|
Enable probing of AVS node in R5 SPL.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
|
|
Add AVS and Tulip TPS62873 regulator node.
Signed-off-by: Keerthy <j-keerthy@ti.com>
|
|
Enable CONFIG_SPL_DRIVERS_MISC, CONFIG_SPL_MISC, CONFIG_ESM_K3
to probe the Main ESM and MCU ESM nodes.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
|
|
On AM62A and AM62P devices, it is possible to route Main ESM error
events to MCU ESM. MCU ESM high error output can trigger the reset
logic to reset the device. So, for these devices we have Main ESM and
MCU ESM nodes in the device tree. Add functions to probe these nodes
if CONFIG_ESM_K3 is enabled.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
|
|
Remove 'reserved' status for MCU ESM node in AM62P device tree
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
|
|
Add Main ESM and MCU ESM nodes to the AM62A device tree.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
|
|
Enable CONFIG_TI_COMMON_CMD_OPTIONS and CONFIG_CMD_DDRSS to use the
'ddrss' command for testing ECC.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
|
|
Introduce a new version of the Keystone-II "ddr" command
for testing the inline ECC support in the DDRSS bridge
available on K3 devices. The ECC hardware support in
K3's DDRSS and the test method differ substantially from
what we support in the K2 variant of the command. The
name of the new command is "ddrss".
The ECC test procedure follows these steps:
1) Flush and disable the data cache.
2) Shrink the protected ECC R0 range.
3) Flip a bit outside the shrunk range.
4) Restore the range to original.
5) Read the modified value (corrected).
6) Re-enable the data cache.
This which will cause the 1-bit ECC error count to increase
while the read will return the corrected value.
The K3 version of the command preserves the syntax for the
"ecc_err" argument.
Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
|
|
Add ss_cfg memory region which maps the DDRSS configuration region
for the memory controller node.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
|
|
size when ECC is enabled
As there are few redundant functions in board/ti/*/evm.c files, pull
them to a common location of access to reuse and include the common file
to access the functions.
Call k3-ddrss driver through fixup_ddr_driver_for_ecc() to fixup the
device tree and resize the available amount of DDR, if ECC is enabled.
Otherwise, fixup the device tree using the regular
fdt_fixup_memory_banks().
Modify fixup_ddr_driver_for_ecc() to make the function agnostic to the
number of DDR controllers present.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
|
|
Add the bootph-pre-ram property to the memory node so that it can be
accessed by FDT functions at R5 stage.
The fdt_setup_mem*() functions require the memory node to be able to
initialize and set the size of the DRAM banks. For this purpose, make
sure all memory nodes are present and standardized, and add them if not.
Also make sure they have bootph-pre-ram property so that it can be
accessible at R5 SPL stage.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
|
|
Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL
only when the config has been enabled.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
|
|
Enable ECC 1-bit error, 2-bit error, multiple 1-bit error interrupts
by setting the respective bits in the DDRSS_V2A_INT_SET_REG register.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
|
|
Setup the ECC region's start and range using the device private data,
ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and
range of ECC regions from 32 bits to 64 bits to accommodate for
DDR greater than or equal to 4GB.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
|
|
restricted to 32 bits' issue
As R5 is a 32 bit processor, the RAM banks' base and size calculation
is restricted to 32 bits, which results in wrong values if bank's base
is greater than 32 bits or bank's size is greater than or equal to 4GB.
So, add k3_ddrss_ddr_bank_base_size_calc() to get the base address and
size of RAM's banks from the device tree memory node, and store in a
64 bit device private data which can be used for ECC reserved memory
calculation, Setting ECC range and Fixing up bank size in device tree
when ECC is enabled.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
|
|
The 1-bit inline ECC support in TI's DDRSS bridge requires
the configured memory regions to be preloaded with a pattern
before use. This is done by the k3-ddrss driver from the
R5 SPL in a 'for' loop. It takes around 10 seconds to fill
2GB of memory, for example. Memset can cut the time in half
and using DMA currently yields a similar result.
The BIST engine of DDR controller provides support for
initializing any memory region with a pattern. This
bypasses the DDRSS bridge, so the required inline ECC
data is not computed and populated in the memory. For
some values like zero, the computed ECC syndrome is also
zero and we can use these values to preload the memory
from the DDR controller, without the assistance of the
bridge.
The registers involved in the process are described in the
'DDR controller registers' topic in [1] AM62 and [2] J721E
reference manuals.
The patch replaces the 'for' loop memory fill function with
the BIST memory initialization procedure. This cuts the time
to preload the 2GB memory from 10 seconds down to 1 second.
The bist preload function uses the lpddr4 APIs in the k3-ddrss,
so this is compatible with devices with both 16-bit LPDDR4 and
32-bit LPDDR4 interfaces (e.g J721E).
[1] AM62x: https://www.ti.com/lit/pdf/spruiv7
[2] DRA829/TDA4VM: https://www.ti.com/lit/zip/spruil1
Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
|
|
Update to the latest RM (Resource Management) auto-generated YAMLs.
This accommodates CSI INT_AGG fix for Linux and RTOS both.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
|
|
Update the delay values for various speed modes supported, based on
the revised august 2021 J721E Datasheet [1].
[1] https://www.ti.com/lit/ds/symlink/tda4vm.pdf,
(SPRSP36J - FEBRUARY 2019 - REVISED AUGUST 2021)
- Table 7-77. MMC0 DLL Delay Mapping for All Timing Modes and
- Table 7-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
|
|
For R5 SPL, we include the NAND support in the board DTS file
(k3-am642-r5-evm.dts) as there is no way to use overlay in
BootROM at the moment.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
|
|
Include the configuration required for booting from NAND.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
|
