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Enable AVS and TPS6287X configs
Signed-off-by: Keerthy <j-keerthy@ti.com>
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Add driver for TPS6287x step down convertors
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
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Enable probing of AVS node in R5 SPL.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
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Add AVS and Tulip TPS62873 regulator node.
Signed-off-by: Keerthy <j-keerthy@ti.com>
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Enable CONFIG_SPL_DRIVERS_MISC, CONFIG_SPL_MISC, CONFIG_ESM_K3
to probe the Main ESM and MCU ESM nodes.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
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On AM62A and AM62P devices, it is possible to route Main ESM error
events to MCU ESM. MCU ESM high error output can trigger the reset
logic to reset the device. So, for these devices we have Main ESM and
MCU ESM nodes in the device tree. Add functions to probe these nodes
if CONFIG_ESM_K3 is enabled.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
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Remove 'reserved' status for MCU ESM node in AM62P device tree
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
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Add Main ESM and MCU ESM nodes to the AM62A device tree.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
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Enable CONFIG_TI_COMMON_CMD_OPTIONS and CONFIG_CMD_DDRSS to use the
'ddrss' command for testing ECC.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
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Introduce a new version of the Keystone-II "ddr" command
for testing the inline ECC support in the DDRSS bridge
available on K3 devices. The ECC hardware support in
K3's DDRSS and the test method differ substantially from
what we support in the K2 variant of the command. The
name of the new command is "ddrss".
The ECC test procedure follows these steps:
1) Flush and disable the data cache.
2) Shrink the protected ECC R0 range.
3) Flip a bit outside the shrunk range.
4) Restore the range to original.
5) Read the modified value (corrected).
6) Re-enable the data cache.
This which will cause the 1-bit ECC error count to increase
while the read will return the corrected value.
The K3 version of the command preserves the syntax for the
"ecc_err" argument.
Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
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Add ss_cfg memory region which maps the DDRSS configuration region
for the memory controller node.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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size when ECC is enabled
As there are few redundant functions in board/ti/*/evm.c files, pull
them to a common location of access to reuse and include the common file
to access the functions.
Call k3-ddrss driver through fixup_ddr_driver_for_ecc() to fixup the
device tree and resize the available amount of DDR, if ECC is enabled.
Otherwise, fixup the device tree using the regular
fdt_fixup_memory_banks().
Modify fixup_ddr_driver_for_ecc() to make the function agnostic to the
number of DDR controllers present.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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Add the bootph-pre-ram property to the memory node so that it can be
accessed by FDT functions at R5 stage.
The fdt_setup_mem*() functions require the memory node to be able to
initialize and set the size of the DRAM banks. For this purpose, make
sure all memory nodes are present and standardized, and add them if not.
Also make sure they have bootph-pre-ram property so that it can be
accessible at R5 SPL stage.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL
only when the config has been enabled.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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Enable ECC 1-bit error, 2-bit error, multiple 1-bit error interrupts
by setting the respective bits in the DDRSS_V2A_INT_SET_REG register.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
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Setup the ECC region's start and range using the device private data,
ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and
range of ECC regions from 32 bits to 64 bits to accommodate for
DDR greater than or equal to 4GB.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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restricted to 32 bits' issue
As R5 is a 32 bit processor, the RAM banks' base and size calculation
is restricted to 32 bits, which results in wrong values if bank's base
is greater than 32 bits or bank's size is greater than or equal to 4GB.
So, add k3_ddrss_ddr_bank_base_size_calc() to get the base address and
size of RAM's banks from the device tree memory node, and store in a
64 bit device private data which can be used for ECC reserved memory
calculation, Setting ECC range and Fixing up bank size in device tree
when ECC is enabled.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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The 1-bit inline ECC support in TI's DDRSS bridge requires
the configured memory regions to be preloaded with a pattern
before use. This is done by the k3-ddrss driver from the
R5 SPL in a 'for' loop. It takes around 10 seconds to fill
2GB of memory, for example. Memset can cut the time in half
and using DMA currently yields a similar result.
The BIST engine of DDR controller provides support for
initializing any memory region with a pattern. This
bypasses the DDRSS bridge, so the required inline ECC
data is not computed and populated in the memory. For
some values like zero, the computed ECC syndrome is also
zero and we can use these values to preload the memory
from the DDR controller, without the assistance of the
bridge.
The registers involved in the process are described in the
'DDR controller registers' topic in [1] AM62 and [2] J721E
reference manuals.
The patch replaces the 'for' loop memory fill function with
the BIST memory initialization procedure. This cuts the time
to preload the 2GB memory from 10 seconds down to 1 second.
The bist preload function uses the lpddr4 APIs in the k3-ddrss,
so this is compatible with devices with both 16-bit LPDDR4 and
32-bit LPDDR4 interfaces (e.g J721E).
[1] AM62x: https://www.ti.com/lit/pdf/spruiv7
[2] DRA829/TDA4VM: https://www.ti.com/lit/zip/spruil1
Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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Update to the latest RM (Resource Management) auto-generated YAMLs.
This accommodates CSI INT_AGG fix for Linux and RTOS both.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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Update the delay values for various speed modes supported, based on
the revised august 2021 J721E Datasheet [1].
[1] https://www.ti.com/lit/ds/symlink/tda4vm.pdf,
(SPRSP36J - FEBRUARY 2019 - REVISED AUGUST 2021)
- Table 7-77. MMC0 DLL Delay Mapping for All Timing Modes and
- Table 7-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
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For R5 SPL, we include the NAND support in the board DTS file
(k3-am642-r5-evm.dts) as there is no way to use overlay in
BootROM at the moment.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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Include the configuration required for booting from NAND.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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Expansion cards like NAND are available as a
Device Tree Overlay blob in the FIT image.
Enable CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY to R5 SPL can
apply the overlay before loading next stage.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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AM64 ES2.0 bootrom seems to enable WAIT0EDGEDETECTION interrupt.
This causes a lockup at A53 SPL when accessing NAND controller
or ELM registers.
A good option would be to softrest GPMC block at probe
but this cannot be done for AM64 as SOFTRESET bit is marked
as reserved in SYSCONFIG register.
Fix the issue by disabling all IRQs at probe.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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pr_info() depends on CONFIG_LOGLEVEL > 6. If user has
enabled CONFIG_TI_GPMC_DEBUG then we should print the
GPMC settings/timings regardless of CONFIG_LOGLEVEL.
So use printf() instead of pr_info().
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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Add config fragment to disable splashscreen related Kconfigs and also
revert back to older memory map to save space.
It is especially required to disable U-boot splash screen when using
custom device manager firmware which use RTOS based splash screen
during bootup.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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- Enable splash screen for AM62P using DSS0 instance and microtips
mf101hie OLDI panel.
- As DSS0 instance has same register space , video ports and video
planes as AM62x use the same compatible as AM62x.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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- Enable BMP and Splash screen related configs
- Enable bloblist support to pass video blob from SPL stage
to U-boot proper.
- Use same memory map for enabling splash screen as used for AM62x[1] :
-> Create space for loading bmp image file by moving the malloc area
and BSS region down to 0x80b80000 and 0x80c80000 respectively
-> Increase the SPL size limit and SPL stack size to 512 KiB and 2KiB
respectively to accommodate splash support
-> Set stack above the malloc region and report stack overflow by
setting CONFIG_SPL_SYS_REPORT_STACK_F_USAGE
- Enable simple malloc() for A53 SPL
[1]:
https://source.denx.de/u-boot/u-boot/-/blob/v2024.01/doc/board/ti/am62x_sk.rst?ref_type=tags
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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- Add splash screen related environment variables for AM62P platform.
- Set default splash location to MMC.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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Add MMC and OSPI NOR flash as storage locations for splash screen Enable
video memory reservation and splash display by calling board specific
routine for splash screen.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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Setup page table, data cache and reserve memory for SPL as a precursor
to enable splash screen for AM62P platform
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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Use device-tree node property names for parsing nodes instead of
indexing as indexing could be different between different SoCs based on
number of DSS entities available on that particular SoC.
Also correct the video layer naming in driver to match to actual one
being used in upstream DSS device-tree node [1].
This also fixes AM62x splash screen usage using the latest upstream DSS
device-tree nodes where hard-coded indexing which driver was using
before this patch was not matching the correct properties in the DT
node.
[1]: Upstream AM62x DSS node:
https://github.com/torvalds/linux/blob/v6.8-rc1/arch/arm64/boot/dts/ti/k3-am62-main.dtsi#L774
Fixes: 5f9f816bb8 ("drivers: video: tidss: TIDSS video driver support
for AM62x")
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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Don't compile ubifs splash mount command for SPL build as this command
is not supported (and also not enabled) during SPL stage.
This fixes below compilation error, when CONFIG_CMD_UBIFS is enabled in
defconfig along with splash screen enabled at SPL stage:
"aarch64-none-linux-gnu-ld.bfd: common/cli.o: in function `run_command':
u-boot-next/u-boot/common/cli.c:51: undefined reference to
`parse_string_outer'
u-boot-next/u-boot/common/cli.c:51:(.text.run_command+0x10): relocation
truncated to fit: R_AARCH64_JUMP26 against undefined symbol
`parse_string_outer' make[2]: ***
[u-boot-next/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
make[1]: *** [u-boot-next/u-boot/Makefile:2053: spl/u-boot-spl] Error 2
make[1]: Leaving directory 'u-boot-next/u-boot/out/a53' make: ***
[Makefile:177: sub-make] Error 2"
Fixes: eb9217dc03 ("common: Enable splash functions at SPL")
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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Run `make savedefconfig` to sort the defconfig.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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The number of DDR controllers to be initialised and used should depend
on the device tree with the constraint of the maximum number of
controllers the device supports. Since J784S4 has multiple (4)
controllers, instead of hardcoding the number of probes, move to
depending on the device tree UCLASS_RAM nodes present.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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The number of DDR controllers to be initialised and used should depend
on the device tree with the constraint of the maximum number of
controllers the device supports. Since J721S2 has multiple (2)
controllers, instead of hardcoding the number of probes, move to
depending on the device tree UCLASS_RAM nodes present.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
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Enable eMMC support by adding sdhci0 node.
Add cma node and led node as well.
Also add missing bootph-all flag for main_i2c0 node.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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This adds FS and raw boot mode support similar to other K3 platforms
with the default boot mode being filesystem.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Add DMSC child node sysreset-controller for uboot reset.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
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Add Main-R5F and C7x nodes to the SOC file and keep them disabled.
Rename the firmwares for MCU and WKUP R5F cores.
Enable IPC support for main, mcu and wakeup R5F and C7x cores
with memory craveouts and mailboxes.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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K3 R5 remoteproc driver requires reserved memory carveouts and mailbox
configuration to instantiate the cores successfully. Since this is a
board level resource dependency, keep the R5 subsystem disabled at SoC
level and enable them at EVM where the dependencies are met.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Enable Quality of Service blocks for Display Subsystem DSS0 and DSS1
and Main R5F core by servicing their traffic from RT queue.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Increase the SPL_MAX_SIZE to 0x6ce00 as J7AEN SRAM has larger
loadable memory space for SBL (0x7e000).
This also ensures that the SPL does not go beyond the limit while
having a single defconfig for different boot modes.
Correspondingly, increase CONFIG_SPL_BSS_START_ADDR from 0x43c4b000
to 0x43c7b000 ensuring no overlap in memory.
SRAM memory allocation map:
┌─────────────────────────────────────┐ (0x43c00000)
│ SPL (0x6ce00) │
├─────────────────────────────────────┤ (0x43c6ce00)
│ EMPTY (0x50) │
├─────────────────────────────────────┤ (0x43C6CE50)
│ STACK │
│ SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000 │
├─────────────────────────────────────┤ (0x43C71E50)
│ Global data │
│ sizeof(struct global_data) = 0x1ac |
| (+0x4) │
├─────────────────────────────────────┤ (0x43C72000)
│ HEAP │
│ CONFIG_SYS_MALLOC_F_LEN = 0x9000 │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│ SPL BSS │ (0x43c7b000)
│ CONFIG_SPL_BSS_MAX_SIZE = 0x3000 │
├─────────────────────────────────────┤ (0x43c7e000)
│ ROM Boot parameter table │
└─────────────────────────────────────┘CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
(0x43c7f290)
Fixes: b5d58d70642f ("configs: introduce configs needed for the J722S")
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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fsstub seems to be unused and should be removed.
Suggested-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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Replace all the fsstub occurences with tifsstub to avoid new
terminology and resulting confusion.
Suggested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
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The TMDS64EVM [1] ships with AM64X SR2.0 HS-FS chip
and a slightly different board name in the board information
EEPROM header. Support this board.
[1] https://www.ti.com/tool/TMDS64EVM
Gets rid of below message at boot
"Unidentified board claims AM64-EVM in eeprom header"
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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Firewalling IP has 3 permissions slots for slave and DRU firewalls. Each
permission slot can be populated with different accesses to different
privIDs.
Configuring a background firewall with an allow all permission
(0xc3ffff) in just one slot doesn't work as intendted as the other
permission slots which are essentially 0x0000 act as a block all
transaction for privID 0.
Explicitly fill all the permission registers of background firewall
regions to allow all transactions to go through including privID 0.
Foreground firewalls are intendted to block privID 0 as well so they are
not touched.
[ AM68-SK CSI Test ]
Tested-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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commit 0d72b0f2f83b788273c40ed4a64d1adf74877726 upstream.
Since upstream U-Boot uses ti_common.env instead of ti_armv7_common.env,
the implementation here differs in this aspect from the upstream commit.
The main_cpsw0_qsgmii_phyinit command is defined only for certain TI
SoCs which have the do_main_cpsw0_qsgmii_phyinit variable set.
Add a check to ensure that the main_cpsw0_qsgmii_phyinit command is run
only for such SoCs.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
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Entry for physical address 0x500000000 in memory map table for MMU
configuration is spilling over and inadvertently making DDR available at
higher address (above 4GB address space) get mapped as device memory
(nGnRnE).
Fix this by adjusting entry size. Tested on AM62A SK. Before this patch:
=> time crc32 0x881000000 0x20000000
crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca
time: 1 minutes, 14.716 seconds
After patch:
=> time crc32 0x881000000 0x20000000
crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca
time: 2.710 seconds
Acked-by: Andrew Davis <afd@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
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DDR50 speed mode is enabled for MMCSD in J784s4 but its Itap Delay
Value is not present in the device tree. Thus, add Itap Delay Value
for MMCSD Ultra High Speed DDR which is DDR50 speed mode for J784s4 SoC
according to datasheet for J784s4 [1].
[1] Refer to : section 6.10.5.17.2 MMC1/2 - SD/SDIO Interface, in
J784s4 datasheet
- https://www.ti.com/lit/ds/symlink/tda4vh-q1.pdf
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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