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Follow commit 4a5d8a5cac0b ("configs: j7*_evm_r5_defconfig: Set
NR_DRAM_BANKS to 2"). (The A72 config already sets 2)
SPL_FIT_IMAGE_POST_PROCESS is selected by default, removed
by `make savedefconfig`.
Upstream-Status: Pending
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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RC Release 09.02.00.010
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Add combined binaries for all Aquila AM69 variants.
These binaries can be used to flash the U-Boot via single
binary instead of few as it is done at the moment.
Upstream-Status: Pending
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
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Add combined binaries for all Verdin AM62 variants.
These binaries can be used to flash the U-Boot via single
binary instead of few as it is done at the moment.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240605091057.48225-1-andrejs.cainikovs@gmail.com/]
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
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Configure DDRSS using "J784S4 (Jacinto7) DDRSS Register
Configuration Tool (version 0.11.0)" targeting
"Micron MT53E2G32D4DE-046 AIT:C" memories.
Upstream-Status: Pending
This patch will be part of a series when Aquila AM69 support
will be upstreamed.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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There are 5 dedicated pins used for future hardware
configurations that cannot be autodetected.
Read these pins in the R5 and A72 SPL, and print the configuration.
Upstream-Status: Pending
This patch will be part of a series when Aquila AM69 support
will be upstreamed.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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Enable gpio driver in R5 and A72.
Upstream-Status: Pending
This patch will be part of a series when Aquila AM69 support
will be upstreamed.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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Set wkup_gpio0 status to enable and let it be available in U-Boot.
Upstream-Status: Pending
This patch will be part of a series when Aquila AM69 support
will be upstreamed.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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MCU_ADC1 pins are used as General Purpose Inputs,
so configure them accordingly.
Upstream-Status: Pending
This patch will be part of a series when Aquila AM69 support
will be upstreamed.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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Manually, since SysConfig tool do not have the relevant option,
set PHY_LP4_WDQS_OE_EXTEND to 1.
Since WDQS control mode is required on our modules LPDDR4,
this enables WDQS control mode 1.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240515080058.1530985-1-ghidoliemanuele@gmail.com/]
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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Update the autogenerated LPDDR4 configuration using the latest available
SysConfig tool.
This changes are cosmetic and are made to track the last used tool version.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240515080058.1530985-1-ghidoliemanuele@gmail.com/]
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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Use mac address for cpsw_port1
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
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Allow other boards to reuse the binman definition by using macros for
the board names
Signed-off-by: Nishanth Menon <nm@ti.com>
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Sync with kernel please
Signed-off-by: Nishanth Menon <nm@ti.com>
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This adds initial support for the Toradex Aquila AM69 module.
Upstream-Status: Pending
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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msmc and ddrss probes do not depends on specific target boards but on
K3_J721E_DDRSS configuration.
So enable probe using this configuration.
Upstream-Status: Inappropriate
Upstream already probes these drivers using K3_J721E_DDRSS configuration.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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Set CONFIG_NR_DRAM_BANKS to 2 as we have two banks described in the
memory/ node for lower and higher addressible DDR regions.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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Call fixup_memory_node() in A72 SPL stage so that the memory changes
made by fixup_ddr_driver_for_ecc() by R5 SPL is propagated to the A72
U-Boot stage as well.
Fixes: 410888e38c7e ("board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled")
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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Correct fixup_ddr_driver_for_ecc() for multi-DDR cases,
uclass_next_device_err returns 0 when the next memorycontroller instance
is successfully found and not !0.
Also call dram_init_banksize() after every call to
fixup_ddr_driver_for_ecc() is made so that gd->bd is populated
correctly.
Fixes: 410888e38c7e ("board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled")
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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The memory node is already defined in k3-am69-sk.dts, remove the
duplicate node from k3-am69-r5-sk.dts which includes the former.
Fixes: afb074d9e26c ("arm: dts: k3-am69-sk: Add r5 specific dt support")
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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At HS400 mode the ITAPDLY value is that from High Speed mode
which is incorrect and may cause boot failures.
The ITAPDLY for HS400 speed mode should be the same as ITAPDLY
as HS200 timing after tuning is executed. Add the functionality
to save ITAPDLY from HS200 tuning and save as HS400 ITAPDLY.
Upstream-Status: Backport [f13a830e6e4ad884069e25c7cd2dc333b474da98]
Fixes: c964447ea3d6 ("mmc: am654_sdhci: Add support for input tap delay")
Signed-off-by: Judith Mendez <jm@ti.com>
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According to the device datasheet [0], ENDLL=1 for
DDR52 mode, so call am654_sdhci_setup_dll() and write
itapdly after since we do not carry out tuning.
[0] https://www.ti.com/lit/ds/symlink/am62p.pdf
Upstream-Status: Backport [a124e31a97cd2963181d3a8a00678998bf9958a2]
Fixes: c964447ea3d6 ("mmc: am654_sdhci: Add support for input tap delay")
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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Set itap_del_ena if ITAPDLY is found in DT or if the tuning
algorithm was executed and found the optimal ITAPDLY. Add the
functionality to save ITAPDLYENA that can be referenced later
by storing the bit in array itap_del_ena[].
Upstream-Status: Backport [056af04a39aef6d9777a8d4fc29917b4494db4a5]
Signed-off-by: Judith Mendez <jm@ti.com>
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U-Boot is failing to boot class U1 UHS SD cards due to incorrect
OTAP and ITAP delay select values. Update OTAP and ITAP delay select
values from DT.
Upstream-Status: Backport [5048b5c61afddddb0a6ff2e6bffdd9dd028e399b]
Fixes: c7d106b4eb3 ("mmc: am654_sdhci: Update output tap delay writes")
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
Signed-off-by: Judith Mendez <jm@ti.com>
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
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Currently the sdhci_am654 driver only supports one tuning
algorithm which should be used only when DLL is enabled. The
ITAPDLY is selected from the largest passing window and the
buffer is viewed as a circular buffer.
The new tuning algorithm should be used when the delay chain
is enabled; the ITAPDLY is selected from the largest passing
window and the buffer is not viewed as a circular buffer.
This implementation is based off of the following paper: [1].
Also add support for multiple failing windows.
[1] https://www.ti.com/lit/an/spract9/spract9.pdf
Upstream-Status: Backport [6b8dd9ca6e06bc9ebd3d55cbbe094d4947e197bf]
Fixes: a759abf569d4 ("mmc: am654_sdhci: Add support for software tuning")
Signed-off-by: Judith Mendez <jm@ti.com>
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
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Substitute failing calls to fdt_fixup_msmc_ram function
by calling fdt_fixup_msmc_ram_k3 function which was implemented in
commit [1].
At functional level nothing changes.
[1] b6e669d7a393 ("arm: k3: Fix ft_system_setup so it can be enabled on any SoC")
Upstream-Status: Inappropriate
Commit [1] is already upstreamed and the new function is already used
when new boards were added.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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Since commit [1] spl_enable_dcache is no more available and,
at the same time, by enabling instruction cache, boot time is reduced.
[1] 536d0d5eef24 ("arm: k3: Enable instruction cache for main domain SPL")
Upstream-Status: Inappropriate
Commit [1] is already upstreamed. am62p5 and j784s4 were introduced
afterwards and they are using the new function.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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The maximum frequency of the A53 CPU on the AM62 depends on the speed
grade of the SoC. However, this value is hardcoded in the DT for all
AM62 variants, potentially causing specifications to be exceeded. Moreover,
setting a common lower frequency for all variants increases boot time.
To prevent these issues, modify the DT at runtime from the R5 core to
adjust the A53 CPU frequency based on its speed grade.
Upstream-Status: Backport [5ed961094d456d03c481d2bf751f6eeb06c1bada]
Suggested-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
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AM62 SoC has multiple speed grades. Add function to return max A53 CPU
frequency based on grade. Fastest grade's max frequency also depends on
PMIC voltage, to simplify implementation use the smaller value.
Upstream-Status: Backport [ba26524cad98aa70913afb7a2436949ac14c3b41]
Suggested-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
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During the boot, the EFI loader maps the memory from ram_top to ram_end
as EFI_BOOT_SERVICES_DATA. When LMB does boot_fdt_add_mem_rsv_regions()
to OPTEE, TFA, R5, and M4F DMA/memory "no-map" for the kernel it produces
the following error message:
ERROR: reserving fdt memory region failed (addr=9cb00000 size=100000 flags=4)
ERROR: reserving fdt memory region failed (addr=9cc00000 size=e00000 flags=4)
ERROR: reserving fdt memory region failed (addr=9da00000 size=100000 flags=4)
ERROR: reserving fdt memory region failed (addr=9db00000 size=c00000 flags=4)
ERROR: reserving fdt memory region failed (addr=9e780000 size=80000 flags=4)
ERROR: reserving fdt memory region failed (addr=9e800000 size=1800000 flags=4)
To avoid this, don't flag with EFI_BOOT_SERVICES_DATA the memory from
ram_top to ram_end by the EFI loader.
Upstream-Status: Backport [3206b77c844c7f2d85e9154982f6ef9d72adaab6]
Related-to: ELB-5326
Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
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Call a k3-ddrss fixup function to fixup device tree and resize the
available amount of DDR if ECC is enabled.
A second fixup is required from A53 SPL to fixup device tree passed to
A53 U-Boot.
Fixes: 8712298323f0 ("board: ti: am6*x: Fix up incorrect RAM size for AM62A and AM62P")
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
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RC Release 09.02.00.009
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RC Release 09.02.00.008
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The maximum DDR RAM size stuffed on the Verdin AM62 is 2GB,
correct the memory node accordingly.
Commit 3610dbfc37e3 ("ram: k3-ddrss: Set SDRAM_IDX using device private
data, ddr_ram_size") now evaluates the device tree property and limits
DDR access to the specified size. Thus set the maximum stuffed size in
the dts corresponding to what is set in CFG_SYS_SDRAM_SIZE.
If CFG_SYS_SDRAM_SIZE is bigger than what is set in the device tree
SPLs and U-Boot freeze when probing for the DDR size.
Upstream-Status: Pending
The R5 dtb memory node is only needed in downstream TI U-Boot.
All mainline AM62 boards do not set the node, when said commit gets
upstreamed we can follow the pattern TI adds the node to the dtb.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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The maximum DDR RAM size stuffed on the Verdin AM62 is 2GB,
correct the memory node accordingly.
Commit 3610dbfc37e3 ("ram: k3-ddrss: Set SDRAM_IDX using device private
data, ddr_ram_size") now evaluates the device tree property and limits
DDR access to the specified size. Thus set the maximum stuffed size in
the dts corresponding to what is set in CFG_SYS_SDRAM_SIZE.
If CFG_SYS_SDRAM_SIZE is bigger than what is set in the device tree
SPLs and U-Boot freeze when probing for the DDR size.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240320142937.2028707-1-max.oss.09@gmail.com/]
Submitted to the linux kernel. Upstream U-Boot will get it through the
regular sync with Linux.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Replace all the fsstub occurences with tifsstub to avoid new
terminology and resulting confusion.
This follows commit 57f1e97afad ("arm: dts: k3-*: s/fsstub/tifsstub/")
Upstream-Status: Pending
Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com>
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Move the DM entry in tispl.bin FIT image from default fetching an
external blob entry to fetching using ti-dm entry type. This way, the
DM entry will be populated by the TI_DM pathname if provided. Else it
will resort to the ti-dm.bin file.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Upstream-Status: Backport [3ef977e085767df31e42262f15837a66558052db]
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Move the DM entry in tispl.bin FIT image from default fetching an
external blob entry to fetching using ti-dm entry type. This way, the
DM entry will be populated by the TI_DM pathname if provided. Else it
will resort to the ti-dm.bin file.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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J7200 has SR1.0 and SR2.0 having three variants of each GP, HS-FS and
HS-SE. Current build does not generate HS-SE SR1.0 and HS-FS SR1.0 so
add support for them.
Reported-by: Suman Anna <s-anna@ti.com>
Reported-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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J721E has SR1.1 and SR2.0 having three variants of each GP, HS-FS and
HS-SE. Current build does not generate HS-SE SR2.0 and HS-FS SR1.1 so
add support for them.
Reported-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
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- Enable BMP and Splash screen related configs
- Enable bloblist support to pass video blob from SPL stage
to U-boot proper.
- Use same memory map for enabling splash screen as used for
AM62x[1] :
-> Create space for loading bmp image file by moving the malloc
area
and BSS region down to 0x80b80000 and 0x80c80000 respectively
-> Increase the SPL size limit and SPL stack size to 512 KiB and
2KiB
respectively to accommodate splash support
-> Set stack above the malloc region and report stack overflow by
setting CONFIG_SPL_SYS_REPORT_STACK_F_USAGE
- Enable simple malloc() for A53 SPL
- Enable simplefb and fb reservation for A53 SPL
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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Run `make savedefconfig` to sort the defconfig.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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Enable microtips mf101hie OLDI panel and link it with DSS ports to
enable splash screen on AM62x LP SK.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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The NAND flash utility functions under CONFIG_CMD_NAND should not be
compiled at SPL stage as the underlying functions are under separate
Kconfigs viz. CONFIG_ENV_IS_IN_NAND and hence are not supported at
SPL stage right now for splash screen.
Long term, the NAND flash utility functions and their dependencies need
to be tied with splash screen specific Kconfigs too as splash logo
file can be present in NAND storage before bootup.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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Update size of tiboot3.bin is exceeding allocated
area of 512KB, 1MB assigned to tiboot3.bin. Default offset for
tispl.bin will not work for OSPI NAND. Add config for tispl.bin
offset.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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commit 2764be4345 ("remoteproc: uclass: Add methods to load
firmware to rproc and boot rproc") selects FS_LOADER in Kconfig
and this breaks R5 build for some defconfigs across multiple platforms.
Enabling CONFIG_SPL_FS_LOADER does not help for all cases.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Tested-by: MD Danish Anwar <danishanwar@ti.com>
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Enable simple-framebuffer support for AM62x and AM62p platforms which
have early splash screen enabled. This updates the simple-framebuffer
node in Linux device-tree on the fly with framebuffer address and
meta-data and also reserves framebuffer region in device-tree.
Also disable the simple-framebuffer support in am62p's prune
splashscreen config fragment as it is not required without splashscreen
support.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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Run `make savedefconfig` to sort the A53 defconfig files for AM62x and
AM62p.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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Update simple-framebuffer device-tree node by enumerating framebuffer
related information in existing simple-framebuffer node in Linux
device-tree file and enabling it.
While at it, ignore error return value for framebuffer related DT node
updates as a non-zero return value for ft_board_setup is treated as a fatal
error causing board reset.
In case there is no simple-framebuffer stub detected in Linux kernel
device-tree and video is still active, then update the device-tree to
reserve the framebuffer region for the active splash screen.
This helps preserve the splash screen till the display server takes over
after OS is booted.
In case the simplefb node update or the framebuffer reservation fails we
treat it as a non-fatal error and avoid returning error to parent
function as the non-zero return value of ft_board_setup is treated as
fatal error which leads to board reset
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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Create separate helper for just reserving framebuffer region without
creating or enabling simple-framebuffer node.
This is useful for scenarios where user want to preserve the bootloader
splash screen till OS boots up and display server gets started without
displaying anything else in between and thus not requiring
simple-framebuffer.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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