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MAIN domain ESM support was already added for J721E to configure main
domain watchdog interrupts to generate ESM pin events. Move the main_esm
node to be in sync with kernel dts. Also add register mapping for ESM in
J721E.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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Since the MDIO driver is not DM enabled and the CPSW driver is
responsible for configuring the pins corresponding to MDIO as well,
add the MDIO pinctrl in the cpsw3g device-tree node as a HACK in
the k3-am642-sk-u-boot.dtsi file.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
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Enable i2c0 to support EEPROM reads at U-Boot stage.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
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In the "legacy" way, partitions are listed directly under the flash
node. In the "new" way, there is a partitions node under the flash node,
and the partitions are listed under that node. Allow parsing both styles
of partitions for finding the PHY pattern location.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Acked-by: Vaishnav Achath <vaishnav.a@ti.com>
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CONFIG_IS_ENABLED(CADENCE_QSPI_PHY) would check for
CONFIG_SPL_CADENCE_QSPI_PHY when building SPL. But only
CONFIG_CADENCE_QSPI_PHY is defined and used, so calibration ends up not
happening for SPL. Use IS_ENABLED() instead which does not have this
behaviour.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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A very frequent operation is the Read Status Register command that is
executed repeatedly after doing an erase or page program. On the Cypress
S28HS512T flash this command expects 4 address bytes and so it does not
go via the STIG route. The command reads 2 bytes from the flash. Setting
up DMA for it is more hassle than it is worth. For small reads like
this, the speed gain, if any, will not be worth the extra overhead.
So do not use DMA for reads smaller than 16 bytes. This should cover
polling operations like SR polling.
It also fixes an issue on J721E and J7200 with the Cypress S28HS512T
flash where DMA would eventually freeze when writing or erasing because
of the constant bombardment of small, frequent reads.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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The controller can only run at 1/8 ref clock speed without PHY. With
PHY, it can run at the ref clock speed. So, to enable higher speed
operations, perform the PHY tuning algorithm and determine the RX, TX,
and read delay values for optimal performance. The details of the tuning
algorithm can be found at [0].
To allow this tuning to happen, pre-determined data must be programmed
to the flash at some location. This location is then advertised via a
nvmem cell. Without this data being available, the tuning would fail.
The tuning algorithm is a multi-variable search. The RX and TX delays
need to be found, along with the read delay that would work across a
temperature range. To do that, first the upper and lower RX values at
which the tuning pattern is readable are looked for. This is called the
passing region. The search is performed with Tx = 16 incrementing the
read delay with each iteration. If the two RX values have the same read
delay, the same search is performed with TX = 48.
Once the RX boundaries are found, the TX boundaries are searched for in
a similar fashion with RX set to 1/4 of the RX window (the difference
between the highest and lowest values). And similarly, if the TX
boundaries have the same read delay, the same search is performed with
RX set to 3/4 of the RX window.
There is a region around the boundary of the two passing regions. It is
called the failing region. PHY reads will not work in this region so the
PHY should be tuned as far from it as possible to allow for temperature
variations. This region is found using binary search where the window is
progressively narrowed down until it arrives at the final boundary's
lower and upper limits.
Once PHY is successfully tuned, mark it as usable to allow eligible
operations to run at high speeds. PHY can only be used with DAC mode
reads, and only in chunks of 16 bytes. For all other operations, PHY
mode should be turned off.
[0] https://www.ti.com/lit/pdf/spract2/
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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Check if a read is eligible for PHY and if yes, enable PHY and DQS.
Since PHY reads only work at an address that is 16-byte aligned and of
size that is a multiple of 16 bytes, read the starting and ending
unaligned portions without PHY, and only enable PHY for the middle part.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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The PHY tuning pattern should be located at the start of the partition
named "ospi.phypattern". Find it in the devicetree, if it exists.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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Once the flash is initialized tell the controller it can run calibration
procedures if needed. This can be useful when calibration is needed to
run at higher clock speeds.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
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A template of the read op will be needed in a upcoming commit. So,
refactor the code to create a read op in spi_nor_read_data() to a
separate function that returns the template of the op. The caller can
then fill in the details like address, data length, and the data buffer.
Update spi_nor_read_data() to use this template.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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Some controllers like the Cadence OSPI controller need to perform a
calibration sequence to operate at high clock speeds. This calibration
should happen after the flash is fully initialized otherwise the
calibration might happen in a different SPI mode from the one the flash
is finally set to. Add a hook that can be used to tell the controller
when the flash is ready for calibration. Whether calibration is needed
depends on the controller.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
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If the device supports PHY tuning, we don't need to run
spi_calibration(). The PHY tuning algorithm will take care of that.
We pull the read delay for non-PHY reads in that case from the device
tree since those two are not always the same.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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As "dtb" seems to be more common than "dtbs", use that as our standard.
Signed-off-by: Andrew Davis <afd@ti.com>
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The 'gsub' setexpr sub command is using when creating the FIT image
configuration string on K3 devices. Enable this for K3.
Signed-off-by: Andrew Davis <afd@ti.com>
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This is used when building the FIT image configuration string. Enable
it for all FIT using TI platforms.
Signed-off-by: Andrew Davis <afd@ti.com>
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Since get_fdt_mmc is common, factor it out into mmc.env and remove
it from each platform env file. Use it in mmcloados but keep loadfdt
defined in case it is still used by some external uEnv.txt script.
Signed-off-by: Andrew Davis <afd@ti.com>
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ESM MCU masks must be set to 0h so that PMIC can handle errors
that require attention for example SYS_SAFETY_ERRn. The required bits
must be cleared: ESM_MCU_RST_MASK, ESM_MCU_FAIL_MASK, ESM_MCU_PIN_MASK.
If PMIC expected to handle errors, make sure EVM is configured to
connect SOC_SAFETY_ERRz (Main) to the PMIC.
Note that even though the User Guide for TPS65941 for J721E mentions
that these bits are reset to 0h; it is not reflected once board boots to
kernel, possibly due to NVM configurations. Eithercase, it is best to
account for this from R5 SPL side as well.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Tested-by: Udit Kumar <u-kumar1@ti.com>
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This reverts commit 44c5f2798e218c6cc1f722e401266e726a0214bb.
Reverting this patch as some boot regressions on am64xx hs platform is
observed.
Further investigation and proper fix shall be followed up on top.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
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This reverts commit 9af8e6313abe564660e65050d843499b51014997.
Reverting this patch as some boot regressions on am64xx hs platform is
observed.
Further investigation and proper fix shall be followed up on top.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
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Add the configs needed for USB DFU support
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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To ensure we continue to have enough space in our SRAM, split the device
firmware upgrade protocol bootmode into a separate configuration
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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Add support for USB controllers and enable the USB to boot via DFU.
The USB node changes are in sync with linux kernel.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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Now that DFU args are available in k3_dfu.env, remove the DFU
args from am62ax_evm.h and include them in the am62ax.env file
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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Set the USB PHY core voltage to 0.85V
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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As per [1], dfu_alt_info is mentioned to be as semicolon separated
string of information on each alternate and the parsing logic in
the dfu.c is based on this.
Typically, the dfu_alt_info_* is defined in .h files as preprocessor
macros with 'alt' info separated by semicolon.
But when dfu_alt_info_* is added in the environment files(.env)
the script at "scripts/env2string.awk" converts a newline to space.
Thus adding a space character after semicolon. This results in
incorrect parsing in dfu.c which is based on the information that
'alt' info are only semicolon separated.
One option is to add dfu_alt_info_* variable in .env in single line.
But there is possiblity for it to exceed the line length limit.
So update the parsing logic to remove leading space characters
before adding to the dfu list.
[1]: https://u-boot.readthedocs.io/en/latest/usage/dfu.html
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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When the device port is in a low power state [U3/L2/Not Connected],
accesses to usb device registers may take a long time. This could lead to
potential core hang when the controller registers are accessed after the
port is disabled by setting DEVDS field. Setting the fast register access
bit ensures that the PHY clock is keeping up in active state.
Therefore, set fast access bit to ensure the accesses to device registers
are quick even in low power states.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
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K3 GP devices allows booting the secure binaries on them by bypassing
the x509 header on them.
ATF and OPTEE firewalling required the rproc_load to be called before
authentication. This change caused the failure for GP devices that
strips off the headers. The boot vector had been set before the headers
were stripped off causing the runtime stripping to fail and stripping
becoming in-effective.
Separate out the secure binary check on GP/HS devices so that the
boot_vector could be stripped before calling rproc_load. This allows
keeping the authentication later when the cluster is on along with
allowing the stripping of the binaries in case of gp devices.
Fixes: 07e8de1a2cd2 ("arm: mach-k3: common: re-locate authentication for atf/optee")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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commit 1e00e9be62e54e87673ad03b77fb5ebe4ac270b1 upstream.
For setting up the master firewalls present in the K3 SoCs, the arm64
clusters need to be powered on.
Re-locates the code for atf/optee authentication.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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commit 1e666512fb00d3aed6e32db2c22579e87d977d76 upstream
Update the DDR settings to those generated using 0.6 version of
Jacinto 7 DDRSS Register Configuration tool.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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commit b99d710fe090b1af7cadd4ab09dbf205169e3090 upstream
Update the DDR settings to those generated using 0.9.1 version of
Jacinto 7 DDRSS Register Configuration tool.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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Add PCIe device tree node (both RC and EP) for the single PCIe
instance present in j721s2.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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The board uses lane 1 of SERDES for USB. Set the mux
accordingly.
The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that upto 2 protocols can be used at a time. The SERDES is
wired for PCIe, eDP and USB super-speed. It has been
chosen to use PCIe and eDP as default. So restrict
USB0 to high-speed mode.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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Configure first lane to PCIe, the second lane to USB and the last two lanes
to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is
connected to PCIe.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, eDP and USB.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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Add support for single instance of USB 3.0 controller in J721S2 SoC.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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Add support for j721s2-wiz-10g device to use clock-names interface
instead of explicitly defining clock nodes within device tree node.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
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During refactor this seemed to have been missed.
Fixes: 3e85631db7c5 ("include: environment: ti: Use .env for environment variables")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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Enable DMA and CPSW options we now support for the am62ax SoC family
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Enable CPSW3G MAC Port 1 at U-Boot stage.
Since the MDIO driver is not DM enabled, add the MDIO pinctrl in the
cpsw3g device-tree node as a HACK.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
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Add CPSW device-tree nodes to support Ethernet at U-Boot stage.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
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In preparation for enabling ethernet for the am62ax family of SoCs,
introduce the initial DMA channel settings for the am62ax
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
[bb@ti.com: expanded on commit message]
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
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J721E and J7200 have same file j721e_init.c which had the firewall
configs for J721E being applied on J7200 causing the warnings. Split the
firewalls for both the boards to remove those warnings.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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commit 77df85c48537faade5648b314baeff2259787ee8 upstream
Currently, name_fdt is not set for J7200, fix this so right DTB is
picked during boot.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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This reverts commit 07e8de1a2cd2f4e341ebc53fc8bdacc3f9954f22.
Unfortunately this commit breaks the jump to ATF for the GP variant of
the am62x family of SoCs.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
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On K3 HS-SE devices all the firewalls are locked by default
until sysfw comes up. Rom configures some of the firewall for its usage
along with the SRAM for R5 but the PSRAM region is still locked.
The K3 MCU Scratchpad for j784s4 was set to a PSRAM region triggering the
firewall exception before sysfw came up. The exception started happening
after adding multi dtb support that accesses the scratchpad for reading
EEPROM contents.
Old map:
┌─────────────────────────────────────┐ 0x41c00000
│ SPL │
├─────────────────────────────────────┤ 0x41c61f20 (approx)
│ STACK │
├─────────────────────────────────────┤ 0x41c65f20
│ Global data │
│ sizeof(struct global_data) = 0xd8 │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c66000
│ HEAP │
│ CONFIG_SYS_MALLOC_F_LEN = 0x10000 │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│ SPL BSS │ (0x41c76000)
│ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │
├─────────────────────────────────────┤ (0x41c80000)
│ DM DATA │
├─────────────────────────────────────┤ (0x41c84130) (approx)
│ EMPTY │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
(0x41cffbfc)
New map:
┌─────────────────────────────────────┐ 0x41c00000
│ SPL │
├─────────────────────────────────────┤ 0x41c61f20 (approx)
│ STACK │
├─────────────────────────────────────┤ 0x41c65f20
│ Global data │
│ sizeof(struct global_data) = 0xd8 │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c66000
│ HEAP │
│ CONFIG_SYS_MALLOC_F_LEN = 0x10000 │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│ SPL BSS │ (0x41c76000)
│ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │
├─────────────────────────────────────┤ (0x41c80000)
│ DM DATA │
├─────────────────────────────────────┤ (0x41c84130) (approx)
│ EMPTY │
├─────────────────────────────────────┤ SYS_K3_MCU_SCRATCHPAD_BASE
│ SCRATCHPAD │ (0x41cff9fc)
│ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
(0x41cffbfc)
Fixes: a7341dea7087 ("configs: j784s4_evm_r5: Enable support for building multiple dtbs into FIT")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
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Some firewalls enabled by ROM are still left on. So some
address space is inaccessible to the bootloader. For example,
in OSPI boot mode we get an exception and the system hangs.
Therefore, disable all the firewalls left on by the ROM.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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( hopefully this will be covered by andrew's series so wouldn't be
required during merge )
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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include the common files and remove the redundant variables. run_fit
wasn't working so the refactor for the env was required.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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