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2014-10-11power: Add AMS AS3722 PMIC supportThierry Reding
The AS3722 provides a number of DC/DC converters and LDOs as well as 8 GPIOs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-10-11i2c: tegra: Implement i2c_get_bus_num_fdt()Thierry Reding
This is useful to retrieve the U-Boot bus number of an I2C controller given a device tree node. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-10-11i2c: Add high-level APIThierry Reding
This API operates on I2C adapters or I2C clients (a new type of object that refers to a particular slave connected to an adapter). This is useful to avoid having to call i2c_set_bus_num() whenever a device is being accessed. Drivers for I2C devices are supposed to embed a struct i2c_client within a driver-specific data structure and call i2c_client_init() on it, passing in a pointer to the parent I2C adapter and the slave address of the device. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-10-11i2c: Refactor adapter initializationThierry Reding
A subsequent patch will introduce a new API to access I2C adapters directly rather than going through the bus number and constantly looking up the same adapter. In order to share the adapter initialization code, move it into a separate function and make i2c_init_bus() use it to avoid code duplication. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-10-11i2c: Initialize the correct busThierry Reding
i2c_bus_init() takes a bus number but relies on the currently selected bus to determine which adapter to initialize. Make the function use the bus passed in as parameter rather than the currently selected bus. While at it, keep a pointer to the specified bus to avoid having to look it up repeatedly. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-10-11Add pr_fmt() macroThierry Reding
This macro can be overridden in source files (before including common.h) and can be used to specify a prefix for debug and error messages. An example of how to use this is shown below: #define pr_fmt(fmt) "foo: " fmt #include <common.h> ... debug("bar"); The resulting message will read: foo: bar Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-10-11pci: Honour pci_skip_dev()Thierry Reding
When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-10-11pci: Abort early if bus does not existThierry Reding
When listing the devices on a PCI bus, the current code will blindly try to access all devices. Internally this causes pci_bus_to_hose() to be repeatedly called and output an error message every time. Prevent this by calling pci_bus_to_hose() once and abort early if no bus was found. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-10-11fdt: Add a subnodes iterator macroThierry Reding
The fdt_for_each_subnode() iterator macro provided by this patch can be used to iterate over a device tree node's subnodes. At each iteration a loop variable will be set to the next subnode. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-10-11fdt: Add a function to return PCI BDF tripletThierry Reding
The fdtdec_pci_get_bdf() function returns the bus, device, function triplet of a PCI device by parsing the "reg" property according to the PCI device tree binding. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-10-11fdt: Add resource parsing functionsThierry Reding
Add the fdt_get_resource() and fdt_get_named_resource() functions which can be used to parse resources (memory regions) from an FDT. A helper to compute the size of a region is also provided. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-10-11fdt: Add functions to retrieve stringsThierry Reding
Given a device tree node, a property name and an index, the new function fdt_get_string_index() will return in an output argument a pointer to the index'th string in the property's value. The fdt_get_string() is a shortcut for the above with the index being 0. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-10-11fdt: Add a function to get the index of a stringThierry Reding
Given a device tree node and a property name, the new fdt_find_string() function will look up a given string in the string list contained in the property's value and return its index. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-10-11fdt: Add a function to count stringsThierry Reding
Given a device tree node and a property name, the fdt_count_strings() function counts the number of strings found in the property value. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-10-11vsprintf: Add modifier for phys_addr_tThierry Reding
Provide a new modifier to vsprintf() to print phys_addr_t variables to avoid having to cast or #ifdef when printing them out. The %pa modifier is used for this purpose, so phys_addr_t variables need to be passed by reference, like so: phys_addr_t start = 0; printf("start: %pa\n", &start); Depending on the size of phys_addr_t this will print out the address with 8 or 16 hexadecimal digits following a 0x prefix. Signed-off-by: Thierry Reding <treding@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
2014-10-11tegra: apalis_t30: master revampMarcel Ziswiler
Update Apalis T30 as per the following commits c369139234c03b1494394d12cd27009f47aa6606 tegra: dts: Add serial port details 461be2f96e4b87e5065208c6659a47dd0ad9e9f8 kconfig: remove redundant "string" type in arch and board Kconfigs f1ef2b62339526df3b921bcfefd174ce76d4c624 kconfig: move CONFIG_DEFAULT_DEVICE_TREE to kconfig Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2014-10-11tegra: dts: colibri_t30 add serial port detailsMarcel Ziswiler
Add missing chosen stdout-path device tree node. This got missed by commit c369139234c03b1494394d12cd27009f47aa6606 tegra: dts: Add serial port details Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2014-10-11tegra: colibri_t30: clean-up spurious new lineMarcel Ziswiler
Clean-up a spurious new line which got introduced resp. left behind by commit f1ef2b62339526df3b921bcfefd174ce76d4c624 kconfig: move CONFIG_DEFAULT_DEVICE_TREE to kconfig Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2014-10-10mmc: Tegra: Fix timeout issue seen on certain eMMC partsMarcel Ziswiler
During rigorous testing of our latest update infrastructure I came across quite consistent timeouts on certain eMMC parts (e.g. Hynix H26M21001ECR) when writing big (e.g. in excess of 400 MB) file system images: MMC write: dev # 0, block # 40960, count 944128 ... mmc_send_cmd_bounced: MMC Timeout Interrupt status 0x00000001 Interrupt status enable 0xdfff003b Interrupt signal enable 0xdfff0002 Present status 0x01870106 mmc write failed Comparing the various data sheets I came across the following timeout specification: Secure Erase/TRIM Timeout=300ms*2*10=6000ms Unfortunately empirical testing still failed albeit much more rarely. Increasing the timeout to 8000ms made it finally disappear entirely. This patch allows us writing various eMMC parts without seeing any further issues. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2014-10-10ARM: tegra: Use mem size from MC in combination with get_ram_size()Marcel Ziswiler
On popular request this now completes the Warren's work started for TK1: aeb3fcb35956461077804720b8a252d50758d7e0 ARM: tegra: Use mem size from MC rather than ODMDATA In addition to the move of using the Tegra memory controller (MC) register rather than ODMDATA for T20, T30 and T114 as well it further uses the generic get_ram_size() function (see "common/memsize.c") <supposed to be used in each and every U-Boot port>TM. Added benefit is that it should <catch 99% of hardware related (i. e. reliably reproducible) memory errors> as well. Thoroughly tested on the various Toradex line of Tegra modules available which unfortunately does not include T114 and T124 (yet at least) plus on the Jetson TK1. Based-on-work-by: Stephen Warren <swarren@nvidia.com> Based-on-work-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2014-10-10tegra: colibri_t30: asix usb ethernet reset regressionMarcel Ziswiler
Fix ASIX USB to Ethernet reset which due to the new driver model Tegra GPIO driver changes now requires a label string to be provided otherwise the reservation and subsequent direction/value calls will fail. This fixes a regression introduced by commit: 2fccd2d96badcdf6165658a99771a4c475586279 tegra: Convert tegra GPIO driver to use driver model Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2014-10-10tegra: gpio: fix null label regressionMarcel Ziswiler
Fix Tegra GPIO driver to not crash resp. misbehave upon requesting GPIOs with an empty aka NULL label. As the driver uses exclusively the label to check for reservation status actually supplying one is mandatory! This fixes a regression introduced by commit: 2fccd2d96badcdf6165658a99771a4c475586279 tegra: Convert tegra GPIO driver to use driver model Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2014-10-09arm: tegra: initial support for apalis t30Marcel Ziswiler
This patch adds board support for the Toradex Apalis T30 a computer on module which can be used on different carrier boards. For the sake of ease of use we do not distinguish between different carrier boards for now as the base module features are deemed sufficient enough for regular booting. The following functionality is working so far: - eMMC boot and environment storage - Gigabit Ethernet (once Thierry's PCIe as well as my E1000 resp. i210 fixes hit mainline) - MMC/SD cards (both 8-bit as well as 4-bit slot) - USB client/host (dual role port as client e.g. for DFU/UMS, other two ports as host) Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit 90a565acf3a18c61170ec0e0b2046c98cb7ecc85)
2014-10-06Prepare v2014.10-rc3v2014.10-rc3Tom Rini
Signed-off-by: Tom Rini <trini@ti.com>
2014-10-06Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
2014-10-06Merge branch 'topic/arm/socfpga-20141006' of git://git.denx.de/u-boot-socfpgaTom Rini
Fix a trivial conflict in dw_mmc.c after talking with Marek. Conflicts: drivers/mmc/dw_mmc.c Signed-off-by: Tom Rini <trini@ti.com>
2014-10-06usb: gadget: fastboot: terminate commands with NULLEric Nelson
Without NULL termination, various commands will read past the end of input. In particular, this was noticed with error() calls in cb_getvar and simple_strtoul() in cb_download. Since the download callback happens elsewhere, the 4k buffer should always be sufficient to handle command arguments. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2014-10-06usb: musb-new: core: set MUSB_POWER_HSENAB in MUSB_POWER for host modeDaniel Mack
This bit allows the MUSB controller to negotiate for high-speed mode when the device is reset by the hub. If unset, Babble errors occur with high-speed mass storage devices right after the first packet. This condition is not caught by the interrupt handles in U-Boot, so no recovery is done, and the USB communication is stuck. To fix this, set the bit unconditionally, not only for CONFIG_USB_GADGET_DUALSPEED but also for host-only modes. Signed-off-by: Daniel Mack <zonque@gmail.com>
2014-10-06arm: socfpga: Use CMD_FS_GENERICMarek Vasut
Enable and use the CONFIG_CMD_FS_GENERIC to avoid hard-coding the filesystem type into the environment. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: Split SoCFPGA configurationPavel Machek
Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: Clean up SoCFPGA configurationMarek Vasut
Reorganize and cleanup the configuration file for SoCFPGA. There is no functional change after this cleanup. This was necessary, since the file was a wild mess and it was impossible to make sense of it's content, let alone change something without breaking some other thing. This patch puts the contents on par with regular U-Boot standards. Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER and CONFIG_USE_IRQ, which is undefined by default. Finally, do logical reordering of the defines in the file so it's much more readable. The reordering was also necessary for the splitting as the initial one was messy. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: Add command to control HPS-FPGA bridgesMarek Vasut
Add command to enable and disable the bridges between HPS and FPGA. This patch does have a checkpatch issue with the assembler portion, checkpatch correctly complains that there should be no whitespace before quoted newline. I do not agree that fixing this specific checkpatch issue will improve the readability, thus this one is not addressed. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de>
2014-10-06arm: socfpga: Move cache_enable to CPU codeMarek Vasut
Move icache_enable() and dcache_enable() function calls from board code into the CPU code and into the enable_caches() function. This is how the cache enabling code was designed to work. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: Enable SDMMC boot for SOCFPGA U-BootChin Liang See
Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit. Enable the bootz command as zImage is used instead uImage. Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: Enable DWMMC for SOCFPGAChin Liang See
Enable the DesignWare MMC controller driver support for SOCFPGA Cyclone5 dev kit Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: nic301: Add NIC-301 configuration codePavel Machek
Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA . The code sets the access permissions for the CPU to the AMBA slaves such that the CPU can access them in both secure and non-secure mode. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: pl310: Map SDRAM to 0x0Marek Vasut
Configure the PL310 address filter to make sure DRAM is mapped to 0x0. This code also configures the "remap" register of NIC-301 and sets the required 'mpuzero' bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: nic301: Add NIC-301 GPV register fileMarek Vasut
Add register definition for the NIC-301 used on SoCFPGA. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: scu: Add SCU register fileMarek Vasut
Add the Snoop Control Unit register definition file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: cache: Enable PL310 L2 cacheMarek Vasut
Enable the PL310 L2 cache controller support for the SoCFPGA. With the cache related issues resolved, this is safe to be done. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: cache: Enable D-CacheMarek Vasut
The code is now fixed to the point where we can safely enable the L1 data cache. Enable the D-Cache and set it as write-alloc. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: cache: Define cacheline sizeMarek Vasut
The Cortex-A9 has 32-byte long L1 cachelines. Define this value. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: sysmgr: Add FPGA bits into system managerMarek Vasut
Add missing system manager bits from Altera U-Boot to make the code comparable. These are the bits which depend on the FPGA manager. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: reset: Add function to reset FPGA bridgesMarek Vasut
Add function to enable and disable FPGA bridges. This code is used by the FPGA manager to disable the bridges before programming the FPGA and will later be also used by the initialization code for the chip to put the chip into well defined state during startup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: fpga: Add SoCFPGA FPGA programming interfacePavel Machek
Add code necessary to program the FPGA part of SoCFPGA from U-Boot with an RBF blob. This patch also integrates the code into the FPGA driver framework in U-Boot so it can be used via the 'fpga' command. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move the not-CPU specific stuff into drivers/fpga/ and base this on the cleaned up altera FPGA support.
2014-10-06arm: socfpga: board: Align checkboard() outputMarek Vasut
Cosmetic change to the checkboard() function output. Align the output with the rest of initial output produced by U-Boot. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: board: Correctly set ATAG positionPavel Machek
The bi_boot_params must point to offset 0x100 in DRAM. Make it so. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: misc: Align print_cpuinfo() outputPavel Machek
Cosmetic change to the print_cpuinfo() function output. Align the output with the rest of initial output produced by U-Boot. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: misc: Add SD controller initPavel Machek
Add CPU function to register and initialize the dw_mmc SD controller. This allows us to use the HPS SDMMC block. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: misc: Add proper ethernet initializationPavel Machek
Add function to initialize the EMAC blocks upon board startup. The preprocessor guards against building on SoCFPGA-VT and against SPL build are not needed as those are handled implicitly via both SPL framework and the socfpga_cyclone5.h config file, which will not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
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