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2023-05-17arm: dts: k3-j721s2-*-common-proc-board: Add USB supportAswath Govindraju
The board uses lane 1 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that upto 2 protocols can be used at a time. The SERDES is wired for PCIe, eDP and USB super-speed. It has been chosen to use PCIe and eDP as default. So restrict USB0 to high-speed mode. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
2023-05-17arm: dts: k3-j721s2-common-proc-board: Enable SERDES0Aswath Govindraju
Configure first lane to PCIe, the second lane to USB and the last two lanes to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
2023-05-17arm: dts: k3-j721s2-main: Add SERDES and WIZ device tree nodeAswath Govindraju
Add dt node for the single instance of WIZ (SERDES wrapper) and SERDES module shared by PCIe, eDP and USB. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
2023-05-17arm: dts: k3-j721s2-main: Add support for USBAswath Govindraju
Add support for single instance of USB 3.0 controller in J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
2023-05-17phy: ti: phy-j721e-wiz: Add j721s2-wiz-10g module supportRavi Gunasekaran
Add support for j721s2-wiz-10g device to use clock-names interface instead of explicitly defining clock nodes within device tree node. Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org>
2023-05-15environment: ti: rproc: fix remoteproc environment variablesManorit Chawdhry
During refactor this seemed to have been missed. Fixes: 3e85631db7c5 ("include: environment: ti: Use .env for environment variables") Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-12configs: enable net features for am62axBryan Brattlof
Enable DMA and CPSW options we now support for the am62ax SoC family Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-05-12HACK: arm: dts: add DMA and CPSW nodes for ubootBryan Brattlof
Enable CPSW3G MAC Port 1 at U-Boot stage. Since the MDIO driver is not DM enabled, add the MDIO pinctrl in the cpsw3g device-tree node as a HACK. Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-05-12arm: dts: sync am62ax CPSW and related nodes with linux v6.3-rc6Bryan Brattlof
Add CPSW device-tree nodes to support Ethernet at U-Boot stage. Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-05-12dma: ti: k3-udma: Introduce DMA support for the am62axVignesh Raghavendra
In preparation for enabling ethernet for the am62ax family of SoCs, introduce the initial DMA channel settings for the am62ax Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> [bb@ti.com: expanded on commit message] Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-05-12arm: mach-k3: j7200: Fix firewall warnings at boot timeManorit Chawdhry
J721E and J7200 have same file j721e_init.c which had the firewall configs for J721E being applied on J7200 causing the warnings. Split the firewalls for both the boards to remove those warnings. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-11include: configs: j721e_evm: Fix name_fdt for J7200Neha Malcom Francis
commit 77df85c48537faade5648b314baeff2259787ee8 upstream Currently, name_fdt is not set for J7200, fix this so right DTB is picked during boot. Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-05-10Revert "arm: mach-k3: common: re-locate authentication for atf/optee"Bryan Brattlof
This reverts commit 07e8de1a2cd2f4e341ebc53fc8bdacc3f9954f22. Unfortunately this commit breaks the jump to ATF for the GP variant of the am62x family of SoCs. Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
2023-05-09Kconfig: j784s4: Change K3_MCU_SCRATCHPAD_BASE to non firewalled regionManorit Chawdhry
On K3 HS-SE devices all the firewalls are locked by default until sysfw comes up. Rom configures some of the firewall for its usage along with the SRAM for R5 but the PSRAM region is still locked. The K3 MCU Scratchpad for j784s4 was set to a PSRAM region triggering the firewall exception before sysfw came up. The exception started happening after adding multi dtb support that accesses the scratchpad for reading EEPROM contents. Old map: ┌─────────────────────────────────────┐ 0x41c00000 │ SPL │ ├─────────────────────────────────────┤ 0x41c61f20 (approx) │ STACK │ ├─────────────────────────────────────┤ 0x41c65f20 │ Global data │ │ sizeof(struct global_data) = 0xd8 │ ├─────────────────────────────────────┤ gd->malloc_base = 0x41c66000 │ HEAP │ │ CONFIG_SYS_MALLOC_F_LEN = 0x10000 │ ├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR │ SPL BSS │ (0x41c76000) │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ ├─────────────────────────────────────┤ (0x41c80000) │ DM DATA │ ├─────────────────────────────────────┤ (0x41c84130) (approx) │ EMPTY │ └─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX (0x41cffbfc) New map: ┌─────────────────────────────────────┐ 0x41c00000 │ SPL │ ├─────────────────────────────────────┤ 0x41c61f20 (approx) │ STACK │ ├─────────────────────────────────────┤ 0x41c65f20 │ Global data │ │ sizeof(struct global_data) = 0xd8 │ ├─────────────────────────────────────┤ gd->malloc_base = 0x41c66000 │ HEAP │ │ CONFIG_SYS_MALLOC_F_LEN = 0x10000 │ ├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR │ SPL BSS │ (0x41c76000) │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ ├─────────────────────────────────────┤ (0x41c80000) │ DM DATA │ ├─────────────────────────────────────┤ (0x41c84130) (approx) │ EMPTY │ ├─────────────────────────────────────┤ SYS_K3_MCU_SCRATCHPAD_BASE │ SCRATCHPAD │ (0x41cff9fc) │ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │ └─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX (0x41cffbfc) Fixes: a7341dea7087 ("configs: j784s4_evm_r5: Enable support for building multiple dtbs into FIT") Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
2023-05-09arch: mach-k3: j784s4_init: Disable the firewallsManorit Chawdhry
Some firewalls enabled by ROM are still left on. So some address space is inaccessible to the bootloader. For example, in OSPI boot mode we get an exception and the system hangs. Therefore, disable all the firewalls left on by the ROM. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-09environment: ti: add prefix to j784s4 device treeManorit Chawdhry
( hopefully this will be covered by andrew's series so wouldn't be required during merge ) Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-09board: ti: j784s4: env: remove redundant env variablesManorit Chawdhry
include the common files and remove the redundant variables. run_fit wasn't working so the refactor for the env was required. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-09configs: enable configs for J784S4 High Security EVMManorit Chawdhry
Add J784S4 High Security EVM defconfig. These configs are same as for the non-secure part, except for: CONFIG_TI_SECURE_DEVICE option set to 'y' CONFIG_FIT_SIGNATURE option set to 'y' CONFIG_BOOTCOMMAND option is changed to use fitImage '# CONFIG_CMD_SETEXPR is not set' is removed to allow fit booting Non-HS devices will continue to boot due to runtime device type detection. If TI_SECURE_DEV_PKG is not set the build will emit warnings, for non-HS devices these can be ignored. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-09Kconfig: change default for FIT_IMAGE_POST_PROCESSManorit Chawdhry
Now that the default flow is moving towards FIT_SIGNATURE, make the default of FIT_IMAGE_POST_PROCESS depend on it. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-09environment: ti: Find DTB files in dtbs directoriesAndrew Davis
Fedora/Redhat and Arch are somewhat standardized on their dtb directory structure. Our TI Arago distro will now follow that standard. Add the directory dtbs/ to the DTB search path. Signed-off-by: Andrew Davis <afd@ti.com>
2023-05-09environment: ti: Prefix ARM64 DTB names with directoryAndrew Davis
In Linux the ARM64 DTSs are stored in vendor directories to help organize the files and prevent naming collisions. The deployed DTBs will mirror this and so the vendor prefix should be added to the variable used to locate these files. Suggested-by: Ryan Eatmon <reatmon@ti.com> Signed-off-by: Andrew Davis <afd@ti.com>
2023-05-09environment: ti: Add get_fit_config command to get FIT config stringAndrew Davis
When OE is packaging a dtb file into the FIT image it names the node based on the dtb filename. Node names can't have "/" so it is turned into "_". We select our FIT config using the "fdtfile" env var so we don't duplicate the board_name to fdt logic. Result is fdtfile needs mangled when used to select a config node from OE made FIT image. Do this here. Signed-off-by: Andrew Davis <afd@ti.com>
2023-05-09arm: mach-k3: common: re-locate authentication for atf/opteeManorit Chawdhry
[ upstream commit 1e00e9be62e54e87673ad03b77fb5ebe4ac270b1 ] For setting up the master firewalls present in the K3 SoCs, the arm64 clusters need to be powered on. Re-locates the code for atf/optee authentication. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-09remoteproc: ti_k3_arm64: Change the startup of arm64 coreManorit Chawdhry
[ upstream commit 65f3afc6b92a4c1cb4fa0dc47d810db9a4dad5e9 ] Configuring master firewalls require the power of the cluster to be enabled before configuring them, change the load of rproc to configure the gtc clocks and start the cluster along with configuring the boot vector. The start of rproc will only start the core. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-09arm: dts: k3-am625-r5-sk: add a53 cluster powerManorit Chawdhry
[ upstream commit 53f02be32e1fd387a37ef9a10a55cbeed425f599 ] adds a53 cluster to control from the rproc driver Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-09arm: dts: k3-am62a7-r5-sk: add a53 cluster power domain nodeManorit Chawdhry
[ upstream commit 9a36735b0f62efc892d3b0eb2c020487c72359f9 ] adds a53 cluster to control from the rproc driver Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-09arm: dts: k3-am642-r5: add a53 cluster power domain nodeManorit Chawdhry
[ upstream commit 3922cf6295c772e703d8c1f1044f2ead22ef02c7 ] adds a53 cluster to control from the rproc driver Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-09arm: dts: k3-am642-r5-sk: add a53 cluster power domain nodeManorit Chawdhry
[ upstream commit 7fe7920c5e8316e112f66cf2213e3e9df6e35fc2 ] adds a53 cluster to control from the rproc driver Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-09arm: dts: k3-j7200-r5: add a72 cluster power domain nodeManorit Chawdhry
[ upstream commit dcdcbde2bbbc770573c0a8da19a937e0d8ee6d80 ] adds a72 cluster to control from the rproc driver Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-09arm: dts: k3-j721e-r5: add a72 cluster power domain nodeManorit Chawdhry
[ upstream commit bdbd6688534cd998edc7dc057b67a70c5a5eeccb ] adds a72 cluster to control from the rproc driver Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-09arm: dts: k3-j721e-r5-sk: add a72 cluster power domain nodeManorit Chawdhry
[ upstream commit ab3df39ffa981043302bac6300a6cebbbf550a5b ] adds a72 cluster to control from the rproc driver Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-09arm: dts: k3-j721s2-r5: add a72 cluster power domain nodeManorit Chawdhry
[ upstream commit d363013e87a94daf375fb60723f4d8e08b592fc3 ] adds a72 cluster to control from the rproc driver Lore Link: https://lore.kernel.org/u-boot/20230411-upstream-firewalling-v2-0-b6c705d50099@ti.com/ Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-09soc: soc_ti_k3: fix revision array bounds checksRasmus Villemoes
commit 45981a9a3759eae8375c85927fb213e4cc14353d upstream If rev is equal to the array size, we'll access the array one-past-the-end. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-05-09soc: soc_ti_k3: Use hardware.h to remove definition duplicationAndrew Davis
commit 677a1e23da1b97d91a0f69f5a956fbdb11d41524 upstream The K3 JTAG and SoC ID information is already stored in the K3 arch hardware file, include that and use its definitions here. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> [bb@ti.com: rebased to ti-v2023.04] Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-05-09arm: mach-k3: add j784s4 to hardware.hBryan Brattlof
The jtag id information has moved into the hardware.h file upstream. Move the j784s4's id information to the correct location to align with what we're doing upstream. Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-05-09arm: mach-k3: Move J721e SoC detection out of common sectionAndrew Davis
commit ca0973741d62e7c67270b723a6c25c8e855fb87c upstream This belongs in the J721e specific file as it is the only place this is used. Any board level users should use the SOC driver. While here, move the J721e and J7200 SoC IDs out of sys_proto.h and into hardware.h. Use a macro borrowed from Rockchip and add the rest of the SoC IDs for completeness and later use. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-05-08configs: am62ax_evm_a53_defconfig: Enable YMODEM support at A53 SPLVignesh Raghavendra
This is required for UART boot flow where u-boot.img needs to be downloaded via YMODEM. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-05arch: mach-k3: j721s2_init: Disable the firewallsJayesh Choudhary
commit 2e43ba78052825c62e3078e308d681da44ccdc8f upstream. Some firewalls enabled by ROM are still left on. So some address space is inaccessible to the bootloader. For example, in OSPI boot mode we get an exception and the system hangs. Therefore, disable all the firewalls left on by the ROM. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-04spi: spi-mem: perform odd len check only while writing dataDhruva Gole
commit db58dc5438ec674cad438a606edc155d06914adc upstream. in spi_mem_dtr_supports_op we have a check for allowing only even number of bytes to be r/w. Odd bytes writing can be a concern while writing data to a flash for example because 8 DTR mode doesn't support it. However, reading ODD Bytes even though may not be physically possible we can still allow for it because it will not have serious implications on any critical registers being overwritten since they are just reads. Cc: Vaishnav Achath <vaishnav.a@ti.com> Cc: Pratyush Yadav <pratyush@kernel.org> Cc: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Nikhil M Jain <n-jain1@ti.com> Signed-off-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-05-04spi: spi-mem: s/dummy/data buswidth check in dtr_supports_op()Dhruva Gole
commit 963b5da339a2ac8ad1451c9b84e746a2e26fd0d4 upstream. This should have been op->data.buswidth instead as we check for octal bus width for the data related ops Also add explanation for why there is checks for 8D even data bytes Cc: Pratyush Yadav <pratyush@kernel.org> Reviewed-by: Pratyush Yadav <ptyadav@amazon.de> Tested-by: Nikhil M Jain <n-jain1@ti.com> Signed-off-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-05-04spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completionDhruva Gole
commit 08b3098eadc7f826c3e6fb9d184cf6d82f5028fe upstream. If one leaves the CQSPI_REG_CMDCTRL in an unclean state this may cause issues in future command reads. This issue came to light when some flash reads in STIG mode were coming back dirty. Co-developed-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Dhruva Gole <d-gole@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2023-05-04spi: cadence-quadspi: Use STIG mode for all ops with small payloadApurva Nandan
commit 8077d296adff235e13c1478f92ef42c08e17ec33 upstream. OSPI controller supports all types of op variants in STIG mode, only limitation being that the data payload should be less than 8 bytes when not using memory banks. STIG mode is more stable for operations that send small data payload and is more efficient than using DMA for few bytes of memory accesses. It overcomes the limitation of minimum 4 bytes read from flash into RAM seen in DAC mode. Use STIG mode for all read and write operations that require data input/output of less than 8 bytes from the flash, and thereby support all four phases, cmd/address/dummy/data, through OSPI STIG. Also, remove the reorder address chunk in apb_command_write since we now setup ADDR BIT field that does the same job in a cleaner way. Signed-off-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Dhruva Gole <d-gole@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2023-05-04spi: cadence-quadspi: Fix check condition for DTR opsApurva Nandan
commit 44e2de0480a8a5a5780b6b200935a96b961b94e7 upstream. buswidth and dtr fields in spi_mem_op are only valid when the corresponding spi_mem_op phase has a non-zero length. For example, SPI NAND core doesn't set buswidth when using SPI_MEM_OP_NO_ADDR phase. Fix the dtr checks in set_protocol() to ignore empty spi_mem_op phases, as checking for dtr field in empty phase will result in false negatives. Signed-off-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-05-04arm: mach-k3: am62a7: Enable QoS for DSSAradhya Bhatia
commit 28e5e95bf8e75efc8ed49e2dc3c260ab998d59fb upstream Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is done by setting the DSS DMA orderID to 8. The C7x and VPAC have been overwhelming the DSS's access to the DDR (when it was accessing via the Non Real-Time (NRT) Queue), primarily because their functional frequencies, and hence DDR accesses, were significantly higher than that of DSS. This led the display to flicker when certain edgeAI models were being run. With the DSS traffic serviced from the RT queue, the flickering issue has been found to be mitigated. The am62a qos files are auto generated from the k3 resource partitioning tool. Section-3.1.12, "QoS Programming Guide", in the AM62A TRM[1], provides more information about the QoS, and section-14.1, "System Interconnect Registers", provides the register descriptions. [1] AM62A Tech Ref Manual: https://www.ti.com/lit/pdf/spruj16 Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
2023-04-28arch: arm: mach-k3: Delete tifs node in DT fixupUdit Kumar
This patch deletes tifs DT node as part of fixup. TISCI API reported msmc_size, does not include 64KB reserved size for tifs aka MSMC comms memory. As part of fixup, original code uses TISCI API reported msmc_size as size for sram DT node. tifs node is similar to l3-cache, which should hold address above msms_size, and should be deleted before passing control to OS. Documentation https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/core.html?highlight=msmc#tisci-msg-query-msmc Signed-off-by: Udit Kumar <u-kumar1@ti.com>
2023-04-27arm: mach-k3: am625_init: Add Erratum WA for RTC startupNishanth Menon
Add erratum i2327 work around for initialization for RTC interrupt where interrupt is stuck for ever at startup. Unfortunately, this workaround needs to be applied under 1 second of boot. Signed-off-by: Nishanth Menon <nm@ti.com> [bb@ti.com: rebased from 2021.01] Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-04-21Kconfig: j721s2: Change K3_MCU_SCRATCHPAD_BASE to non firewalled regionManorit Chawdhry
On K3 HS-SE devices all the firewalls are locked by default until sysfw comes up. Rom configures some of the firewall for its usage along with the SRAM for R5 but the PSRAM region is still locked. The K3 MCU Scratchpad for j721s2 was set to a PSRAM region triggering the firewall exception before sysfw came up. The exception started happening after adding multi dtb support that accesses the scratchpad for reading EEPROM contents. Old map: ┌─────────────────────────────────────┐ 0x41c00000 │ SPL │ ├─────────────────────────────────────┤ 0x41c61f20 (approx) │ STACK │ ├─────────────────────────────────────┤ 0x41c65f20 │ Global data │ │ sizeof(struct global_data) = 0xd8 │ ├─────────────────────────────────────┤ gd->malloc_base = 0x41c66000 │ HEAP │ │ CONFIG_SYS_MALLOC_F_LEN = 0x10000 │ ├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR │ SPL BSS │ (0x41c76000) │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ ├─────────────────────────────────────┤ (0x41c80000) │ DM DATA │ ├─────────────────────────────────────┤ (0x41c84130) (approx) │ EMPTY │ └─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX (0x41cffbfc) New map: ┌─────────────────────────────────────┐ 0x41c00000 │ SPL │ ├─────────────────────────────────────┤ 0x41c61f20 (approx) │ STACK │ ├─────────────────────────────────────┤ 0x41c65f20 │ Global data │ │ sizeof(struct global_data) = 0xd8 │ ├─────────────────────────────────────┤ gd->malloc_base = 0x41c66000 │ HEAP │ │ CONFIG_SYS_MALLOC_F_LEN = 0x10000 │ ├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR │ SPL BSS │ (0x41c76000) │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ ├─────────────────────────────────────┤ (0x41c80000) │ DM DATA │ ├─────────────────────────────────────┤ (0x41c84130) (approx) │ EMPTY │ ├─────────────────────────────────────┤ SYS_K3_MCU_SCRATCHPAD_BASE │ SCRATCHPAD │ (0x41cff9fc) │ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │ └─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX (0x41cffbfc) Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-21arm: mach-k3: common: Default to non fitImage boot on HS-FSVignesh Raghavendra
Allow non fitImage bootflow on Field Securable (HS-FS) devices in addition to GP, force fitImage boot only on Security enforced (HS-SE) devices where signed images are necessary to maintain chain of trust. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
2023-04-18HACK: arm: dts: k3-j784s4: Fix MCU CPSW2G at U-BootSiddharth Vadapalli
Enable MCU CPSW2G at U-Boot stage. Since the MDIO driver is not DM enabled and the CPSW driver is responsible for configuring the pins corresponding to MDIO as well, add the MDIO pinctrl in the mcu_cpsw device-tree node as a HACK in the k3-j784s4-evm-u-boot.dtsi file. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-04-18arm: dts: k3-j784s4-evm: Enable MCU CPSW2GSiddharth Vadapalli
Add device tree nodes to enable MCU CPSW with J784S4 EVM. Linux kernel device tree patch for the same is at: https://git.kernel.org/ti/linux/c/6cd4b7cfbcca Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
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