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Introduce the basic functions and definitions needed to properly
initialize Ti's am62p family of SoCs
[bb@ti.com: rebased on TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Currently for the K3 generation of SoCs there are more SoCs that utilize
the split firmware approach than the combined DMSC firmware. Invert the
logic to avoid adding more and more SoCs to this list.
[bb@ti.com: rebased on TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
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The am62px family of SoCs uses the same DDR controller as found on the
am62ax family. Enable this option when building for the am62px family
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Include the clock and lpsc tree files needed for the wkup spl to
initialize the proper PLLs and power domains to boot the SoC.
[bb@ti.com: rebased to TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Include the part number for TI's am62px family of SoCs so we can
properly identify it during boot
[bb@ti.com: rebased to TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
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PLL calibration needs to be enabled when operating in non fractional
mode. Add the sequence to do a fast calibration when using PLL
in this mode.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Tested-by: Neha Malcom Francis <n-francis@ti.com>
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EEPROM detection logic in ti_i2c_eeprom_get() involves reading the total
size followed by reading 1-byte size with an offset 1. This commit fixes
the header matching issue in commit 9f393a2d7af8 ("board: ti: common:
board_detect: Fix EEPROM read quirk for 2-byte").
In the previous commit, the value with one offset is being read into
offset_test, but the pointer used to match was still ep. After reading
with an offset 1, the second byte of the header is compared with the 1-byte
data read from EEPROM. This is taken care by comparing proper first byte
value from the header.
Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
Fixes: 9f393a2d7af8 (board: ti: common: board_detect: Fix EEPROM read quirk for 2-byte)
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Fix below warning by including appropriate header file
drivers/remoteproc/ti_k3_m4_rproc.c: In function 'k3_m4_load':
drivers/remoteproc/ti_k3_m4_rproc.c:151:9: warning: implicit declaration of function 'ti_secure_image_post_process' [-Wimplicit-function-declaration]
151 | ti_secure_image_post_process(&image_addr, &size);
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Fixes: cf4727c2f602 ("remoteproc: k3-m4: Introduce K3 remote proc driver for M4 subsystem")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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BOOT_DEVICE_SPINAND and BOOT_DEVICE_UART have same index of 0x7, this
leads to attempting SPINAND boot during UART boot. Fix this by
allocating unique value to BOOT_DEVICE_SPINAND. While at that move it
out of unused list as SPINAND boot is very much supported on AM62x SoCs.
Fixes: 8c7827f522b0 ("arm: mack-k3: am62x: Add SPI NAND as a boot device")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Set remote proc FW binaries for u-boot loading of remote cores.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
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Add support for R5F remote proc driver.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
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AM64x SoCs have two R5F clusters in the main power domain.
Extend support for R5F remote proc driver on AM64x with compatible
strings.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
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Similar to other K3 platforms, drop specifying source of env to avoid
picking up stale env. This enables proper FitImage boot on HS-SE
devices which used to fail due to stale env from older releases.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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For systems with 512MB DDR, reduce the top 64MB for firmwares instead of
current 256MB. This provides more useable memory for U-Boot during image
load.
Fixes: 64c0d9e010da ("board: ti: am62x: Avoid overwriting reserve mem for AM62 SIP")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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spi-tx-bus-width is set as 8 in SoM dtsi, but set to 1 in R5 common
proc board dts, which seems wrong. SPI NOR requires a 8D reset before
probe starts using 0x66+0x99 op, but that will fail if the flash tx
width is set as 1.
Set spi-tx-bus-width to 8 in R5 common proc board dtsi also.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>
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spi_nor_read_sfdp() calls nor->read() to read the SFDP data.
The MTD and SPI subsystem expects the tx and rx buf used for
transfers should point to a dma-safe memory.
However, two out of the three calls of spi_nor_read_sfdp() were given
pointers to stack allocated memory as buf argument, hence not in a
dma-safe area.
The third and last call of spi_nor_read_sfdp() was already given a
kmalloc'ed buffer argument, hence dma-safe.
So this patch fixes this issue by introducing a
spi_nor_read_sfdp_dma_unsafe() function which simply wraps the existing
spi_nor_read_sfdp() function and uses some kmalloc'ed memory as a bounce
buffer.
This patch is ported from upstream Linux mtd spi-nor fix commit
bfa4133795e5a0badd402dd3f58b13b3cec64a4b ("mtd: spi-nor: fix DMA unsafe
buffer issue in spi_nor_read_sfdp()")
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Fixes: 0c6f187cdb18b52bcf6d3964771cf3a36b758568 ("mtd: spi: spi-nor-core: Add SFDP support")
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
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Enable ESM & PMIC ESM configs
Signed-off-by: Keerthy <j-keerthy@ti.com>
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Enable ESM & PMIC ESM configs
Signed-off-by: Keerthy <j-keerthy@ti.com>
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Currently J721E defines only the main_esm in DTS. Add node for mcu_esm
as well.
According to J721E TRM (12.11.2.2 ESM Environment) [1], we see that the
interrupt line from ESMi (main_esm) is routed to MCU_ESM (mcu_esm). This
is MCU_ESM0_LVL_IN_95 with interrupt ID 95. Configure mcu_esm
accordingly so that errors from main_esm are routed to mcu_esm and
handled.
[1] https://www.ti.com/lit/zip/spruil1
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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Support bootcore_opts field in x509 template. The bootcore_opts argument
had been defined earlier but not utilised into the final certificate.
Fixes: d43c636437d1 ("binman: openssl: x509: ti_secure_rom: Add support for bootcore_opts")
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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Set boot core-opts to enable split mode for MCU R5 cluster by default.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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Previously, MCU R5F runs DM on core0, and core1 sits waiting in WFI mode.
The support to shut the core1 and use it for loading other firmware,
while DM runs on core0, has been added. Enable split-mode on the MCU R5F.
Use the newly introduced compatible for MCU R5F cores.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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Link the default firmware in the environment variable for MCU R5 core1.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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On J7 family of devices, the resource management (RM) and power
management (PM) functions run on the MCU domain R5F cores. As a result
it cannot control its own power and reset. That has to be done by the
TIFS firmware.
In the normal case, MCU R5F should be not shut down since it runs the RM
and PM functions. But when the R5F subsystem is booted in split mode,
core 0 will run these functionality, and second core can be shut down or
used for running other firmwares.
During boot, ROM can bring up the boot R5F cores in either lockstep or
split mode based on X509 certificate flags. If booted in lockstep mode,
all R5F cores will run first the R5 SPL, and then once A72 comes up will
run the Device Manager (DM) firmware. But if booted in split mode, core
0 will run DM firmware and second core sits in WFI. Shut it down so that
other firmwares can later be loaded on them. As it is part of cluster that
runs DM, its shut down is handled by TIFS and uses a different TISCI msg
for shut down which sets LPSC R5 register.
Add support for shutting down MCU R5F core1 for Jacinto platforms.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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As AM57x uses overlays for display and camera interfaces, add support to
load DT overlay files to MMC boot.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
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TI AM57x boards use a custom (though family common to TI boards) mechanism
for booting Linux. Add support to enable custom MMC boot as a default
option along with the distroboot approach.
Also, add supporting mmc boot environment variables which shall be used for
custom MMC boot
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
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This commit adds a general flow to explain the usage of firewalls and
the chain of trust in K3 devices.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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The following commits adds the configuration of firewalls required to
protect ATF and OP-TEE memory region from non-secure reads and
writes using master and slave firewalls present in our K3 SOCs.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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The following commits adds the configuration of firewalls required to
protect ATF and OP-TEE memory region from non-secure reads and
writes using master and slave firewalls present in our K3 SOCs.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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The following commits adds the configuration of firewalls required to
protect ATF and OP-TEE memory region from non-secure reads and
writes using master and slave firewalls present in our K3 SOCs.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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For readability during configuring firewalls, adding k3-security.h file
and including it in k3-binman.dtsi to be accessible across K3 SoCs
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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Add test for TI firewalling node in ti-secure.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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We can now firewall entities while loading them through our secure
entity TIFS, the required information should be present in the
certificate that is being parsed by TIFS.
The following commit adds the support to enable the certificates to be
generated if the firewall configurations are present in the binman dtsi
nodes.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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Drop the buck node as the AVS is still not enabled and is causing
issues with the xSPI boot.
Signed-off-by: Keerthy <j-keerthy@ti.com>
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commit 4a6105e7830e9e945a6dc556a43ffaf26f0156e5 upstream.
Add test case for an address range which is coalescing with one of
range and overlapping with next range
Cc: Simon Glass <sjg@google.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
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commit edb5824be17f018c76d094372a4573750be7c631 upstream.
In case of new memory range to be added is coalesced
with any already added non last lmb region.
And there is possibility that, then region in which new memory
range added is not adjacent to next region. But have some
sections are overlapping.
So along with adjacency check with next lmb region,
check for overlap should be done.
In case overlap is found, adjust and merge these two lmb
region into one.
Reported-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
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Initialize the 3 instances of SOC ESM & PMIC ESM.
This is needed for watchdog functionality.
Signed-off-by: Keerthy <j-keerthy@ti.com>
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Currently only the Main domain ESM is being initialized. For watchdog
reset we need the MCU ESM as well. Enbaling the same.
Signed-off-by: Keerthy <j-keerthy@ti.com>
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Initialize the ESM & PMIC ESM
Signed-off-by: Keerth <j-keerthy@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
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PMIC ESM is part of tps6594x PMIC and connected to WKUP_I2C instance.
Signed-off-by: Keerthy <j-keerthy@ti.com>
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Patch adds the ESM instances for j721s2. It has 3 instances.
One in the main domain and two in the mcu-wakeup domian.
Signed-off-by: Keerthy <j-keerthy@ti.com>
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Patch adds the ESM instance for MCU domian of j7200.
Signed-off-by: Keerthy <j-keerthy@ti.com>
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Patch adds the ESM instances for j784s4. It has 3 instances.
One in the main domain and two in the mcu-wakeup domian.
Signed-off-by: Keerthy <j-keerthy@ti.com>
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The PMIC ESM node is responsible for triggering the PMIC reset.
Signed-off-by: Keerthy <j-keerthy@ti.com>
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commit c97ed47b42364f6b8b387aac331ab111480a8075 upstream.
The following checks are more reasonable as the previous logs were a bit
misleading as we could still get the logs that the authetication is
being skipped but still authenticate. Move the debug prints and checks
to proper locations.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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commit 7ebbce535c774806b3db0bedd2ba3cfb95c07658 upstream.
After the refactor with conf- nodes in fitImage, overlaystring wasn't
didn't handle the new conf- nodes in FIT Booting. Fix get_overlaystring
to handle conf- nodes.
Fixes: 837833a724b7 ("environment: ti: Add get_fit_config command to get FIT config string")
Reported-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
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commit 44dab785809ac1ef808eacf141abbc75ac89ddba upstream.
Fix regression occurred during refactoring for the mentioned commit.
Fixes: bd6a24759374 ("arm: mach-k3: security: separate out validating binary logic")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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commit bd6a247593742596a83d6e36bebb45cb78a4017e upstream.
K3 GP devices allows booting the secure binaries on them by bypassing
the x509 header on them.
ATF and OPTEE firewalling required the rproc_load to be called before
authentication. This change caused the failure for GP devices that
strips off the headers. The boot vector had been set before the headers
were stripped off causing the runtime stripping to fail and stripping
becoming in-effective.
Separate out the secure binary check on GP/HS devices so that the
boot_vector could be stripped before calling rproc_load. This allows
keeping the authentication later when the cluster is on along with
allowing the stripping of the binaries in case of gp devices.
Fixes: 1e00e9be62e5 ("arm: mach-k3: common: re-locate authentication for atf/optee")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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commit 1e00e9be62e54e87673ad03b77fb5ebe4ac270b1 upstream.
For setting up the master firewalls present in the K3 SoCs, the arm64
clusters need to be powered on.
Re-locates the code for atf/optee authentication.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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As per data sheet of J784S4[0], name of board is
J784S4X instead of J784S4.
Fixes: 80f078723786 ("board: ti: j784s4: Add support for board detection by EEPROM read")
[0]: https://www.ti.com/lit/pdf/spruj62<F2>
Section 3.8 Identification EEPROM, Table 3-6. Board ID Information
B_NAME Field
Cc: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
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