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fsstub seems to be unused and should be removed.
Suggested-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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Replace all the fsstub occurences with tifsstub to avoid new
terminology and resulting confusion.
Suggested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
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The TMDS64EVM [1] ships with AM64X SR2.0 HS-FS chip
and a slightly different board name in the board information
EEPROM header. Support this board.
[1] https://www.ti.com/tool/TMDS64EVM
Gets rid of below message at boot
"Unidentified board claims AM64-EVM in eeprom header"
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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Firewalling IP has 3 permissions slots for slave and DRU firewalls. Each
permission slot can be populated with different accesses to different
privIDs.
Configuring a background firewall with an allow all permission
(0xc3ffff) in just one slot doesn't work as intendted as the other
permission slots which are essentially 0x0000 act as a block all
transaction for privID 0.
Explicitly fill all the permission registers of background firewall
regions to allow all transactions to go through including privID 0.
Foreground firewalls are intendted to block privID 0 as well so they are
not touched.
[ AM68-SK CSI Test ]
Tested-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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commit 0d72b0f2f83b788273c40ed4a64d1adf74877726 upstream.
Since upstream U-Boot uses ti_common.env instead of ti_armv7_common.env,
the implementation here differs in this aspect from the upstream commit.
The main_cpsw0_qsgmii_phyinit command is defined only for certain TI
SoCs which have the do_main_cpsw0_qsgmii_phyinit variable set.
Add a check to ensure that the main_cpsw0_qsgmii_phyinit command is run
only for such SoCs.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
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Entry for physical address 0x500000000 in memory map table for MMU
configuration is spilling over and inadvertently making DDR available at
higher address (above 4GB address space) get mapped as device memory
(nGnRnE).
Fix this by adjusting entry size. Tested on AM62A SK. Before this patch:
=> time crc32 0x881000000 0x20000000
crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca
time: 1 minutes, 14.716 seconds
After patch:
=> time crc32 0x881000000 0x20000000
crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca
time: 2.710 seconds
Acked-by: Andrew Davis <afd@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
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DDR50 speed mode is enabled for MMCSD in J784s4 but its Itap Delay
Value is not present in the device tree. Thus, add Itap Delay Value
for MMCSD Ultra High Speed DDR which is DDR50 speed mode for J784s4 SoC
according to datasheet for J784s4 [1].
[1] Refer to : section 6.10.5.17.2 MMC1/2 - SD/SDIO Interface, in
J784s4 datasheet
- https://www.ti.com/lit/ds/symlink/tda4vh-q1.pdf
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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DDR50 speed mode is enabled for MMCSD in J721s2 but its Itap Delay
Value is not present in the device tree. Thus, add Itap Delay Value
for MMCSD Ultra High Speed DDR which is DDR50 speed mode for J721s2 SoC
according to datasheet for J721s2 [1].
[1] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in
J721s2 datasheet
- https://www.ti.com/lit/ds/symlink/tda4vl-q1.pdf
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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DDR52 speed mode is enabled for eMMC in J7200 but its Itap Delay Value
is not present in the device tree. Thus, add Itap Delay Value for eMMC
High Speed DDR which is DDR52 speed mode for J7200 SoC according to
datasheet for J7200 [1].
[1] Refer to : section 7.9.5.16.1 MMCSD0 - eMMC Interface, in
J7200 datasheet
- https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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We need the I2C GPIO drivers to detect expansion cards.
Gets rid of below error message at R5 SPL on AM64-EVM
"Failed to lookup gpio gpio@38_0: -22"
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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SK-AM64B boot is broken. The main_i2c0 node is
left disabled in r5-evm.dts preventing
proper board detection. Explicitly enable
the main_i2c0 node in r5-evm.dts.
Fixes boot and below error message:
"Reading on-board EEPROM at 0x51 failed -19"
Fixes: cc471479d3850: ("arm: dts: k3-am642: main_i2c0 cleanup")
Reported-by: Andreas Dannenberg <dannenberg@ti.com>
Suggested-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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Adds the default config for K3_OPP_LOW in J7200
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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Adds a check for K3_OPP_LOW config and will change MPU freq/voltage
and msmc clock according to opp_low spec.
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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Useful when trying to check if an opp efuse is burned in or not.
k3_avs driver checks opp_ids when probing and overwrites the voltage
values in vd_data for the respective board. This can be called to check
that data and returns 0 if valid.
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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Upstream u-boot changed to using the ti,j7200-vtm compatible with
the Linux 6.6 DT sync, so using the same here
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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Add opp_low to j721e vd_data
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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J7200 has support for opp_low, so adding the option here
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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The J7200 SoC supports MPU core voltage of 760mv
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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Define the MSMC clk in the a72 node
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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commit 09a17b0d01dd7c81f6fd96228581d7df47a1a7b1 upstream
Mention TI_DM argument can be used to fetch a custom DM binary in the
A72 build instructions for K3 devices.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
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commit 3ef977e085767df31e42262f15837a66558052db upstream
Move the DM entry in tispl.bin FIT image from default fetching an
external blob entry to fetching using ti-dm entry type. This way, the
DM entry will be populated by the TI_DM pathname if provided. Else it
will resort to the ti-dm.bin file.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
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commit 23d2ef91efa40d525a4a5557704184bcfd64ca16 upstream
K3 devices introduces the concept of centralized power, resource and
security management to System Firmware. This is to overcome challenges
by the traditional approach that implements system control functions on
each of the processing units.
The software interface for System Firmware is split into TIFS and DM. DM
(Device Manager) is responsible for resource and power management from
secure and non-secure hosts. This additional binary is necessary for
specific platforms' ROM boot images and is to be packaged into tispl.bin
Add an entry for DM. The entry can be used for the packaging of
tispl.bin by binman along with ATF and TEE.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
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Update ARM64 MMU entries for J722S to support early remoteproc
boot requirements.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Sync with Linux device-tree w.r.t. CPSW3G.
With this, MAC Port 1 of the CPSW3G instance of CPSW Ethernet Switch
is functional in RGMII-RXID mode of operation.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Introduce the initial configs needed to support the J722S SoC family.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Include the uboot device tree files needed to boot the board.
Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Pull in the device tree source files for TI's J722S SoCs needed to boot
the board from v6.6-rc5. These are an early release with only the
peripherals to boot the board via UART boot.
Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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PSIL mapping is same as AM62P other than extra instances of CSI-RX.
Reuse the same file and add CSI PSIL mapping there.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Introduce the basic files needed to support the TI J722S family of SoCs.
Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Include the static DMA channel data for using DMA at SPL stage
for J722S SoC family.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Introduce the basic functions and definitions needed to properly
initialize TI J722S family of SoCs.
Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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The J722S family of SoCs uses the same DDR controller as found on the
AM62A family. Enable this option when building for the J722S family.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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Introduce support for J722S SoC.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Include the part number for TI's j722s family of SoC
to identify it during boot.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Update variable name_fdt for beagleboneai64 case with vendor prefix
to locate the dtb files. This prefix of vendor specific directory
is made to avoid naming issues and match the path on the latest kernel
versions.
Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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The macro ELM_BASE is defined in mach/hardware.h and is
not visible at the omap_elm.h header file. Avoid using it
in omap_elm.h.
Reported-by: Hong Guan <hguan@ti.com>
Fixes: 7363cf0581a3 ("mtd: rawnand: omap_elm: u-boot driver model support")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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Increase the SPL_STACK_R_MALLOC_SIMPLE_LEN to 0x200000 to accommodate the
size of tispl.bin fit image. With the recent upgrade of ti-linux-firmware
from version v9.1.0 to v9.2.5, the size of tispl.bin fit image has
increased to 1.4MB, causing allocation errors in the R5 SPL:
```
alloc space exhausted
Could not get FIT buffer of 1325056 bytes
check CONFIG_SPL_SYS_MALLOC_SIZE
```
Upstream-Status: Submitted [https://lore.kernel.org/all/20240320164845.141894-1-hiagofranco@gmail.com/]
- Only the verdin-am62_r5_defconfig was submmited because USB support is
missing upstream, and there is no verdin-am62_r5_usbdfu_defconfig file
yet.
Related-to: ELB-5658
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
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The lowest speed grade of Toradex AM62 SoMs is K speed, resulting in a
max value of 800MHz for the CPU operating frequency. A solution with
runtime selection of the CPU frequency is already planned to avoid these
kinds of problems in the future.
Upstream-Status: Submitted [https://lore.kernel.org/u-boot/20240319140427.73721-1-jpaulo.silvagoncalves@gmail.com/T/#u]
Fixes: 8fb8a6d49977 ("arm: dts: k3-am625-verdin-r5:Change CPU
frequency to 1000MHz")
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
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The same U-Boot binary is compatible with multiple Verdin AM62 board
variants. However, some of the SoC models can only operate at a maximum
speed of 1 GHz.
Previously, the boards with lower-speed grades were running at
overclocked speeds, leading to kernel complaints about unsupported
configurations.
To resolve this issue, the operating speed has been decreased to the
maximum allowable value across all Verdin AM62 board variants. As a
result, there is a regression in overall boot time, increasing by around
200 milliseconds for the faster SoC variant.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240219123408.22054-1-ivitro@gmail.com]
Related-to: ELB-5325
Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
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This reverts commit d2099587d661c6ca2309256c0e04c06e26c8d34c.
According to TI changing the VDD_CORE while the SoC is running is not
allowed, the voltage must be set before the AM62 device reset is
released, revert this change therefore.
The correct solution would be to program the PMIC during manufactoring
according to the speed grade of the SoC.
Upstream-Status: Backport [ea7d3eec1e6e6541db68bf48a1314410e06cd9de]
Link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1318338/am623-booting-from-mmc-failed-after-lowering-vdd_core-to-0-75v/5036508#5036508
Fixes: d2099587d661 ("board: verdin-am62: set cpu core voltage depending on speed grade")
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
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Read the max temperature for the SoC temperature grade from the hardware
and change the critical trip nodes on each thermal zone of FDT at
runtime so they are correct with the hardware value for its grade.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240208092951.11769-1-francesco@dolcini.it/#t]
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
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AM62x SoC is available in multiple temperature grade:
- Commercial: 0° to 95° C
- Industrial: -40° to 105° C
- Automotive: -40° to 125° C
Add a new function that returns the am62 max temperature value
accordingly to its temperature grade in Celsius.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240208092951.11769-1-francesco@dolcini.it/#t]
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
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Speed grade T requires the VDD_CORE voltage to be 0.85V if using
the maximum core frequency.
Speed grades G, K, S allow the VDD_CORE voltage to be 0.75V up to the
maximum core frequency but allow to run at 0.85V.
For efficiency in manufacturing and code maintenance we use 0.85V for
the PMIC defaults and device tree settings and dynamically adjust the
voltage in the PMIC and device tree to 0.75V for lower speed SKU to
gain more than 100mW power consumption reduction.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240117101743.3955852-1-max.oss.09@gmail.com/T/#t]
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Add two functions, one which returns the SoC speed grade and one
which returns the SoC operating temperature range.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240117101743.3955852-1-max.oss.09@gmail.com/T/#t]
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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mach-k3/am625_fdt.c does fdt fixup depending on fields in the device
identification register. Move the accessors to the device identification
register as inline functions into the am62_hardware.h header, so that
they can be used for other functionality.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240117101743.3955852-1-max.oss.09@gmail.com/T/#t]
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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TI recommends to clear the bit independent of the used voltage.
So the comment which claims to do it due to the core voltage
at 0.85V is bogus.
See https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1252724/am625-usb-phy-core-voltage-selection-and-vdda_core_usb-mismatch
Upstream-Status: Submitted [https://lore.kernel.org/all/20240117101743.3955852-1-max.oss.09@gmail.com/T/#t]
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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These headers follow the pattern:
| #if CONFIG_IS_ENABLED(FANCY_FEATURE)
| void foo(void);
| #else
| static inline void foo(void) { return -ENOSYS; }
| #endif
In the #else path ENOSYS is used, however linux/errno.h is not included.
If errno.h has not been included already the compiler errors out even
if the inline function is not referenced.
Make those headers self contained.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240118181106.4133924-1-max.oss.09@gmail.com/T/#u]
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Adds fsstub binaries to tispl binary, this is required for
deepsleep functionality.
This implements the same change as commit 91886b68025c ("arm: dts: k3: binman: am625: add support for signing FSSTUB images")
did for TI AM62 SK board.
Upstream-Status: Pending
Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com>
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The current DDR subsystem configuration occasionally results in write failures,
impacting memory stability, on Verdin AM62 Solo 512MB WB IT 0072 SKU.
This commit addresses the issue by adjusting Drive Pull-Up/Down and
Write Latency to improve the eye diagram and ensure reliable write operations.
This configuration is shared with all Verdin AM62 SoM and
it does not introduce regressions.
Configurations changes from previous / default values:
- Drive Pull-Up/Down from 40 to 34.3 Ohm
- Write Latency from 8 to 10
- ODTLon / ODTLoff latency from 0 / 0 to 4 / 20 nCK
- VREF control range 1 at 27 %
- tFAW from 30 to 40 ns
Configuration is output from SysConfig [1] web tool, currently at version
1.18.1+3343 (DDR SubSystem v9.10).
[1] https://dev.ti.com/sysconfig
Upstream-Status: Submitted [https://lore.kernel.org/all/20231219082533.8399-1-francesco@dolcini.it/]
Fixes: 7d1a10659f5b ("board: toradex: add verdin am62 support")
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
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RC Release 09.01.00.008
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