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2019-05-07efi_loader: clean up UEFI sub-system initializationHeinrich Schuchardt
allow_unaligned(), switch_to_non_secure_mode(), and efi_init_obj_list() are called in sequence in multiple places. Move calls to allow_unaligned() and switch_to_non_secure_mode() to efi_init_obj_list(). Remove unused includes. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-06Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Various pinctrl / gpio fixes for R-Car
2019-05-06Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
- Important spi-mem fix
2019-05-05Merge branch '2019-05-05-master-imports'Tom Rini
- Various assorted fixes - btrfs zstd compression support - Enable hardware DDR levelling on am43xx platforms. - pl310 cache controller driver
2019-05-05env: add missing newlinePhilip Molloy
Signed-off-by: Philip Molloy <philip@philipmolloy.com>
2019-05-05board: toradex: drop support.arm maintainer emailMarcel Ziswiler
Drop Toradex ARM Support <support.arm@toradex.com> from maintainer email list as this just clogs our support ticketing system. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
2019-05-05cmd: pxe: add board specific PXE default pathMarek Behún
The list of PXE default paths contains ARCH and SOC specific paths, but one PXE server can serve different board with the same ARCH and SOC. This is the case for Turris Omnia and Turris Mox, where ARCH=arm and SOC=mvebu. If CONFIG_SYS_BOARD is defined, also try "default-$ARCH-$SOC-$BOARD" path. Signed-off-by: Marek Behún <marek.behun@nic.cz>
2019-05-05ARM: da850evm: Enable da850-ohci USB host controllerAdam Ford
The DA850 EVM has one USB 1.1 OHCI Host controller. With the host controller now support DM_USB, this patch enables the respective functions for the da850evm. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-05-05usb: ohci: ohci-da8xx: Enable da850-ohci driver with DM supportAdam Ford
This patch reuses some former code for the hawkboard, combines it with some some similar DM_USB compatible code for the OHCI driver, and enables the use of the da850's OHCI controller with DM_USB compatibility. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-05-05fs: btrfs: add zstd decompression supportMarek Behún
This adds decompression support for Zstandard, which has been included in Linux btrfs driver for some time. Signed-off-by: Marek Behún <marek.behun@nic.cz>
2019-05-05lib: add Zstandard decompression supportMarek Behún
Add the zstd library from Linux kernel (only decompression support). There are minimal changes to build with U-Boot, otherwise the files are identical to Linux commit dc35da16 from March 2018, the files had not been touched since in kernel. Also SPDX lincese tags were added. Signed-off-by: Marek Behún <marek.behun@nic.cz>
2019-05-05lib: Add xxhash supportMarek Behún
This adds the xxhash support from Linux. Files are almost identical to those added to Linux in commit 5d240522 ("lib: Add xxhash module") (they haven't been touched since in Linux). The only difference is to add some includes to be compatible with U-Boot. Also SPDX lincese tags were added. Signed-off-by: Marek Behún <marek.behun@nic.cz>
2019-05-05board: ti: am43xx: Enable hardware levelingBrad Griffis
Remove the RDLVL_MASK, RDLVLGATE_MASK, WRLVL_MASK & enable PHY_INVERT_CLKOUT to enable Hardware leveling for am437x as recommended by EMIF Tools app note: http://www.ti.com/lit/an/sprac70/sprac70.pdf Signed-off-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-05-05arm: mach-omap2: am33xx: ddr: update value for ext_phy_ctrl_36Brad Griffis
for suspend/resume robustness update value for ext_phy_ctrl_36 for suspend/resume robustness with hardware leveling enabled. Match recommended values from EMIF Tools app note: http://www.ti.com/lit/an/sprac70/sprac70.pdf Signed-off-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-05-05arm: mach-omap2: am33xx: Disable EMIF_DEVOFF immediately before hw levelingBrad Griffis
In case of RTC+DDR resume, need to restore EMIF context before initiating hardware leveling. Signed-off-by: Brad Griffis <bgriffis@ti.com> [j-keerthy@ti.com Fixed the am335x build issues] Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-05-05arm: mach-omap2: am33xx: Enable HW Leveling in the rtc+ddr pathBrad Griffis
Enable HW leveling in RTC+DDR path. The mandate is to enable HW leveling bit and then wait for 1 ms before accessing any register. Signed-off-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-05-05arm: mach-omap2: am33xx: ddr: Add 1ms delay to avoid L3 errorBrad Griffis
Add 1ms delay to avoid L3 timeout error during suspend resume. Signed-off-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-05-05arm: mach-omap2: am33xx: ddr: programming of EXT_PHY_CTRL1 and ↵Brad Griffis
EXT_PHY_CTRL1_SHADOW Adjust DQS skew in case where invert_clkout=1 is used. Match recommended values from EMIF Tools app note: http://www.ti.com/lit/an/sprac70/sprac70.pdf Signed-off-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-05-05lib/display_options: avoid illegal memory accessHeinrich Schuchardt
display_options_get_banner_priv() overwrites bytes before the start of the buffer if the buffer size is less then 3. This case occurs in the Sandbox when executing the `ut_print` command. Correctly handle small buffer sizes. Adjust the print unit test to catch when bytes before the buffer are overwritten. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-05configs: am335x_evm: enable SPL_FIT_IMAGE_TINYJean-Jacques Hiblot
The size of the SPL for the am335x_evm is constrained. There is no need to have advanced SPL FIT features, so keep the SPL FIT support tiny. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-05-05spl: fit: Always enable tracking of os-type if SPL_OS_BOOT is enabledJean-Jacques Hiblot
FIT_IMAGE_TINY is used to reduce the size of the SPL by removing os-type tracking and recording the loadables into the loaded FDT. When this option is enabled, it is assumed that the next stage firmware is u-boot. However this does not play well with the SPL_OS_BOOT option that enables loading different type of next stage firmware, like the OS itself. When SPL_OS_BOOT is used, do not disable os-tracking. The added footprint is about 300 Bytes. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-05-05spl: fix linker size check off-by-one errorsSimon Goldschmidt
This fixes SPL linker script size checks for 3 lds files where the size checks were implemented as "x < YYY_MAX_SIZE". Fix the size checks to be "x <= YYY_MAX_SIZE" instead. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-05configs: socfpga: add imply pl310 cache controllerDinh Nguyen
Select the PL310 UCLASS_CACHE driver for SoCFPGA. Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-05ARM: socfpga: use the pl310 driver to configure the cacheDinh Nguyen
Find the UCLASS_CACHE driver to configure the cache controller's settings. Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-05dm: cache: add the pl310 cache controller driverDinh Nguyen
Add a PL310 cache controller driver that is usually found on ARMv7(32-bit) devices. The driver configures the cache settings that can be found in the device tree files. This initial revision only configures basic settings(data & instruction prefetch, shared-override, data & tag latency). I believe these are the settings that affect performance the most. Comprehensive settings can be done by the OS. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-05dm: cache: Create a uclass for cacheDinh Nguyen
The cache UCLASS will be used for configure settings that can be found in a CPU's L2 cache controller. Add a uclass and a test for cache. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-05ARM: pl310: Add macro's for handling tag and data latency maskDinh Nguyen
Add the PL310 macros for latency control setup, read and write bits. Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-05Documentation: dts: Add pl310 cache controller dts documentationDinh Nguyen
Linux commit 8ecd7f5970c5 ("ARM: 8483/1: Documentation: l2c: Rename l2cc to l2c2x0") Linux docs: Documentation/devicetree/bindings/arm/l2c2x0.txt Copied from Linux kernel v5.0. "The documentation in the l2cc.txt is specific to the L2 cache controllers L2C210/L2C220/L2C310 (also known as PL210/PL220/PL310 and variants) and not generic as the file name implies. It's not valid for integrated L2 controllers as found in e.g. Cortex-A15/A7/A57/A53." Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-05board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 buildVignesh Raghavendra
AM654 SoC is IO coherent wrt A53 cores, therefore enable SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53 SPL/U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-05-05arch: armv8: Provide a way to disable cache maintenance opsVignesh Raghavendra
On AM654 SoC(arm64) which is IO coherent and has L3 Cache, cache maintenance operations being done to support non-coherent platforms causes issues. For example, here is how U-Boot prepares/handles a buffer to receive data from a device (DMA Write). This may vary slightly depending on the driver framework: Start DMA to write to destination buffer Wait for DMA to be done (dma_receive()/dma_memcpy()) Invalidate destination buffer (invalidate_dcache_range()) Read from destination buffer The invalidate after the DMA is needed in order to read latest data from memory that’s updated by DMA write. Also, in case random prefetch has pulled in buffer data during the “wait for DMA” before the DMA has written to it. This works well for non-coherent architectures. In case of coherent architecture with L3 cache, DMA write would directly update L3 cache contents (assuming cacheline is present in L3) without updating the DDR memory. So invalidate after “wait for DMA” in above sequence would discard latest data and read will cause stale data to be fetched from DDR. Therefore invalidate after “wait for DMA” is not always correct on coherent architecture. Therefore, provide a Kconfig option to disable cache maintenance ops on coherent architectures. This has added benefit of improving the performance of DMA transfers as we no longer need to invalidate/flush individual cache lines(especially for buffer thats several KBs in size). In order to facilitate use of same Kconfig across different architecture, I have added the symbol to top level arch/Kconfig file. Patch currently disables cache maintenance ops for arm64 only. flush_dcache_all() and invalidate_dcache_all() are exclusively used during enabling/disabling dcache and hence are not disabled. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-05-05Refactor IMAGE_ENABLE_VERIFY to handle builds without SPL verificationAlex Kiernan
If building with SPL_LOAD_FIT_FULL and FIT_SIGNATURE, but without SPL_FIT_SIGNATURE then the build fails with: common/built-in.o: In function `fit_image_verify_with_data': common/image-fit.c:1220: undefined reference to `fit_image_verify_required_sigs' common/image-fit.c:1244: undefined reference to `fit_image_check_sig' common/built-in.o: In function `fit_image_load': common/image-fit.c:1857: undefined reference to `fit_config_verify' Refactor so that host builds still depend on FIT_SIGNATURE, but target builds check FIT_SIGNATURE/SPL_FIT_SIGNATURE dependent on the build. Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-04Merge tag 'mips-pull-2019-05-03' of git://git.denx.de/u-boot-mipsTom Rini
- mscc: small fixes, enhance network support for Serval, Luton and Ocelot - mt7620: rename arch to more generic name mtmips - mips: pass initrd addresses via DT as physical addresses
2019-05-04Merge tag 'mmc-2019-5-3' of https://github.com/MrVan/u-bootTom Rini
2019-05-04Merge branch '2019-05-04-master-imports'Tom Rini
- Remove dead code from davinci - Migrate CONFIG_SUPPORT_EMMC_BOOT
2019-05-04cmd: mmc: Make Mode: printout consistentMarek Vasut
The "Mode :" line is the only one in "mmc info" output that has a space in front of the colon. Drop the space to make it consistent with the rest of the output, e.g.: => mmc dev 1 ; mmc info switch to partitions #0, OK mmc1 is current device Device: sd@ee160000 Manufacturer ID: 3 OEM: 5344 Name: SL08G Bus Speed: 50000000 Mode : SD High Speed (50MHz) ^------------------------------ Remove this space Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 7.4 GiB Bus Width: 1-bit Erase Group Size: 512 Bytes Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> CC: Tom Rini <trini@konsulko.com>
2019-05-04net: ravb: Avoid unsupported internal delay mode for R-Car E3/D3Marek Vasut
According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) or D3 (r8a77995). Avoid setting the APSR:TDM bit on these SoCs. Moreover, only set APSR:TDM when the DT explicitly specifies RGMII ID or TXID mode instead of setting it unconditionally when the PHY link speed is 1000 Mbit/s. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
2019-05-04ARM: rmobile: Always select pin control drivers on Gen3Marek Vasut
To assure the pins on R-Car Gen3 SoCs are configured correctly, always select pin control drivers on Gen3 SoCs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-04pinctrl: renesas: Remove sh_pfc_config_mux_for_gpio()Marek Vasut
This function is now replaced by common pin controller GPIO configuration functionality, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04gpio: renesas: Migrate to pinctrl GPIO accessorsMarek Vasut
Switch to generic pin controller API for configuring pins as GPIOs instead of using the ad-hoc call into the R-Car PFC driver. Moreover, add .free() implementation for the GPIO controller. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04pinctrl: renesas: Implement gpio_request_enable/gpio_disable_freeMarek Vasut
Implement the gpio_request_enable/gpio_disable_free callbacks to let the GPIO driver call the pin control framework and let it reconfigure pins as GPIOs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04pinctrl: renesas: Set pin type in sh_pfc_config_mux_for_gpioMarek Vasut
Add missing cfg->type = PINMUX_TYPE_GPIO upon successfully setting pin as a GPIO to retain the pin configuration information. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04pinctrl: gpio: Add callback for configuring pin as GPIOMarek Vasut
Add callback to configure, and de-configure, pin as a GPIO on the pin controller side. This matches similar functionality in Linux and aims to replace the ad-hoc implementations present in U-Boot. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04ARM: renesas: Configure DRAM size from ATF DT fragmentMarek Vasut
The ATF can pass additional information via the first four registers, x0...x3. The R-Car Gen3 with mainline ATF, register x1 contains pointer to a device tree with platform information. Parse this device tree and extract DRAM size information from it. This is useful on systems where the DRAM size can vary between configurations. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-04cmd: clk: Handle ENODEV from clk_get_rateIsmael Luceno Cortes
clk_get_rate may return -ENODEV if the clock isn't valid. Also, make the error cases go through a single path. Fixes: ff8eee0330a6 ("cmd: clk: Add trivial implementation of clock dump for DM") Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
2019-05-04delete Kbuild "select" of long-dead SPL_DISABLE_OF_CONTROLRobert P. J. Day
>From way back in 2015: commit dffb86e468c8e02ba77283989aefef214d904dc5 Author: Masahiro Yamada <yamada.masahiro@socionext.com> Date: Wed Aug 12 07:31:54 2015 +0900 of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROL As we discussed a couple of times, negative CONFIG options make our life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ... and here is another one. Now, there are three boards enabling OF_CONTROL on SPL: - socfpga_arria5_defconfig - socfpga_cyclone5_defconfig - socfpga_socrates_defconfig This commit adds CONFIG_SPL_OF_CONTROL for them and deletes CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert the logic. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-05-04Convert CONFIG_SUPPORT_EMMC_BOOT to KconfigAlex Kiernan
This converts the following to Kconfig: CONFIG_SUPPORT_EMMC_BOOT As requested by Michal Simek <michal.simek@xilinx.com>, these boards have no eMMC so CONFIG_SUPPORT_EMMC_BOOT has not been migrated: xilinx_zynqmp_zc1275_revB xilinx_zynqmp_zc1751_xm018_dc4 xilinx_zynqmp_zc1751_xm019_dc5 xilinx_zynqmp_zcu100_revC xilinx_zynqmp_zcu102_rev1_0 xilinx_zynqmp_zcu102_revA xilinx_zynqmp_zcu102_revB xilinx_zynqmp_zcu104_revA xilinx_zynqmp_zcu104_revC xilinx_zynqmp_zcu106_revA xilinx_zynqmp_zcu111_revA Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Acked-by: Lukasz Majewski <lukma@denx.de> Acked-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2019-05-04arm: davinci: remove leftover code for dm* SoCsBartosz Golaszewski
The support for DaVinci DM* SoCs has been dropped a while ago. There's still a lot of leftover code in mach-davinci though. Entirely remove certain files and modify the common code to no longer reference unsupported chips. Note: all DaVinci platforms supported in u-boot now define SOC_DA8XX but not all define SOC_DA850 (e.g. omapl138). We can safely remove all ifdefs for the former, but let's leave the ones for the latter. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-05-04usb: musb_hcd: remove unnecessary ifdefs for dm* SoCsBartosz Golaszewski
The support for DaVinci DM* SoCs has been dropped. The ifdefs in the musb_hcd driver are no longer needed. Remove them. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by: Marek Vasut <marex@denx.de>
2019-05-04nand: davinci: remove dead code for dm644xBartosz Golaszewski
The support for DaVinci DM* SoCs has been dropped. The code that used to be relevant to dm644x is no longer needed. Remove it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-05-04arm: davinci: remove dead code for PHYs used by DaVinci DM* boardsBartosz Golaszewski
The support for DaVinci DM* boards has been dropped a while ago. The code for all those PHYs is no longer used and they have their own proper PHY drivers in drivers/net/phy anyway. Remove all dead code. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
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