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2020-03-05apalis-imx8: fix eMMC/MMC/SD interface muxingStefan Agner
Signed-off-by: Stefan Agner <stefan.agner@toradex.com> (cherry picked from commit fa3d4f980a515b135778a74ce1b7476f61ef20d0) (cherry picked from commit 2ee92bc1dd56b44343079a5474d0fc4e79f28f4a) (cherry picked from commit 649afbe0aec4089112772a49a7e6f7d34c3741a7) (cherry picked from commit 81591346d11ffdf9a2442ad976390ffe0e61abda)
2020-03-05apalis-imx8: add Apalis iMX8 specific device treeStefan Agner
Signed-off-by: Stefan Agner <stefan.agner@toradex.com> (cherry picked from commit aa830cb6a7c953ce85232b2ae951543ab1060948) (cherry picked from commit f6c37cdf31633a541078d0813ab4f59f6b80babb) (cherry picked from commit ae70d02213beabcd60853f655e2ff9849375c45c) (cherry picked from commit ba629689c627a571d5902a1c50fe9927424b45c6)
2020-03-05apalis-imx8: initial addStefan Agner
Initial board support for Apalis iMX8 using a copy of NXP iMX8QM ARM2 LPDDR4 board. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> (cherry picked from commit 68e401998ba0654292b7914b85433d8453202ec8) (cherry picked from commit 6b9234fa1f5889f0eeecc6147afffbc859933c99) (cherry picked from commit 0b7feded806717b4292615373ed6c018324b8ef5) Conflicts: arch/arm/cpu/armv8/imx8/Kconfig, file moved (cherry picked from commit 393dd8dd4061833fcc3cfd85886d49160b515ce0)
2020-02-12MLK-23289 driver: ddr: correct the pwrctl setting of selfref_en on imx8mJacky Bai
The 'selfref_en' should be bit'0', so correct the setting to enable the auto self-refresh. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Jian Li <jian.li@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-02-05SSI-87: imx8: snvs: Update behaviorFranck LENORMAND
Changes: - warning about behavior of B0 and C0 SoCs - support of interruption configuration - porperly support code for 8QM - Fix the clear acommand Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Reviewed-by: Silvano Di Ninno <silvano.dininno@nxp.com> (cherry picked from commit 12534e02bbca7b9746a3d3e60d2f6157b9131149)
2020-02-05TEE-502 imx: refactor optee bindings additionSilvano di Ninno
- Remove code duplication betwee imx8 and imx8m support - add reserved memory node to prevent Linux accessing optee reserved memory Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 8beac7ef22c16b72ad337b44a0516436a4a0d00c)
2020-01-15MLK-23241 imx8dx_mek: Add iMX8DX MEK board supportYe Li
iMX8DX MEK board has similar design with 8QXP MEK. The major changes are 1. DDR changed to 16bits 1GB DDR part 2. USB3.0 is removed and only support OTG on typec port. (No SW change needed) This patch adds new defconfigs and DTS file for this new board. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 5efb4275f6cfefb5dd342f2e498834b40b989883)
2020-01-02MA-16203 Load boot/dtbo image to fixed memoryJi Luo
Only limited heap memory is available on imx8q platforms due to some memory is reserved for m4 image. Commit cd67414 will free avb verify data and thus help decrease the heap memory consumption. But when the device is locked, avb will try to verify one slot first, it will continue to verify another if the first slot returns failure. Function load_full_partition() will alloc memory to load boot/dtbo images from heap (which is a big and continuous memory region), this memory will be freed if the first slot returns verify failure. but because part of the continous memory region will be used in following verify process, even total available memory is enough, u-boot can't find a continous memory region to load the boot/dtbo image for another slot and will return error "Failed to allocate memory". Instead, this commit use fixed memory region start from 96MB offset of CONFIG_FASTBOOT_BUF_ADDR to load the boot/dtbo images. Test: slot verify and A/B slot switch. Change-Id: Ifc83bed5a6be37196c0fd109d942eaf9b07b6a74 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2019-12-31MLK-23179 board: imx8mn_evk: Update the ddr QoS setting on imx8mn ddr4 evkJacky Bai
The QoS setting is originally added in MLK-22001, but override when update the DDR script for DLL-ON only support, so add it back again. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2019-12-30MA-16095-1 remove CONFIG_USB_TCPC form defconfig filesfaqiang.zhu
Android does not use usb host function in uboot, and also TCPC function failure may cause the fastboot does not work, remove all CONFIG_USB_TCPC configuration items so TCPC is not used in uboot. Change-Id: I8c54e144517160bd7234a8ae28c6bc83734be538 Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
2019-12-27MA-16095 set evk_8mm/evk_8mn usb dr_mode to "otg"faqiang.zhu
When trying to remove "CONFIG_USB_TCPC=y" to avoid ramdom issue of synchronous abort when enter fastboot, evk_8mm and evk_8mn can't enter fastboot mode, it's because init_type of the usb udevice private data is host if tcpc configuration is removed, if this init_type is host/peripheral, then the usb is forced to be this mode, can not be initialized as another. init_type of the usb udevice private data is firstly set based on the "dr_mode" in dtb, if "dr_mode" is not set, it will be set by other ways. here set the "dr_mode" property for the usb device to be "otg", then the device can be configured as either host or peripheral. Change-Id: Idadab7bb07e74bfc1f8768490c07127a35a02572 Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
2019-12-18MA-15860 Get and switch the target dev in fastboot eraseJi Luo
Target mmc dev is not properly switched when the device enters fastboot mode via uuu "-i" parameter, which causes "erase" operation doesn't work. Get and switch the target mmc dev every time before erase operations happen. Test: "fastboot erase boot_a" in uuu fastboot mode. Change-Id: I4822d2b4ecfd2d874dfbe7474d6824b8fc3a7903 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2019-12-13MLK-23093 imx8m: Enable WDOG_B for timeoutYe Li
When doing reset_cpu, in normal case the WDOG_B outputs immediately after we clean WDA bit. But on mscale, the WDOG_B may be later than internal reset, and cause PMIC not reset. As we enabled the SD3.0 support, the PMIC must be reset to reset SD card. Change the reset_cpu to enable the WDOG_B for timeout as well, and set WDOG timeout to 1s. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit e78f889637636d8b67fe6250623f3473514f1a23)
2019-12-10MA-16048 Fix imx8q u-boot hangJi Luo
Address 0x8880_0000 is reserved for M4 image on imx8q, which leaves limited memory region for the malloc pool. The avb will consume much heap memory to verify the kernel and dtbo image, memory conflicts may happen as the kernel/dtbo image size is getting larger. As the avb will load kernel/dtbo in every avb_slot_verify(), but will only free the memory after both slots are checked(if needed). And for trusty enabled platforms, extra heap memory will be used to do the hash calculation. This commit will free the slot memory once it's marked as unbootable and will use fixed memory started from CONFIG_FASTBOOT_BUF_ADDR to help store the data to do the hash calculation. With above change, we get a chance to decrease the malloc pool size. Test: boot on imx8qxp and imx8mn. Change-Id: Id95b9becf6fa7fae4f120a4dc9e9a3ba90da578c Signed-off-by: Ji Luo <ji.luo@nxp.com>
2019-12-09MLK-23101 imx8mn: Fix address conflict in SPLYe Li
The latest patch "MLK-23081 imx8mn: Change SPL malloc and BSS address" changed SPL runtime data to OCRAM_S. But this introduced a conflict with CONFIG_SAVED_DRAM_TIMING_BASE which is also using OCRAM_S for DDR parameters. To fix the issue, adjust the SPL runtime data addresses to reserve 16KB space for DDR parameter and move SPL BSS to OCRAM. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 20fdadfa50227b518d1a185da4c59e756eb8e594)
2019-12-05MLK-23088 imx8mn: Fix u-boot hang when ENV_IS_NOWHERE is enabledYe Li
By default we enable two env storage devices: SD/emmc or Flexspi. And u-boot will select it according to boot device. Some customer does not save env, so he removes these storage devices and enable ENV_IS_NOWHERE. But current env_get_location does not process the ENV_IS_NOWHERE, returns ENVL_UNKNOWN and causes u-boot hang. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 8ca25fba643e4cdbd71f8c7a41d0991e57388fc8)
2019-12-05MLK-23081 imx8mn: Change SPL malloc and BSS addressYe Li
Android's build has large size of SPL which overlays with malloc pool, and causes DDR FW image destroyed by the malloc. Adjust some SPL addresses to align with iMX8MQ and allow SPL + DDRFW using the 312 KB OCRAM from 0x912000 to 0x960000. Since the max DDR FW size is 96KB, we set max SPL size to be 216KB. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit e3df1f1cf9972ce8ed84de09d183599bd52a5c47)
2019-12-05MLK-23037 board: imx8mm_evk: update ddr4 timing for dll-on modeJacky Bai
Update the ddr4 timing file for 2400mts & 1066mts for dll-on mode only. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit f7ed1fd1416f15764cca13993a054963996f6c50)
2019-12-05MLK-23027 imx8mm/imx8mn: Adjust MMC bus width in SPLYe Li
The SPL codes for both EVK and validation board set the MMC bus width to 1 bit for both emmc and SD ports. This causes slow image loading. Change to 8 bits for emmc and 4 bits for SD. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 0859140a862ad1cc16f4e49247868595a6e62b38)
2019-12-05MLK-22998-1 iimx8qm/imx8qxp: Update to latest SCFW APIRanjani Vaidyanathan
Sync SCFW API to commit b3c575a62b0e2 SCFW API version 16 Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> (cherry picked from commit 83014c2cdab9aeef0e1cbeb97820369b21995ea9)
2019-12-05SSI-87: imx8: Configure SNVSFranck LENORMAND
Add a module to configure the tamper and secure violation of the SNVS using the SCU API. The module also adds some commands: - snvs_cfg: Configure the SNVS HP and LP registers - snvs_dgo_cfg: Configure the SNVS DGO bloc if present (8QXP) - tamper_pin_cfg: Change the configuration of the tamper pins - snvs_clear_status: Allow to write to LPSR and LPTDSR to clear status bits Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> (cherry picked from commit 75aa7f2254f0883aa14568ac32702b1ca15367e4)
2019-12-04MA-16001-2 Enable android imx8mn lpddr4 boardJi Luo
Change configs to make imx8mn lpddr4 works on Android. Test: build and boot. Change-Id: Ibd27d73a973660a7d80bf85ba285f5f7619ecbb8 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2019-12-04MA-16001-1 Add configs for imx8mn lpddr4 boardJi Luo
Add build target for imx8mn lpddr4 board based on config imx8mn_evk_defconfig. Change-Id: Iceca7cb65c6417fc3da1878323f8a65ffc31e1ef Signed-off-by: Ji Luo <ji.luo@nxp.com>
2019-11-20MLK-22998 iimx8qm/imx8qxp: Update to latest SCFW APIRanjani Vaidyanathan
Sync SCFW API to commit 6dcd0242ae Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2019-11-05MA-15813-2 [Android] imx8q: Enable reset in spl stageJi Luo
The psci driver is not available at spl stage, calling reset_misc() will lead to panic. Guard the reset_misc() with "CONFIG_SPL_BUILD" config, leave the reset_cpu() to trigger board reset. Test: reset om imx8qm_mek. Change-Id: Icf95eb4505ba444f9930aa0320d34456fa22733f Signed-off-by: Ji Luo <ji.luo@nxp.com>
2019-11-05MA-15814 Check 'successful_boot' flag before marking unbootableJi Luo
Slot will be marked as "unbootable" state if error happens during image load/verify process, this may cause the board never boot up if some random failures happen (like eMMC/DRAM access error at some critical temperature). Check the "successful_boot" flag before marking the slot as "unbootable", this will help ease the "no bootable slot" issue. Test: slot switch on imx8qm_mek. Change-Id: Idfcc5723aa233e9019365b792c48bf8a5dc99b96 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2019-11-01MLK-22881 board: imx8mn: Update the DDR4 timing script on imx8mn ddr4 evkJacky Bai
On i.MX8MN, we can only support DLL-ON mode only, so update the timing to support 2400mts & 1066mts setpoint. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2019-10-28MLK-22851-4 imx8mm/imx8mn: Enable eMMC HS400ES and SD UHS mode on EVKYe Li
Both imx8mn/imx8mm EVK boards have eMMC 5.1 chip and support SD3.0 So we enable the HS400ES and UHS configs to enhance eMMC/SD access. The change also needs to set usdhc clock to 400Mhz and update compatible string to fsl,imx8mm-usdhc Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-27MLK-22851-3 imx8mq: Enable eMMC HS400 and SD UHS mode on EVKYe Li
iMX8MQ EVK board has a eMMC5.0 chip and supports SD3.0, so enable the UHS and HS400 configs to enhance the eMMC/SD access. The change also needs to set usdhc clock to 400Mhz, and add the off-on-delay-us to SD reset pin, otherwise some SD cards will fail to select UHS mode in re-initialization. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-10-27MLK-22851-2 mmc: fsl_esdhc: Update compatible string for imx8mYe Li
To enable HS400 and UHS for imx8m platforms, update the driver data to share with imx8x platforms and add relevant compatible string. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-10-27MLK-22851-1 mmc: fsl_esdhc: reduce unnecessary clock changeYe Li
In mmc initial state, the mmc framework sets clock to 0, so the fsl_esdhc driver converts to use min clock 400Khz. But the priv->clock is logged 400Khz not 0, and cause following calls to set_ios to set clock again. Each set to clock has 10ms delay for stable, then the problem accumulates some unnecessary delay. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-10-24MLK-22832 board: imx8mn_evk: Fix the retention hang on imx8mn lpddr4 evkJacky Bai
The '0x20060' register is used for phy memory reset, should not be put in the ddrphy config section, so remove it from the timing script, otherwise, ddr retention can NOT work. Additionally, the'0xd0000' register config in phy section is redundant, remove it too. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-23MLK-22830 mx7ulp: Fix build break of mx7ulp_evk_m4boot_defconfigYe Li
Get build error when using mx7ulp_evk_m4boot_defconfig arch/arm/lib/built-in.o: In function `setup_serial_tag': /home/leyoen/Workspace/uboot-imx/arch/arm/lib/bootm.c:191: undefined reference to `get_board_serial' The boot cause is CONFIG_SERIAL_TAG is defined in header file without depending on fastboot, but the function definition uses CONFIG_FSL_FASTBOOT. So remove the wrong macro from function definition to fix the issue Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-16MLK-22762 imx8mn_ddr4_evk: Set VDD_SOC to 0.85v in suspend modeYe Li
According to datasheet, the VDD_SOC should be 0.85v in suspend mode. But current voltage is default 0.80v because we don't configure BD71837 BUCK1_VOLT_SUSP register. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-16MLK-22759-4 DTS: imx8mn: Update DDR4 EVK DTSYe Li
Add the "DDR4" to board name to distinguish with LPDDR4 board. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-15MLK-22759-3 imx8mn: Add LPDDR4 EVK board supportYe Li
Add support for iMX8MN LPDDR4 EVK board which uses 2GB LPDDR4 and PCA9450B PMIC. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-10-15MLK-22759-2 power: Add new PMIC PCA9450 driverYe Li
PCA9450 PMIC series is used to support iMX8MM (PCA9450A) and iMX8MN (PCA9450B). Add the PMIC driver for both PCA9450A and PCA9450B. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
2019-10-15MLK-22759-1 imx8mn: Use CONFIG_TARGET_IMX8MN_DDR4_EVK for DDR4 EVK boardYe Li
To align with other iMX8M platforms, use CONFIG_TARGET_IMX8MN_DDR4_EVK for DDR4 EVK board and will use CONFIG_TARGET_IMX8MN_EVK for LPDDR4 EVK. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-10-11MLK-22748 imx8mn: Fix flexspi flash SCLK violationYe Li
Current flexspi driver enables the Quad DTR read, so the measured 100Mhz SCLK is actually for DTR mode not SDR. However, according to MT25QU256ABA datasheet, this flash only supports max DTR at 90Mhz and max SDR at 166Mhz. It means current clock setting violate the flash spec. So change back the flexspi clock to align with imx8mm. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-09MLK-22711-2: fastboot: emmc: update bootloader to offset 0 for RevC QXP chipFrank Li
ROM update emmc offset to 0. previous B0 is 32K. Signed-off-by: Frank Li <Frank.Li@nxp.com>
2019-10-09MLK-22711-1 show RevC instead of Rev? at boot logFrank Li
Add REVC informaiton. Signed-off-by: Frank Li <Frank.Li@nxp.com>
2019-10-09MA-15582 Fix imx8mn u-boot hangJi Luo
The u-boot-spl.bin is getting larger and it will break the ddr firmware which will cause ddr training fail. Disable unnecessary configs for imx8mn to reduce the spl image size. Test: boot on imx8mn_evk. Change-Id: Id105b0adf8669e471752495f78012314efad24c0 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2019-09-27MLK-22622 imx8m: Add Workaround for ROM SError issueYe Li
ROM SError happens on two cases: 1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but when ROM patch lock is fused, this write will cause SError. 2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB is field return mode, but the last 4K of ROM is still protected and cause SError. Since ROM mask SError until ATF unmask it, so then ATF always meets the exception. This patch works around the issue in SPL by enabling the SError exception and take it to eret immediately to clear the SError. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-09-17imx: add lowlevel init for ARM64Peng Fan
Sometimes we met SERROR, but only to catch it when Linux boots up. Let's enable catching in U-Boot to catch it ealier and ease debug. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 7a0c9b08886e5dc7d50e640ed56eed0fe612161f)
2019-09-10MLK-22576 imx8: video: Set clock parent for DC0 display channelYe Li
When enable u-boot splash screen and set kernel dtb with -hdmi.dtb on imx8qm, the kernel reboot (partition reboot) will hang in u-boot if HDMI cable is plugged in. The root cause is kernel set the clock source of DC0 display0 channel to bypass clock, when doing reboot this clock setting may not be cleared. So u-boot has wrong clock source and cause lpcg stop bit always set. Fix the issue by adding the clock parent setting and not depend on default parent value. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-08-26MA-15334-2 enable trusty for imx8q standard Android ubootfaqiang.zhu
"CONFIG_IMX_TRUSTY_OS=y" is added to the corresponding defconfig files to include trusty related code. "CONFIG_SPL_ENV_SUPPORT=y" and "CONFIG_SPL_LIBDISK_SUPPORT=y" are added because "mmc_get_env_dev()" and "blk_get_dev()" are invoked in SPL stage with trusty related code. "CONFIG_SHA256=y" is added since SPL will access RPMB now. MACROs are added in corresponding header files. standard android uboot has more content than android auto uboot, the uboot malloc pool size is changed from 76MB to 86MB to make the boot process can be handed over to kernel without malloc problem. Change-Id: I7505adeb2e30ddaecc8217cee991e6d7b0785af0 Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
2019-08-26MA-15334-1 add two defconfig files for trusty supported ubootfaqiang.zhu
add below two defconfig files: configs/imx8qm_mek_android_trusty_defconfig configs/imx8qxp_mek_android_trusty_defconfig they are directly copied from below two files for the ease of tracking the modifications: configs/imx8qm_mek_android_defconfig configs/imx8qxp_mek_android_defconfig Change-Id: I84ca6ce62698b48bceb651df95ad61cf3e565e99 Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
2019-08-11MLK-22425 TMU: iMX8MN: Enable loading TASR and TCALIV from fuseYe Li
Like iMX8MM, iMX8MN also needs SW to load TMU TASR and TCALIV registers value from fuse before enabling TMU calibration. Otherwise the calibration is not exact. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2019-07-30MLK-22179-2 imx8mn_evk: Enable FSPI DQS loopback for high freqYe Li
There is an divider on imx8mn will always divide 2 to flexspi root clock. So actual SCLK output to device is 50Mhz on imx8mn not 100Mhz. After changing the root clock setting to configure SCLK to 100Mhz, found the read data is not correct. Must enable the internal DQS pad loopback to fix the problem. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-30MLK-22179-1 fsl_fspi: Add a config to enable dummy DQS loopback from padYe Li
Set MCR0 RXCLKSRC to 1 to enable DQS loopback from pad to support higher frequency. Signed-off-by: Ye Li <ye.li@nxp.com>
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