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* Add CONFIG_SYSTEM_RAMDISK_SUPPORT to support system's ramdisk
* Normal boot: cmdline to bypass ramdisk in boot.img,
but use Recovery boot: Use the ramdisk in boot.img
* commandline is larger than 512, system can't bootup sometime for commandline issue.
* support fastboot getvar.
* Support "fastboot erase" command for emmc device.
TODO: uboot community have api to operate flash, we can unify this part
* support "fastboot flash" even on damaged gpt
Change-Id: I080c25d6569d6cab56ff025601cd3b8df21cf3dd
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Fix issue for API changed from v2017.
porting below patch from v2016.
commit 44834fd12f60a090e3d10ab6f84a75460894d49d
Change-Id: Ifaf0b86dd29648f9150646f00f54502676df9013
Signed-off-by: zhang sanshan <sanshan.zhang@nxp.com>
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Change the CONFIG_BOOTDELAY macro to 0 in defconfig to autoboot without delay.
Change-Id: Ie4f49325b0bac73eed6aafe59bf6a5ec584a4d43
Signed-off-by: Zhang Bo <bo.zhang@nxp.com>
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The USDHC uses default clock root OSC 25Mhz, this causes SD/eMMC reading
very slowly.
This patch changes the USDHC IP/BUS clock to 200Mhz.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Fix the build warning below:
arch/arm/cpu/armv8/imx8m/clock.c: In function ‘decode_frac_pll’:
arch/arm/cpu/armv8/imx8m/clock.c:37:36: warning: variable ‘pll_newdiv’
set but not used [-Wunused-but-set-variable]
u32 divr_val, divq_val, divf_val, pll_newdiv, divff, divfi;
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Got the build warning below due to the typo error. Fix it.
drivers/mmc/fsl_esdhc.c: In function ‘check_and_invalidate_dcache_range’:
drivers/mmc/fsl_esdhc.c:355:10: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
start = (unsigned)data->dest;
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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When compiling with android toolchain, there is an instruction
"str q0, [x8],#16", but x8 is not 16bytes aligned,
this instruction will trigger sync abort.
So, following Linux kernel, only use general regs for arm64.
If not, compiler may use simd registers Q[x]. We need to avoid
using simd registers in U-Boot, because load/store Q[x] has
restriction that 128bits aligned when str/ldr.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add i.MX8M EVK board support.
The drivers are not switched to use driver model now.
SPL is used to initialize DDR Controller and DDR PHY, then
load u-boot.img from SD to DRAM.
ATF and PHY FW bin are included.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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The MIB RAM and FIFO receive start register does not exist on
i.MX8M. Accessing these register will cause system hang.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Add ddr register memory map
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add i.MX8M GPIO support.
There are 4 GPIO banks on i.MX8M.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add ddr phy fw section in SPL link file.
Also when objcopy, do not ignore the firmware section.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Bind ATF with u-boot-nodtb.bin together.
Since now ATF's entry is 0x40001000, so when
generating u-boot.img, we use 0x40001000
as the load and entry address.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Include i.MX8M in lcdif register layout map.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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support i.MX8M in fsl esdhc driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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i.MX8M OCOTP follow same flow as i.MX6Q, but it has 64 banks
and each bank 4 words.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Build iomux/i2c/bootaux for i.MX8M.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add soc level initialization code.
Add arch_cpu_init.
Add M4 boot.
Add timer_init.
Add cpuinfo
Add dummy SoC ID.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Add clock driver to support i.MX8M.
There are two kind PLLs, FRAC PLL and SSCG PLL.
ROM code already configured SYS PLL1/PLL2, so we
just enabled all the output here.
The clock root is similar to i.MX7D, so have similar
code structure as i.MX7D. The clock_slice is mainly for
setting clock root.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add pin header file for i.MX8M.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add register definition header file for i.MX8M.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Add i.MX8M into Kconfig.
The architecture of i.MX8M is different to i.MX8QM/QXP, so
add a new folder for i.MX8M.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Request gpio before use it, otherwise it will fail to
drive the gpio when gpio_direction_output.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 31da76c496511b3d640ac1008b630b3ec939e168)
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Fix the SW2MODE setting problem in power_init_board, which causes issue when wakeup source
is set in kernel for LPSR.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
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without this patch, the QoS setting will be lost after exit LPSR mode.
The patch moves the QoS setting into DDR setting group (in plugin mode), thus
when exit LPSR mode, QoS setting will be restored as well as DDR setting.
Signed-off-by: Robby Cai <robby.cai@nxp.com>
(cherry picked from commit 0b217456375bace3fbe9a72c7e92a46dc1907277)
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Add back the defconfig to boot M4 in single mode, because some customers
are using the defconfig during development.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
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The u-boot limits the needed sections in .bin by set -j parameter
in objcopy. Need to add the firmware_image section for M4 image.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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The latest M4 image uses the version 0x41 not 0x40, have to update
it when checking M4 image. Otherwise M4 image won't be loaded.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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soc_type
Append androidboot.soc_type based on the imx soc type
Change-Id: I3ae18bff42b434eb77728a7db70dd3baf6d7e0a6
Signed-off-by: guoyin.chen <guoyin.chen@nxp.com>
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add configure for arm2 imx8qxp.
Change-Id: Ie123e9c342f920db4428d06a8ee580314edc70b8
Signed-off-by: sanshan zhang <sanshan.zhang@nxp.com>
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add is_recovery_key_pressing for imx8qxp.
Change-Id: I660c09e026250d9815ac4db38f17c674d49320ce
Signed-off-by: sanshan zhang <sanshan.zhang@nxp.com>
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To support HDMI display on EVK board, the LCDIF pix clock must be 25.2Mhz. Since
the its PCC divider range is from 1-8, the max rate of LCDIF PCC source clock is
201.6Mhz. This limits the source clock must from NIC1 bus clock or NIC1 clock, other sources
from APLL PFDs are higher than this max rate.
The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source is APLL PFD0, so we must
change the APLL PFD0 and have impact to DDRCLK, NIC1 and NIC1 bus.
Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz (25.2 * 12),
with settings:
PFD0 FRAC: 32
APLL MULT: 22
APLL NUM: 2
APLL DENOM: 5
Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 91be2789a93288cc087cd9e8db522c8308ef007c)
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The OTG ID pin mux setting is missed in DTS, so the OTG can't work
as host mode.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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It is for imx8qm and imx8qxp, and the cadence IP is in it.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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Enable USB3 configuration, only host mode is supported now.
And disable EHCI support at imx8qm_lpddr4_arm2_defconfig.
Currently, the EHCI and xHCI can't be enabled at the same time
due to below redefinition symbols:
drivers/usb/host/xhci.o: In function `submit_control_msg':
/home/b29397/work/projects/uboot-imx/drivers/usb/host/xhci.c:1032: multiple definition of `submit_control_msg'
drivers/usb/host/ehci-hcd.o:/home/b29397/work/projects/uboot-imx/drivers/usb/host/ehci-hcd.c:1517: first defined here
drivers/usb/host/xhci.o: In function `submit_bulk_msg':
/home/b29397/work/projects/uboot-imx/drivers/usb/host/xhci.c:1045: multiple definition of `submit_bulk_msg'
drivers/usb/host/ehci-hcd.o:/home/b29397/work/projects/uboot-imx/drivers/usb/host/ehci-hcd.c:1141: first defined here
drivers/usb/host/xhci.o: In function `submit_int_msg':
/home/b29397/work/projects/uboot-imx/drivers/usb/host/xhci.c:1053: multiple definition of `submit_int_msg'
drivers/usb/host/ehci-hcd.o:/home/b29397/work/projects/uboot-imx/drivers/usb/host/ehci-hcd.c:1523: first defined here
drivers/usb/host/xhci.o: In function `usb_lowlevel_init':
/home/b29397/work/projects/uboot-imx/drivers/usb/host/xhci.c:1063: multiple definition of `usb_lowlevel_init'
drivers/usb/host/ehci-hcd.o:/home/b29397/work/projects/uboot-imx/drivers/usb/host/ehci-hcd.c:1097: first defined here
drivers/usb/host/xhci.o: In function `usb_lowlevel_stop':
/home/b29397/work/projects/uboot-imx/drivers/usb/host/xhci.c:1102: multiple definition of `usb_lowlevel_stop'
drivers/usb/host/ehci-hcd.o:/home/b29397/work/projects/uboot-imx/drivers/usb/host/ehci-hcd.c:1092: first defined here
scripts/Makefile.build:359: recipe for target 'drivers/usb/host/built-in.o' failed
make[1]: *** [drivers/usb/host/built-in.o] Error 1
If the user wants to use EHCI for chipidea IP at imx8qm, please comment out
CONFIG_USB_XHCI_HCD
CONFIG_USB_XHCI_IMX
And define
CONFIG_USB_EHCI_HCD
CONFIG_DM_USB
at imx8qm_lpddr4_arm2_defconfig
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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It only supports USB3 power up sequence now.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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Add scratch buffer support which is missing at u-boot.
No sure if all USB3 IP is needed, but it should have
no affect for adding it.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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add configs for arm2-8qm.
Change-Id: Ief47e1587f6dbc4f16b243c29fa9bc9c8c80c044
Signed-off-by: sanshan zhang <sanshan.zhang@nxp.com>
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enable booti for imx8.
boot_addr_start for booti should be the addr of Image rather than
boot.img, so need read Image into hdr->kernel_addr.
change the offset for bootloader.
booti do not call android_image_get_kernel to init android env.
booti can't load boot.img, so it can't init android env.
init android env through android_image_get_kernel.
Change-Id: Ifb990ee9c5710ce7bd5fa9a0d4221dcb0e52d341
Signed-off-by: sanshan zhang <sanshan.zhang@nxp.com>
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add api get_board_serial and is_recovery_key_pressing for android.
1. read unique num from fuse through api sc_misc_otp_fuse_read exported
by sc firmware.
2. many register have not added in reg.h
set is_recovery_key_pressing into TODO list.
Change-Id: I2175e3a379d979ed473a4494695483dbf579bb2d
Signed-off-by: sanshan zhang <sanshan.zhang@nxp.com>
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Add board codes and configurations to enable USB DM driver (host and gadget)
for the USBOH(OTG) controller on i.MX8QM ARM2 board.
For device mode, the UMS (USB mass storage) is enabled at default.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add the usb alias for OTG1 in QM dtsi.
Add OTG1 power control and its GPIO regulator node.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add board codes and configurations to enable USB DM driver (host and gadget)
for the USBOH(OTG) controller on i.MX8QXP ARM2 board.
For device mode, the UMS (USB mass storage) is enabled at default.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add USB OTG, PHY relevant nodes and properties. Add its power control pin
to GPIO regulator.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add the otg power and clock settings functions. The USBOH clocks are
from Connectivity subsystem's internal bus clocks, which are enabled
at default, so no operation needed to enable them.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The i.MX8 has two USB controllers: USBOH and USB3. The USBOH reuses
previous i.MX6/7. It has same PHY IP as i.MX7ULP but NC registers
are same as i.MX7D. So add its support in ehci-mx6 driver.
Also the driver is updated to remove build warning for 64 bits CPU.
Signed-off-by: Ye Li <ye.li@nxp.com>
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replace fdt_addr with fdtaddr
Signed-off-by: Frank Li <Frank.Li@nxp.com>
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Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
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Add boot from usb support.
Follow same flow as i.mx6 chips.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add MFG ENV settings.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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