Age | Commit message (Collapse) | Author |
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Add ahab_sec_fuse_prog command to support burn secure fuse, for example
the system ROM patch. Before running the command, user needs to sign
the fuse container in format mentioned in ELE API and have loaded the
container to specified address passed to ahab_sec_fuse_prog
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
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After remove the optee memory bank, there is an 32MB hole.
So mem=1280MB should decrease to mem=1248MB.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Due to the errata ERR051067, the MIPI DSI power switch must be on for HIFI4.
ATF has set ALWAYS_ON flag to DSI PS as workaround, so we must enable it in
SPL, otherwise DSI PS can't be enabled by SCMI PD calling.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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The swton indicates the logic switch, magic number 0xfff80 is hard
to understand, so use macro.
Some board design may not have MIPI_CSI/DSI voltage input connected per
data sheet. In that case, the upower power on api may dead loop mu to wait
response, however there is no response. So remove MIPI_CSI/DSI here, let
linux power domain driver to runtime enable the power domain.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Per the datasheet, the VDD_SOC voltage can be set to typical
0.65V when system enter sys_sleep mode(PMIC_standby signal HIGH),
so add this support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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change the ddr saved info to the last 16KB of the OCRAM.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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As the ddr timing info will be saved at the last 16KB of
the OCRAM, spl stack & bss base should be updated to avoid
conflict.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Fix build break of issue "undefined reference to `dm_rng_read'" on
6UL and 6ULZ. which is introduced by commit 8789f3c
(PLATSEC-1781-2 MX6: Device tree fix-up)
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
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Since OPTEE memory will be protected by ATF to secure access only.
We need to remove it from u-boot DRAM banks and MMU table, then
the memory will not be used by both u-boot and kernel.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit c140827845b2ee1de2c2aa6f7df77d2825062996)
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Enable TMU sensor driver on iMX93 boards' defconfigs
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit de014b071446cd1479255549e37d81ef642626c0)
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Probe the TMU device and print CPU temperature in boot log
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 81c0d42a590abaffc9dc7bee570c5d14803d820b)
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Enable the TMU node, update calibration data and remove iMX8MQ
compatible string since the TMU revision is different and not compatble.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit f417c996eabe1727a9c190b0b5e3f3298591f2c7)
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The TMU used on iMX93 is IP revision 2.1 which is different with previous
revision used on iMX8MQ. So add a new FLAG V4 for this revision to
distinguish the operations.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 761ab8136adbb1201b1e72a1d9e915d3069ff5cf)
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Replace the codes with the new API to set max ARM clock. The API
will align the max clock with speed grading fuse.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 6f41fcc451448dc607d70314a45c6bb29f637fb3)
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Add a new API to set max ARM core clock that should be aligned
with speed grading.
For iMX93, the max speed is 1.7Ghz for Consumer and Auto, 1.5Ghz
for Industrial.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 318a1354e3392075b5be6db7bd0cd642027c8daf)
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Get the chip's market segment and speed grading from fuse and print
them in boot log like other i.MX series.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 1226b8cbd8da7b3e2520db9bac0197886725bec2)
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At present, in cgc1_pll3_init we don't set the pll3pfd div values,
just use the default 0. But when MROM-3029 is applied, ROM will set
PLL3 pfd1div2 to 1 and pfd2div1 to 3.
This finally causes some clocks' rate decreased, for example USDHC.
So clear the PLL3DIV_PFD dividers to get correct rate.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 91eb5a47b996b531c5fda5e421d35f54f486c548)
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Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode
access only for boot purpose. Since SW will reuse the SRAM0 as SCMI
buffer and SPL container loading buffer, need to reconfigure MRC3.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit ebfac7540de520b97724d3fd2d5918b4b56327b1)
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According to datasheet, iMX93 has fused parts with CORE1 or NPU or
both disabled.
Update the SOC codes to support such parts and disable/remove nodes
from kernel DTB for fused modules.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit d23f6cda69a572c42d9cc480787ad70a129d1a2e)
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Enable flexspi drivers and relevant configs to support FSPI NOR
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 0843cc8c9a508d2cf8be61e6f728c6e7b71c60ff)
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VPCIe_3V3 is used to supply the power to M.2 card, we must enable it
before using the flash.
The SD3_nRST is connected to reset pin of flash, must deassert
(pull up) it.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit de9747a36721c2bb19a3f5ac5c3da3e580c78010)
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Add the flexspi NOR node and its pinctrl setting to 9x9 QSB DTS to
support M.2 QSPI NOR card.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit e56a523df5372ab432a58a9f0383086cbec27ba0)
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Enable flexspi drivers and relevant configs to support FSPI NOR
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 2c61cee4236a5d50d076627d32b4e3ce484ead0f)
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VPCIe_3V3 is used to supply the power to M.2 card, we must enable it
before using the flash.
The SD3_nRST is connected to reset pin of flash, must deassert
(pull up) it.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit cbd24cd503366f7c657afbaab03b0c85610298e2)
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Enable the flexspi NOR in DTS, and correct the NOR flash and pinctrl
settings to adapt M.2 QSPI NOR board design which uses 4 I/O data pins.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 8f1cedf1ecc36622d310ba26b401ed0f5530dbe1)
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Update flexspi clocks relevant properties and add alias for flexspi
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 271d114e751814488cad885be17da313d8a9079d)
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i.MX8M[M,N,P] SRC not has 0x1004 offset register, so drop it.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 78d7ccda83f729d7f7b5f4b731a6d35764cdc402)
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Enable video config to support splash screen
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 919d29f2bd0264e84abed6b40d9363a7b24eb7d3)
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Update SoC dtsi to include parrel display fmt
Add lcdif pinmux
Add new board dts
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 947b648496737e4dddde3a93e3d21fefc7d9c401)
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Add 300MHz freq for lower video pll settings
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 03ccdbf58acf3333801afe110c8371819346fdbb)
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i.MX93 MediaMix GPR contains the display_mux register to control
parallel display format configuration. Add a video bridge driver for it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit c8084a583054d439314d0cf2b9fa957cd6eb3352)
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Default is active high, but some settings requires active low, so according to
timing flags to set mode sync.
If flags have DISPLAY_FLAGS_HSYNC_LOW and DISPLAY_FLAGS_VSYNC_LOW set,
mode.sync will clear FB_SYNC_HOR_HIGH_ACT and FB_SYNC_VERT_HIGH_ACT,
then INV_VS and INV_HS will be set to 1
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 6f225600790b201c6c6f45a2ec640daed8dfe310)
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DISPLAY_FLAGS_VSYNC_HIGH
To i.MX93/8MP, the VSYNC/HSYNC Polarities are high, so set
the timing flag: DISPLAY_FLAGS_HSYNC_HIGH & DISPLAY_FLAGS_VSYNC_HIGH
in check_timing callback.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 15eba93f742cb427a8808a05f9e800c1b2922f0e)
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Somes boards may default enable backlight and not able to set
brightness, so make it optional.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 928d56fcb5c540e5d8937473a74189a46f701ce3)
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The set_parent calls for the LVDS Pixel and Phy clock must be add. The
default parent from the System firmware may no longer be expected to be set
to "bypass".
Signed-off-by: Oliver F. Brown <oliver.brown@oss.nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit cb6d090fd2f4283a428d65f17ddc9fa1c08f8960)
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Add i.MX93 9x9 QSB board support, the left feature is splash screen for
now.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 7af2a3c29b05007f6e6a47990997ed415f3dad24)
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Merge in LFAC/uboot-nxp from ~NXF69319/uboot-nxp_kshitiz:imx_v2022.04_tmp to imx_v2022.04
* commit '8789f3ca3e400caa4c4acabfabf80b0441909bc6':
PLATSEC-1781-2 MX6: Device tree fix-up
PLATSEC-1781-1 mx6ull:Add config CONFIG_OF_SYSTEM_SETUP
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Merge in LFAC/uboot-nxp from ~NXF28159/uboot-nxp:dek_blob_8ulp to imx_v2022.04
* commit '9710cc4840e1d70ced569b41196ba31be01e9bbc':
LFOPTEE-177 imx93evk: enable cmd_dek command
LFOPTEE-177 imx8ulp: enable cmd_dek command
LFOPTEE-177 imx: cmd_dek: add ELE DEK Blob generation support
LFOPTEE-177 s400_api: add DEK Blob generation
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on A1 chip, when DBD_EN is fused and HAB closed, the TRDC was
owned by S400 and the ATF space (SSRAM) would be locked (RW only)
before HAB verify, which would cause boot hang if we don't enable
CONFIG_AHAB_BOOT by default.
This commit enables CONFIG_AHAB_BOOT by default, so the execution
permission on SSRAM would be added on HAB closed board.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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This commit fixes up the device tree with 16 byte randomly generated
(each) otp_crypto_key, otp_unique_key handles inside dcp
crypto node.
Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
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This commit enables CONFIG_OF_SYSTEM_SETUP for making modification to the
flat device tree before handing it off to the kernel. This causes
ft_system_setup() to be called before booting the kernel.
Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
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The usedata partition fs type is switched to be f2fs. Set it uboot for
the return result of "fastboot getvar" command, and the "fastboot format
userdata" can automatically format the userdata partition as f2fs.
For read-only partitions with android rootfs images, the fs type is
switched to be erofs. Althrough these partitions are dynamic partitions
which cannot be recognized by uboot, set their types still.
Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
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The OEM Secure World Closed is not a valid lifecycle on iMX8ULP/iMX9.
So remove it from lifecycle print.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Add start resets function to set the software reset (SWR) bit to
reset eQOS IP to sample the PHY interface select input signal.
On some platform like i.MX93, the HW reset to eQOS is completed early
before we set GPR for PHY interface. so the setting will not apply
to eQOS and cause issues.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
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In uboot_v2021.04, uboot uses the dts alias number as the devnum for mmc
device but SPL uses the blk_next_free_devnum, which is 0 for SD card on
i.MX8DXL DDR3l board since there is no eMMC. There is patch to set
the SD devnum to 0 for i.MX8DXL DDR3l only, refer to commit
f90218da095be1548e205c9fee270e3d92d28d09
But for uboot_v2022.04, both uboot and SPL use the dts alias number so
the devnum turns back to 1, remove the previous code for i.MX8DXL DDR3l
to align the devnum with uclass devnum.
Signed-off-by: Han Xu <han.xu@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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To resolve DCNANO underrun issue, change the DDR Port 0 arbitration
from round robin fashion to fixed priority level 1, while other ports
are not assigned any priority, so they will be serviced in round robin
fashion if there is no active request from Port 0.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
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To align with ATF's change, adjust DRAM timing save area to new
place 0x20055000. So we can release the old place 0x2006c000 for
ATF NOBITS region
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
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Need to add DRAM access permission for S400, as S400 needs to access
it When SPL calls image authentication
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Before moving the lifecycle to OEM closed, confirm the lifecycle is
OEM open, otherwise cancel to move forward the lifecycle.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Enable cmd_dek command for DEK Blob generation.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
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