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2022-08-01LFU-373 imx8ulp: upower: Do not send AFFB enable message for A1Ye Li
On A1 part, upower ROM will default enable AFFB for APD/AVD/RTD before power on domains. We don't need to send the AFFB enable message any more. Actually enabling the AFFB of APD should happen during power mode switch which needs put APD to hold mode. It is hard to implement for boot, so upower ROM's implementation is necessary and simple. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-08-01imx8ulp: clock: Fix lcd clock algoLoic Poulain
The div loop uses reassign and reuse parent_rate, which causes the parent rate reference to be wrong after the first loop, the resulting clock becomes incorrect for div != 1. Fixes: 829e06bf4175 ("imx8ulp: clock: Add MIPI DSI clock and DCNano clock") Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 85d0580e684c74dcb0a90aa0c010006cda40af44)
2022-07-31LFU-372-3 imx8ulp: Enable SCMI thermal for temperatureYe Li
Change from PMC thermal driver to SCMI thermal to get temperature, so that we can avoid TRDC access issue for PMC and ADC on RTD Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Alice Guo <alice.guo@nxp.com>
2022-07-31LFU-372-2 DTS: imx8ulp: Add SCMI sensor nodeYe Li
Add SCMI sensor node and enable pre-relocation for SCMI, so that we can use SCMI thermal driver at early phase of u-boot. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Alice Guo <alice.guo@nxp.com>
2022-07-31LFU-372-1 thermal: Add SCMI Sensor based thermal driverYe Li
Add SCMI Sensor protocol based thermal driver to get temperature from SCMI platform server. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Alice Guo <alice.guo@nxp.com>
2022-07-29LF-6692-4 imx8ulp_evk: Disable the PMC thermal driverYe Li
On DBD_EN fused part, the upower space is defined to secure access by TRDC. It is not good to open nonsecure access as the TRDC granularity is 64KB, so that whole upower peripheral space will be exposed. We disable the PMC thermal driver, and will switch to use SCMI sensor driver for thermal. This finally traps to ATF which calls the upower API to get the temperature. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2022-07-29LF-6692-3 imx8ulp: Adjust handshake to sync TRDC and XRDC completionYe Li
To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment. M33 will be the TRDC owner and needs to configure TRDC. A35 is the XRDC owner, ATF will configure XRDC. The handshake between U-boot and M33 image is used to sync TRDC and XRDC configuration completion. Once the handshake is done, A35 and M33 can access the allowed resources in others domain. The handshake is needed when M33 is booted or DBD_EN fused, because both cases will enable the TRDC. If handshake is timeout, the boot will panic. We use SIM GPR0 to pass the info from SPL to u-boot, as before the handshake, u-boot can't access SEC SIM and FSB. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2022-07-29LF-6692-2 imx8ulp: Remove the TRDC configure from A35Ye Li
As M33 is responsible for TRDC configuration, the settings for A35 nonsecure world access and DMA0 access are moved to M33 image. So remove the codes to release TRDC and configure it. Just keep the configurations for reference. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2022-07-29LF-6692-1 imx8ulp: xrdc: Fix DID0 access DDR in MRC4Ye Li
eDMA1 and USHDC0 access to DDR are controlled by MRC4, so must configure the MRC4 for DID0 Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2022-07-28LFU-370 imx8mq_evk: Disable LPDDR4 periodic trainingYe Li
There is a known issue on iMX8MQ called DDR FIFO shift issue reported by SNPS (STAR 9001102223 "uMCTL2 Sends MRR/MRW/ ZQCal Commands too Close to or during dfi_phymstr_ack == 1"). And it causes system unstable randomly on some boards. To workaround the issue, we have to disable DFI PHY Master interface entirely both in uMCTL2 and PHY. Since the PHY Master Interface is used in LPDDR4 to initiate the DRAM Drift Compensation operations. The PHY Master Interface uses internal timers to determine when the DRAM needs to be retrained. Then LPDDR4 periodic training is disabled. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Oliver Chen <oliver.chen@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2022-07-27MA-20473 imx8mp/imx8ulp: enable dual bootloader for some configsJi Luo
Switch to use dual bootloader for some configs. Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-07-26LFOPTEE-169 imx8ulp: s400: start the S400 RNG at bootClement Faure
On the imx8ulp A1 SoC, the S400 RNG needs to be manually started. Signed-off-by: Clement Faure <clement.faure@nxp.com>
2022-07-26MA-20464 imx8mp: move enet1 to domain 1Ji Luo
move the enet1 to mcu domain as mcu may use it. Change-Id: I65d42d37c97139cf51b00f541e6688e2a97cc624 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-07-20LFU-362 cpu: imx8_cpu: fix the mpidr checkPeng Fan
CID 22311217 (#1 of 1): Operands don't affect result (CONSTANT_EXPRESSION_RESULT) result_independent_of_operands: plat->mpidr == 18446744073709551615UL /* (ulong)-1 */ is always false regardless of the values of its operands. This occurs as the logical operand of if. The mpidr's type is u32, however dev_read_addr returns a value with type fdt_addr_t(phys_addr_t) which is 64bit long. So the check never fail. This patch we still keep mpidr as u32 type, because i.MX8 only has max two cluster, the higher 32bit will always be 0. Use a variable addr to do the check, if check pass, assign the lower 32 bit to plat->mpidr. Reported-by: Coverity Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-20LFU-363 mmc: fix deference before null checkPeng Fan
CID 21694568 (#1 of 1): Dereference before null check (REVERSE_INULL) check_after_deref: Null-checking m suggests that it may be null, but it has already been dereferenced on all paths leading to the check. Reported-by: Coverity Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-18LFU-332-10: configs: imx8mm: ab2 target board config optionsAdrian Alonso
Audio Board 2.0 target board configs for imx8m mini soms Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-332-9: include: configs: imx8mm ab2: board configsAdrian Alonso
Common config options for imx8m mini audio board 2 Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-332-8: dts: arm: imx8mm ab2: target board supportAdrian Alonso
Add device tree configs for audio board 2.0 for common imx8mm som modules Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-332-7: arm: mach imx8m: imx8mm ab2 target board configsAdrian Alonso
Add iMX8M Mini Audio board 2.0 target board configs Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-332-6: board: freescale: imx8mm ab2: target board supportAdrian Alonso
Audio Board 2.0 support for common imx8mm som lpddr4 som and ddr4 som Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-332-5: include: configs: imx8mn ab2: board configsAdrian Alonso
Common config options for imx8m nano audio board 2 Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-332-4: configs: imx8mn: ab2 target board config optionsAdrian Alonso
Audio Board 2.0 target board configs for imx8m nano soms Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-332-3: dts: arm: imx8mn ab2: target board supportAdrian Alonso
Add device tree configs for audio board 2.0 for common imx8mn som modules Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-332-2: arm: mach imx8m: imx8mn ab2 target board configsAdrian Alonso
Add iMX8M Nano Audio board 2.0 target board configs Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-332-1: board: freescale: imx8mn ab2: target supportAdrian Alonso
Audio Board 2.0 support for common imx8mn som lpddr4 som, ddr4 som and ddr3l som Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-333: drivers: clk: imx: fix clk register compositeAdrian Alonso
Fix clk composite dependency select COMPOSITE_CFF for CLK_IMX8MM Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18MLK-25979-3 imx8ulp: xrdc: Set MRC4/5 for access DDR from A35 and APD PERYe Li
iMX8ULP A1 S400 ROM will remove the setting for MRC4/5. So we have to set them in SPL to allow access to DDR from A35 and APD PER masters Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-18MLK-25979-2 imx8ulp: soc: Limit the eMMC ROM API workaround to A0.1 partYe Li
Since A1 ROM has fixed the ROM API eMMC issue, we should only use the workaround for A0.1 part. Add a SOC revision check. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-18MLK-25979-1 imx8ulp: soc: Get chip revision from SentinelYe Li
In both SPL and u-boot, after probing the S400 MU, get the chip revision, lifecycle and UID from Sentinel. Update get_cpu_rev to use the chip revision not hard coded it for A0 Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-18LF-6576 serial: lpuart: Fix LPUART FIFO_RXFE for all platformsYe Li
Have checked reference manuals of all platforms with LPUART. All of them should define FIFO_RXFE to 0x08. Remove the ARCH check, so for iMX8ULP and iMX93, we can have RX FIFO correctly enabled. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-18MLK-25974 tcpc: check if i2c_dev is NULL before dm_i2c_read/write operationXu Yang
When i2c device probe failed, port->i2c_dev will be NULL. Current tcpc driver lacks some checks before dm_i2c_* operations. Otherwise, the below error will be reporeted: Bus usb@4c100000: dev_get_parent_plat: null device. This patch adds and optimizes some check code. Reported-by: Clark Wang <xiaoning.wang@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-361-3 arm: dts: imx93: move usb i2c devices to i2c3Clark Wang
According to the board design change, move USB i2c devices to lpi2c3 bus. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-361-2 imx9: clock: correct i2c clock rootClark Wang
The root clock used in imx_get_i2cclk() is incorrect. Change it to LPI2C1_CLK_ROOT. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-361-1 imx93_evk: move all usb i2c device from bus 1 to bus 3Clark Wang
The board design has changed. All USB i2c devices has been moved to i2c3. So reconfig USB i2c devices i2c bus number settings here. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-11MA-20419 Move memory region rdc configure to TEEzhai.he
The widevine L1 need to support VP9 4K format video, and the size of secure heap is not enough for it, so need to expand the size of secure heap. The restrictions on the secure heap in the spl stage, and expnasion of secure heap may affect the use of memory in the uboot stage. In order to prevent affecting uboot from using secure heap range, the memory policy are not configured in the spl stage by default. Only widevine TA or confirmationUI TA is loaded, will configure it in TEE. Change-Id: Ib8f0a10b26e3900c66757f7a684270a061e62f46 Signed-off-by: zhai.he <zhai.he@nxp.com>
2022-07-11LF-6555 imx8m[m/n/p/q]_evk: add bootargs to support mcorePeng Fan
If wanna to use linux remoteproc to start Mcore, `run prepare_mcore`. It does not matter to add it if using U-Boot bootaux to start mcore. So this bootargs could be default added with U-Boot start or Linux start. Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-06MLK-25975 imx93: Update pinctrl header file in DTS and archYe Li
The DTS imx93-pinctrl.h in u-boot is not latest. It uses wrong select input registers offset. So update this file to align with kernel. We also update imx93_pins in arch to add SION for all i2c and i3c SCL/SDA Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2022-07-06LFU-360 net: phy: realtek: add support for RTL8821F(D)(I)-VD-CGClark Wang
RTL8821F(D)(I)-VD-CG is the pin-to-pin upgrade chip from RTL8821F(D)(I)-CG. Add new PHY ID for this chip. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25898 ddr: imx9: Add workaround for DDRPHY rank-to-rank errataYe Li
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2022-07-06MLK-25965-13 imx93_evk: Enable MIPI DSI splash screenYe Li
Enable MIPI DSI splash screen in defconfig, support both ADV7535 DSI to HDMI card and RM67199 DSI panel Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-12 DTS: imx93-11x11-evk: Add nodes for MIPI DSI displayYe Li
Add nodes for MIPI DSI RM67199 panel and adv7535 DSI to HDMI card Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-11 DTS: imx93: Update imx93 DTSi for mediamix nodesYe Li
Sync iMX93 SoC DTSi with kernel for adding and updating nodes in mediamix Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-10 imx9: clock: Add mxs_set_lcdclk API and Frac PLL rateYe Li
Implement the mxs_set_lcdclk to select video PLL frequency according to pixel clock rate and set MEDIA_DISP_PIX_CLK_ROOT accordingly Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-9 video: adv7535: Update compatible stringYe Li
Change the compatible string from 7533 to 7535 to align with kernel Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-8 video: imx: lcdifv3: Update LCDIFv3 driver for iMX93Ye Li
Add the compatible string for iMX93 and call check timing to DSI bridge device as the DSI driver needs to fixup HSYNC timing Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-7 video: dw_mipi_dsi: Update Designware MIPI DSI host driverYe Li
Update synopsys DW MIPI DSI host driver for iMX93 DSI controller 1. Fix wrong flag used for HSYNC and VSYNC polarity 2. Fix wrong timing parameters used for VSA, VBP, HSA, HBP and HLINE 3. Sync outvact_lpcmd_time setting with kernel 4. Sync to_clk_division setting with kernel 5. Add compatible string for iMX93 only Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-6 video: dw_dsi_imx: Add bridge driver for DW DSI on iMX93Ye Li
Add video bridge driver for iMX93 MIPI DSI. There is an DSI host driver existed for DW MIPI DSI controller. This bridge driver is used control both DPHY device and DSI host device. Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-5 video: bridge: Add check_timing interfaceYe Li
Add new interface check_timing to video bridge uclass. For bridge device who may update timing needs to implement the callback. So host device can sync the timing with the bridge. Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-4 video: rm67191: Update pixel clock rate to 121MhzYe Li
Follow kernel patch to change pixel clock rate to 121Mhz to resolve an stable issue that the panel display will get blurred and have no response to later display actions when read data from panel through DSI interface. Changing to 121MHz means decrease the frame rate from 60.02Hz to 55.02Hz. Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-3 phy: Add MIPI DSI PHY for iMX93Ye Li
Add MIPI DSI PHY driver for iMX93 to control DSI PLL in mediamix block control Signed-off-by: Ye Li <ye.li@nxp.com>
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