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2019-01-18musb-new: sunxi: Use CLK and RESET supportJagan Teki
Now clock and reset drivers are available for respective SoC's so use clk and reset ops on musb driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Marek Vasut <marex@denx.de>
2019-01-18reset: Add reset validJagan Teki
Add reset_valid to check whether given reset is valid or not. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18phy: sun4i-usb: Use CLK and RESET supportJagan Teki
Now clock and reset drivers are available for respective SoC's so use clk and reset ops on phy driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Marek Vasut <marex@denx.de>
2019-01-18arm: sunxi: Enable CLK, RESETJagan Teki
CLK and DM_RESET drivers are now available for all of the Allwinner platforms, so enable them in arch/arm/Kconfig Enabling CLK will select DM_RESET by default. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18sunxi: A64: Update sun50i-a64-ccu.hJagan Teki
Update sun50i-a64-ccu.h from the Linux sunxi/dt64-for-4.20 tree: commit 679294497be31596e1c9c61507746d72b6b05f26 Author: Rodrigo Exterckötter Tjäder <rodrigo@tjader.xyz> Date: Wed Sep 26 19:48:24 2018 +0000 arm64: dts: allwinner: a64: a64-olinuxino: set the PHY TX delay This should be a part of previous sync patch from commit 1b39a1834ed182bbd8036a5cd74a9ea111fa4691 Author: Andre Przywara <andre.przywara@arm.com> Date: Mon Oct 29 00:56:47 2018 +0000 sunxi: A64: Update .dts/.dtsi files Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18clk: sunxi: Add Allwinner A80 CLK driverJagan Teki
Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18ARM: dts: sun8i: Update A80 dts(i) from Linux-v4.18-rc3Jagan Teki
Update all A80 devicetree dtsi and dtsi files from Linux-v4.18-rc3 with below commits. arch/arm/boot/dts/sun9i-a80*: commit 190e3138f9577885691540dca59c2f07540bde04 Merge: cafc87023b0d a7affb13b271 Author: Arnd Bergmann <arnd@arndb.de> Date: Tue Mar 27 14:58:00 2018 +0200 Merge tag 'sunxi-h3-h5-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt include/dt-bindings/*/sun9i-a80-*: commit 783ab76ae553abc23f80ef7511052d055697531b Author: Chen-Yu Tsai <wens@csie.org> Date: Sat Jan 28 20:22:36 2017 +0800 clk: sunxi-ng: Add A80 Display Engine CCU Note: sun9i-a80-cx-a99.dts is updated only uart0, since the same dts is not available in Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18clk: sunxi: Add Allwinner H6 CLK driverJagan Teki
Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18clk: sunxi: Implement UART resetsJagan Teki
Implement UART resets for all relevant Allwinner SoC clock drivers via ccu reset table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18clk: sunxi: Implement UART clocksJagan Teki
Implement UART clocks for all Allwinner SoC clock drivers via ccu clock gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18clk: sunxi: Add Allwinner V3S CLK driverJagan Teki
Add initial clock driver for Allwinner V3S. - Implement USB bus and USB clocks via ccu_clk_gate table for V3S, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for V3S, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: sunxi: Add Allwinner R40 CLK driverJagan Teki
Add initial clock driver for Allwinner R40. - Implement USB bus and USB clocks via ccu_clk_gate for R40, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for R40, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: sunxi: Add Allwinner A83T CLK driverJagan Teki
Add initial clock driver for Allwinner A83T. - Implement USB bus and USB clocks via ccu_clk_gate table for A83T, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for A83T, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: sunxi: Add Allwinner A23/A33 CLK driverJagan Teki
Add initial clock driver for Allwinner A23/A33. - Implement USB bus and USB clocks via ccu_clk_gate table for A23/A33, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for A23/A33, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: sunxi: Add Allwinner A31 CLK driverJagan Teki
Add initial clock driver for Allwinner A31. - Implement USB ahb1 and USB clocks via ccu_clk_gate table for A31, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB ahb1 and USB resets via ccu_reset table for A31, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: sunxi: Add Allwinner A10s/A13 CLK driverJagan Teki
Add initial clock driver for Allwinner A10s/A13. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10s/A13, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10s/A13, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: sunxi: Add Allwinner A10/A20 CLK driverJagan Teki
Add initial clock driver for Allwinner A10/A20. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10/A20, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10/A20, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: sunxi: Add Allwinner H3/H5 CLK driverJagan Teki
Add initial clock driver for Allwinner H3/H5. - Implement USB bus and USB clocks via ccu_clk_gate table for H3/H5, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for H3/H5, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18reset: Add Allwinner RESET driverJagan Teki
Add common reset driver for all Allwinner SoC's. Since CLK and RESET share common DT compatible, it is CLK driver job is to bind the reset driver. So add CLK bind call on respective SoC driver by passing ccu map descriptor so-that reset deassert, deassert operations held based on ccu reset table defined from CLK driver. Select DM_RESET via CLK_SUNXI, this make hidden section of RESET since CLK and RESET share common DT compatible and code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: Add Allwinner A64 CLK driverJagan Teki
Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18board: sun50i-h5: Add Emlid Neutis N5 supportAleksandr Aleksandrov
Emlid Neutis N5 is a SoM based on Allwinner H5, has a WiFi & BT module, DDR3 RAM and eMMC. - add neutis-devboard target to dtb makefile - add dtsi file for Neutis N5 needs - add config file for Neutis N5 Dev board Signed-off-by: Aleksandr Aleksandrov <aleksandr.aleksandrov@emlid.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> [jagan: update proper commit head] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18sunxi: board: Add i2c initialization for sun50iStefan Mavrodiev
To use TWI0/1/2 the user can select CONFIG_I2C#_ENABLE. However even the controller is enabled, the mux for the pins are not set. This patch follows the existing mux method. Since the pads are different, separate check is added for each i2c. Tested with A64-SOM204 board. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-17Merge tag 'mips-pull-2019-11-16' of git://git.denx.de/u-boot-mipsTom Rini
- MIPS: mscc: various enhancements for Luton and Ocelot platforms - MIPS: mscc: added support for Jaguar2 platform - MIPS: optimised SPL linker script - MIPS: bcm6368: fix restart flow issues - MIPS: fixed CONFIG_OF_EMBED warnings for all MIPS boards - MIPS: mt7688: small fixes and enhancements - mmc: compile-out write support if disabled
2019-01-17Merge branch '2019-01-16-master-imports'Tom Rini
- Fixes for CVE-2018-18440 and CVE-2018-18439 - Patch to allow disabling unneeded NAND ECC layouts - Optimize SPI flash env read process
2019-01-16arm: bootm: fix sp detection at end of address rangeSimon Goldschmidt
This fixes 'arch_lmb_reserve()' for ARM that tries to detect in which DRAM bank 'sp' is in. This code failed if a bank was at the end of physical address range (i.e. size + length overflowed to 0). To fix this, calculate 'bank_end' as 'size + length - 1' so that such banks end at 0xffffffff, not 0. Fixes: 15751403b6 ("ARM: bootm: don't assume sp is in DRAM bank 0") Reported-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2019-01-16tftp: prevent overwriting reserved memorySimon Goldschmidt
This fixes CVE-2018-18439 ("insufficient boundary checks in network image boot") by using lmb to check for a valid range to store received blocks. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> [trini: Always build lib/lmb.o on LMB and lib/fdtdec.o on OF_LIBFDT] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-16lmb: remove unused extern declarationSimon Goldschmidt
lmb.h includes an extern declaration of "struct lmb lmb;" which is not used anywhere, so remove it. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-16bootm: use new common function lmb_init_and_reserveSimon Goldschmidt
This reduces duplicate code only. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-16fs: prevent overwriting reserved memorySimon Goldschmidt
This fixes CVE-2018-18440 ("insufficient boundary checks in filesystem image load") by using lmb to check the load size of a file against reserved memory addresses. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-16lib: lmb: extend lmb for checks at load timeSimon Goldschmidt
This adds two new functions, lmb_alloc_addr and lmb_get_unreserved_size. lmb_alloc_addr behaves like lmb_alloc, but it tries to allocate a pre-specified address range. Unlike lmb_reserve, this address range must be inside one of the memory ranges that has been set up with lmb_add. lmb_get_unreserved_size returns the number of bytes that can be used up to the next reserved region or the end of valid ram. This can be 0 if the address passed is reserved. Added test for these new functions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-16fdt: parse "reserved-memory" for memory reservationSimon Goldschmidt
boot_fdt_add_mem_rsv_regions() adds reserved memory sections to an lmb struct. Currently, it only parses regions described by /memreserve/ entries. Extend this to the more commonly used scheme of the "reserved-memory" node. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-16lib: lmb: reserving overlapping regions should failSimon Goldschmidt
lmb_add_region handles overlapping regions wrong: instead of merging or rejecting to add a new reserved region that overlaps an existing one, it just adds the new region. Since internally the same function is used for lmb_alloc, change lmb_add_region to reject overlapping regions. Also, to keep reserved memory correct after 'free', reserved entries created by allocating memory must not set their size to a multiple of alignment but to the original size. This ensures the reserved region is completely removed when the caller calls 'lmb_free', as this one takes the same size as passed to 'lmb_alloc' etc. Add test to assert this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-16lmb: fix allocation at end of address rangeSimon Goldschmidt
The lmb code fails if base + size of RAM overflows to zero. Fix this by calculating end as 'base + size - 1' instead of 'base + size' where appropriate. Added tests to assert this is fixed. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-16test: add test for lib/lmb.cSimon Goldschmidt
Add basic tests for the lmb memory allocation code used to reserve and allocate memory during boot. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-16env: add spi_flash_read_env functionHoratiu Vultur
The spi_flash_read_env function is a wrapper over spi_flash_read, which enables the env to read multiple flash page size from flash until '\0\0' is read or the end of env partition is reached. Instead of reading the entire env size. When it reads '\0\0', it stops reading further the env and assumes that the rest of env is '\0'. This is an optimization for large environments that contain few bytes environment variables. In this case it doesn't need to read the entire environment and only few pages. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16mtd: nand: raw: allow to disable unneeded ECC layoutsStefan Agner
Each ECC layout consumes about 2984 bytes in the .data section. Allow to disable the default ECC layouts if a driver is known to provide its own ECC layout. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-01-16mips: mt7688: gardena-smart-gateway: Enable green power LED on startupStefan Roese
Set the correct power-up state (default-state) of the green power LED. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16mips: mt7688: gardena-smart-gateway: Update mtdparts/mtdids for Kernel 4.19Stefan Roese
With the new SPI NOR framework in v4.19, we need to adapt the MTD parts so that the kernel cmdline parameter "mtdparts=" uses the correct naming for the devices. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16MIPS: bmips: switch to CONFIG_OF_SEPARATEDaniel Schwierzeck
Fix the Kconfig warning to not use CONFIG_OF_EMBED in defconfigs. Based on https://patchwork.ozlabs.org/patch/1019791/ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16MIPS: xilfpga: switch to CONFIG_OF_SEPARATEDaniel Schwierzeck
Fix the Kconfig warning to not use CONFIG_OF_EMBED in defconfigs. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16MIPS: pic32mzdask: switch to CONFIG_OF_SEPARATEDaniel Schwierzeck
Fix the Kconfig warning to not use CONFIG_OF_EMBED in defconfigs. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16MIPS: malta: switch to CONFIG_OF_SEPARATEDaniel Schwierzeck
Fix the Kconfig warning to not use CONFIG_OF_EMBED in defconfigs. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16MIPS: boston: switch to CONFIG_OF_SEPARATEDaniel Schwierzeck
Fix the Kconfig warning to not use CONFIG_OF_EMBED in defconfigs. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16MSCC: Add board support for Jaguar2 SOC familyHoratiu Vultur
Add board support and configuration for Jaguar2 SOC family. The detection of the board type in this family is based on the phy ids. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16MSCC: add device tree for Serval2 boardHoratiu Vultur
Add device tree based on evaluation board pcb112. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16MSCC: Add device tree for Jaguar2-48 boardHoratiu Vultur
Add device tree based on evaluation board pcb111. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16MSCC: Add device tree for Jaguar2 boardHoratiu Vultur
Add device tree based on evaluation board pcb110. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16MSCC: Add support for Jaguar2 SOC familyHoratiu Vultur
As the Ocelot and Luton SoCs, this family of SoCs are found in Microsemi Switches solution. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16pinctrl: mscc: Add gpio and pinctrl for Jaguar2 SOC familyHoratiu Vultur
The Jaguar2 SOC family has 63 gpio pins therefore I extended mscc-common to support new numbe of pins and remove any platform dependency from mscc-common. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.cLars Povlsen
With the new mscc_bb_spi.c driver, there is no longer use for the gpio-mscc-bitbang-spi.c driver. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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