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2019-04-12board: ti: am335x: Add platdata for cpsw in SPLFaiz Abbas
The SPL image overflows when cpsw dt nodes are added and SPL_OF_CONTROL is enabled. Use static platdata instead to save space. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12net: ti: cpsw: Enable DM_FLAG_PRE_RELOCFaiz Abbas
Add DM_FLAG_PRE_RELOC to make the driver probe in SPL. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12net: ti: cpsw: Block off ofdata_to_platdata with OF_CONTROLFaiz Abbas
The ofdata_to_platdata function should not be called if OF_CONTROL is not enabled because fdtdec_* calls will fail. Block the function with OF_CONTROL Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12net: ti: cpsw-common: Isolate getting syscon address from assigning macidFaiz Abbas
ti_cm_get_macid() is used to get a syscon node from the dt, read the efuse address and then assign the macid read from the address. Divide these two steps into separate functions one of which can be called from ofdata_to_platdata() while the other can be called from _probe(). This ensures that platdata can be assigned statically in a board file when OF_CONTROL is not enabled. Also add a macid_sel_compat in private data to get information about the macid byte placement. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12net: ti: cpsw: Convert cpsw_platform_data to a pointer in cpsw_privFaiz Abbas
Convert cpsw_platform_data to a pointer in cpsw_priv. Allocate it dynamically and assign it as a part of eth_pdata. This helps in isolating platform data handling and implementing platdata for SPL in a board file. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12net: ti: cpsw: Move cpsw_phy_sel() to _probe()Faiz Abbas
cpsw_phy_sel() is a configuration step that should not be in ofdata_to_platdata(). Add phy_sel_compat to the cpsw_platform_data structure so that it is accessible in _probe. Then move the call of cpsw_phy_sel() to _probe. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12net: Add priv_pdata to eth_pdataFaiz Abbas
Add a priv member for eth_pdata for platform specific platform data. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12armv7R: K3: am654: Trigger panic on DDR init failuresAndreas Dannenberg
When initializing DDR from R5 SPL trigger U-Boot's panic facility rather than simply returning from the board init function as there is little point continuing code execution. Further, as panic implies a board reset, so using it might potentially allow to recover from this error in certain cases such as when the init failure was caused by a temporary glitch of some sorts. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12configs: am65x_evm_a53: Enable CONFIG_OF_BOARD_SETUPLokesh Vutla
Enable CONFIG_OF_BOARD_SETUP so that msmc sram dt nodes are updated correctly. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12board: ti: am65x: Enable fixing up msmc sram nodeLokesh Vutla
Create a ft_board_setup() api that gets called as part of DT fixup before jumping to kernel. In this ft_board_setup() call fdt_fixup_msmc_ram that update msmc sram node. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12arm: k3: Add support for updating msmc dt nodeLokesh Vutla
Certain parts of msmc sram can be used by DMSC or can be marked as L3 cache. Since the available size can vary, changing DT every time the size varies might be painful. So, query this information using TISCI cmd and fixup the DT for kernel. Fixing up DT does the following: - Create a sram node if not available - update the reg property with available size - update ranges property - loop through available sub nodes and delete it if: - mentioned size is out if available range - subnode represents l3 cache or dmsc usage. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12arm: k3: Add a wrapper to get tisci handleLokesh Vutla
Create a wrapper to get the ti sci handle. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12firmware: Add support for querying msmc memoryLokesh Vutla
DMSC can use certain amount of msmc memory available in the system. Also certain part of msmc memory can be marked as L3 cache using board config. But users might not know what size is being used and the remaining available msmc memory. In order to fix this TISCI protocol provides a messages that can query the available msmc memory in the system. Add support for this message. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12configs: ti_omap5_common: Add NAND environment settingsFaiz Abbas
Now that NAND is supported on DRA71x include various NAND environment settings Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-12configs: dra71x-evm: Add Support for NANDFaiz Abbas
Add NAND support to dra71x-evm defconfig Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12arm: dra7: Allow NAND to be enabled on DRA71x EVM.Franklin S Cooper Jr
If SW 8 pins 0 and 1 indicate that NAND should be enabled then the pins pinmux must be reconfigured for NAND mode. Therefore, enable NAND by reconfiguring the pinmux. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12board: ti: dra71: Add pinmux settings for NAND on DRA71x EVMFranklin S Cooper Jr
By default VOUT3 occupies the pins required for NAND. Therefore, create a seperate entry that can be use to reconfigure these pins to work for NAND. On the EVM SWITCH 8 pins 0 and 1 will be used to determine if NAND is enabled or not. For NAND to be selected pin 0 should be on and pin 1 should be off. Any other combination will assume NAND shouldn't be enabled. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12ARM: davinci: da850evm: Enable SPL_OF_CONTROL without PLATDATAAdam Ford
With the memory mapping giving us some more avialable RAM, this updates the da850-evm-u-boot.dtsi to include the serial port, SPI and Flash nodes along with some dependent nodes in the SPL dtb. This also removes the platform data initialization code for the serial port and SPI Flash. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-04-12davinci: da850evm/omapl138-lcdk: Move BSS to SDRAM because SRAM is fullAdam Ford
In order to fully support SPL_OF_CONTROL, we need BSS to be a bit larger. This patch relocates BSS to SDRAM instead of SRAM which is similar to how ARMv7 boards (like OMAP2+) do it. This means two new variables are required: CONFIG_SPL_BSS_START_ADDR set to DAVINCI_DDR_EMIF_DATA_BASE CONFIG_SPL_BSS_MAX_SIZE is set to 0x1080000 which is 1 byte before the location where U-Boot will load. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-04-12am335x, guardian: Add support for the bosch guardian boardSjoerd Simons
Add support for the Bosch Guardian board. CPU : AM335X-GP rev 2.1 Model: Bosch AM335x Guardian I2C: ready DRAM: 256 MiB NAND: 512 MiB MMC: OMAP SD/MMC: 0 Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Felix Brack <fb@ltec.ch>
2019-04-12env: Don't check CONFIG_ENV_OFFSET_REDUND for SPL buildMartyn Welch
When booting using an SPL on am335x, if we want to support booting with the boot ROM loader via USB (which uses RNDIS, making bootp and tftp calls) we need to enable gadget eth in the SPL to load the main U-Boot image. To enable CONFIG_SPL_ETH_SUPPORT, we must enable CONFIG_SPL_ENV_SUPPORT as the environment is used by the eth support, but we don't actually need to have environment variables saved in the SPL environment. We do however have environment variables saved in the main U-Boot image and enable CONFIG_ENV_OFFSET_REDUND (we are storing in raw NAND). In such instances, even with the build config enabling both CONFIG_CMD_SAVEENV and CONFIG_CMD_NAND, these options aren't set when building the SPL, but CONFIG_ENV_OFFSET_REDUND still is. Don't check this configuration option for SPL builds to enable the above configuration. Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-12Add support for the MT41K128M16JT125K memory modulesSjoerd Simons
Add configuration for the MT41K128M16JT125K memory modules as used on the Bosch Guardian device. Based on a patch by: Govindaraji Sivanantham <Govindaraji.Sivanantham@in.bosch.com> Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> [checkpatch.pl cleanup by Martyn Welch] Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2019-04-12am57xx_evm_defconfig: Enable configs to support QSPI bootVignesh R
AM57xx IDK EVMs can boot out of QSPI. Enable configs to support QSPI boot. Also enable configs for updating QSPI boot images over DFU. Tested on AM572x IDK EVM. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-12ARM: dts: k2g-ice: add dt node for netcpMurali Karicheri
This patch adds dt node for DP83867 phy used on K2G ICE board and also enable netcp device nodes for the board. EVM hardware spec recommends to add 0.25 nsec delay in the tx direction and 2.25 nsec delay in the rx direction for internal delay in the clock path to be on the safer side. The board straps RX_DV/RX_CTRL pin of on board DP83867 phy in mode 1. Unfortunately, the phy data manual disallows this. Add ti,dp83867-rxctrl-strap-quirk in the phy node to allow software to enable workaround suggested for this incorrect strap setting. This ensures proper operation of this PHY. The dts bindings are kept in sync with that from 4.14.y linux kernel. This required the pinmux device related bindings to be commented out to allow for compilation. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-12k2g: config enable ti phy dp83867 for k2gMurali Karicheri
Enable ti phy dp83867 for k2g Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-12ARM: dts: k2g-evm: remove unused phy-mode property from phy nodeMurali Karicheri
This patch removes the unused phy-mode property from the phy dt node. On K2G, currently link-interface determines if phy is used or not and is already set to use rgmii. So this is not needed. Besides phy-mode should be added to slave interface configuration of the cpsw driver, not in the phy node. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-12ARM: k2g: add a workaround to reset the phyMurali Karicheri
This patch adds a workaround to reset the phy one time during boot using GPIO0 pin 10 to make sure, the Phy latches the configuration from the input pins correctly. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-12net: netcp: add support for phy with rgmii idsMurali Karicheri
Enhance the netcp driver to support phys that can be configured for internal delay (rgmii-id, rgmii-rxid, rgmii-txid) Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-12ARM: k2g-gp-evm: update to rgmii pinmux configurationMurali Karicheri
This patch updates pinmux configuration for K2G GP EVM based on data generated by the pinmux tool at https://dev.ti.com/pinmux/app.html#/default Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12ARM: k2g-ice: Add pinmux support for rgmii interfaceMurali Karicheri
This add pinmux configuration for rgmii interface so that network driver can be supported on K2G ICE boards. The pinmux configurations for this are generated using the pinmux tool at https://dev.ti.com/pinmux/app.html#/default As this required some BUFFER_CLASS definitions, same is re-used from the linux defnitions in include/dt-bindings/pinctrl/keystone.h Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-11configs: am65x_evm_a53: Enable DMA related configsGrygorii Strashko
Enable TI K3 AM65x PSI-L, Ring Accelerator and UDMA drivers Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-11arm64: dts: ti: k3-am65: add mcu navss nodesGrygorii Strashko
Add DT node for MCU NAVSS its components to get DMA working on AM654 SoC. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-11soc: keystone: Merge into ti specific directoryVignesh R
Merge drivers/soc/keystone/ into drivers/soc/ti/ and convert CONFIG_TI_KEYSTONE_SERDES into Kconfig. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-11dma: ti: add driver to K3 UDMAVignesh R
The UDMA-P is intended to perform similar (but significantly upgraded) functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P module supports the transmission and reception of various packet types. The UDMA-P also supports acting as both a UTC and UDMA-C for its internal channels. Channels in the UDMA-P can be configured to be either Packet-Based or Third-Party channels on a channel by channel basis. The initial driver supports: - MEM_TO_MEM (TR mode) - DEV_TO_MEM (Packet mode) - MEM_TO_DEV (Packet mode) Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
2019-04-11soc: ti: k3: add CPPI5 description and helpersGrygorii Strashko
Add TI Communications Port Programming Interface (CPPI) 5 interface description and helpers Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-11soc: ti: k3: add navss ringacc driverGrygorii Strashko
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs. The RINGACC converts constant-address read and write accesses to equivalent read or write accesses to a circular data structure in memory. The RINGACC eliminates the need for each DMA controller which needs to access ring elements from having to know the current state of the ring (base address, current offset). The DMA controller performs a read or write access to a specific address range (which maps to the source interface on the RINGACC) and the RINGACC replaces the address for the transaction with a new address which corresponds to the head or tail element of the ring (head for reads, tail for writes). Since the RINGACC maintains the state, multiple DMA controllers or channels are allowed to coherently share the same rings as applicable. The RINGACC is able to place data which is destined towards software into cached memory directly. Supported ring modes: - Ring Mode - Messaging Mode - Credentials Mode - Queue Manager Mode TI-SCI integration: Texas Instrument's System Control Interface (TI-SCI) Message Protocol now has control over Ringacc module resources management (RM) and Rings configuration. The Ringacc driver manages Rings allocation by itself now and requests TI-SCI firmware to allocate and configure specific Rings only. It's done this way because, Linux driver implements two stage Rings allocation and configuration (allocate ring and configure ring) while TI-SCI Message Protocol supports only one combined operation (allocate+configure). Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
2019-04-11firmware: ti_sci: Add support for NAVSS resource managementGrygorii Strashko
Texas Instruments' System Control Interface (TI-SCI) Message Protocol abstracts management of NAVSS resources, like PSI-L pairing and unpairing, UDMAP tx/rx/flow configuration and Rings. This patch adds support for requesting and configuring such resources from TI-SCI firmware. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
2019-04-11Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
2019-04-11Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Various rmobile fixes
2019-04-10Merge branch '2019-04-09-master-imports-fs'Tom Rini
- test.py tests for mmc - ext4 symlink support and other fixes - ext4 block group descriptor sizing
2019-04-10test.py: Disable fsck for FAT tests for nowTom Rini
Currently enabling fsck on FAT16/FAT32 exposes that we have problems with: TestFsBasic.test_fs13[fat16] TestFsBasic.test_fs11[fat32] TestFsBasic.test_fs12[fat32] TestFsBasic.test_fs13[fat32] TestFsExt.test_fs_ext1[fat32] TestFsExt.test_fs_ext2[fat32] TestFsExt.test_fs_ext3[fat32] TestFsExt.test_fs_ext4[fat32] TestFsExt.test_fs_ext5[fat32] TestFsExt.test_fs_ext6[fat32] TestFsExt.test_fs_ext7[fat32] TestFsExt.test_fs_ext8[fat32] TestFsExt.test_fs_ext9[fat32] TestMkdir.test_mkdir6[fat16] TestMkdir.test_mkdir1[fat32] TestMkdir.test_mkdir2[fat32] TestMkdir.test_mkdir3[fat32] TestMkdir.test_mkdir4[fat32] TestMkdir.test_mkdir5[fat32] TestMkdir.test_mkdir6[fat32] TestUnlink.test_unlink1[fat16] TestUnlink.test_unlink2[fat16] TestUnlink.test_unlink3[fat16] TestUnlink.test_unlink4[fat16] TestUnlink.test_unlink5[fat16] TestUnlink.test_unlink6[fat16] TestUnlink.test_unlink7[fat16] TestUnlink.test_unlink1[fat32] TestUnlink.test_unlink2[fat32] TestUnlink.test_unlink3[fat32] TestUnlink.test_unlink4[fat32] TestUnlink.test_unlink5[fat32] TestUnlink.test_unlink6[fat32] TestUnlink.test_unlink7[fat32] This is because we don't update the "information sector" on FAT32. While in the future we should resolve this problem and include that feature, we should enable fsck for ext4 to ensure that things remain in good shape there. Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-09Fix ext4 block group descriptor sizingBenjamin Lim
Ext4 allows for arbitrarily sized block group descriptors when 64-bit addressing is enabled, which was previously not properly supported. This patch dynamically allocates a chunk of memory of the correct size. Signed-off-by: Benjamin Lim <jarsp.ctf@gmail.com>
2019-04-09test/py: mmc: Add 'mmc read' performance checkMarek Vasut
Add option to the mmc rd test to check the duration of the execution of the mmc read command. This allows intercepting read performance regressions. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-09test/py: mmc: Add 'mmc info' testMarek Vasut
Add test for 'mmc info' subcommand. This tests whether the card information is obtained correctly and verifies the device, bus speed, bus mode and bus width. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-09test/py: mmc: Add 'mmc rescan' testMarek Vasut
Add test for 'mmc rescan' subcommand. This tests whether the system can switch to a specific card and then rescan the card. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-09test/py: mmc: Add 'mmc dev' testMarek Vasut
Add separate test for 'mmc dev' subcommand. This tests whether the system can switch to a specific card. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-09test/py: mmc: Factor out device selectionMarek Vasut
Factor out the 'mmc dev' call so it can be recycled by other tests. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-09fs: fat: fix reading non-cluster-aligned root directoryAnssi Hannula
A FAT12/FAT16 root directory location is specified by a sector offset and it might not start at a cluster boundary. It also resides before the data area (before cluster 2). However, the current code assumes that the root directory is located at a beginning of a cluster, causing no files to be found if that is not the case. Since the FAT12/FAT16 root directory is located before the data area and is not aligned to clusters, using unsigned cluster numbers to refer to the root directory does not work well (the "cluster number" may be negative, and even allowing it be signed would not make it properly aligned). Modify the code to not use the normal cluster numbering when referring to the root directory of FAT12/FAT16 and instead use a cluster-sized offsets counted from the root directory start sector. This is a relatively common case as at least the filesystem formatter on Win7 seems to create such filesystems by default on 2GB USB sticks when "FAT" is selected (cluster size 64 sectors, rootdir size 32 sectors, rootdir starts at half a cluster before cluster 2). dosfstools mkfs.vfat does not seem to create affected filesystems. Signed-off-by: Anssi Hannula <anssi.hannula@bitwise.fi> Reviewed-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Tested-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
2019-04-09fs: ext4: Problem with ext4load and sparse filesGero Schumacher
Hi, when I try to load a sparse file via ext4load, I am getting the error message 'invalid extent' After a deeper look in the code, it seems to be an issue in the function ext4fs_get_extent_block in fs/ext4/ext4_common.c: The file starts with 1k of zeros. The blocksize is 1024. So the first extend block contains the following information: eh_entries: 1 eh_depth: 1 ei_block 1 When the upper layer (ext4fs_read_file) asks for fileblock 0, we are running in the 'invalid extent' error message. For me it seems, that the code is not prepared for handling a sparse block at the beginning of the file. The following change, solved my problem: I am really not an expert in ext4 filesystems. Can somebody please have a look at this issue and give me a feedback, if I am totally wrong or not?
2019-04-09test: fs: Added tests for symlinksJean-Jacques Hiblot
Test cases are: 1) basic link creation, verify it can be followed 2) chained links, verify it can be followed 3) replace exiting file a with a link, and a link with a link. verify it can be followed 4) create a broken link, verify it can't be followed Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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