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2012-08-08powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNsTimur Tabi
The SET_PCI_LIODN() macro takes a compatible property string as a parameter, so that it knows which PCI device tree node to look for. The calls to these macros are using a hard-coded string, but we already have the CONFIG_SYS_FSL_PCIE_COMPAT macro which contains the same string, so we should use that. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08powerpc/mpc85xx: Ignore E bit for BSC9130/1York Sun
Commit 48f6a5c34 removed E bit. BSC9130/1 were left out due to patch apply timing. Remove them now. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08powerpc/sgmii: To support PHY link state auto detect in SGMII modeHongtao Jia
PHYs on SGMII riser card are used in SGMII mode with different external IRQs from eTSEC. This means in SGMII mode phy-handle and phy-connection-type under ethernet node should be updated. Otherwise the PHY interrupt can not be handled therefor PHY link state change can not be auto detected. For we have seperate SGMII PHY nodes, ethernet PHY reg fixup is not needed but it's still be kept to guarantee the sgmii mode could work with old device tree. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08powerpc/85xx: improve definition of BR_PHYS_ADDR macroTimur Tabi
The BR_PHYS_ADDR(x) macro was missing parentheses around "x" in the macro definition, so callers had to supply their own parenthesis. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08powerpc/p2041: configure the CPLD lane_mux according to RCWShaohui Xie
Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg is 0xc, CPLD supports SATA by default, we should re-configure the lane muxing according to RCW, which indicates what SerDes protocol it is running. Default lane muxing map is as below: Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg; Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg; Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2 and bit 3 respectively. Default value of these bits for lane muxing is '1', we should set or clear these bits accoring to RCW. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08powerpc/ddr: fix fsl_ddr_get_dimm_params compile errorShaohui Xie
fsl_ddr_get_dimm_params() should be wrapped by CONFIG_SYS_DDR_RAW_TIMING, otherwise, when using fixed_sdram() instead of using SPD, it will cause compile error. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08powerpc/corenet: fix compile error when CONFIG_SYS_NO_FLASH is definedShaohui Xie
ENV location compile logic is wrong, and when CONFIG_SYS_NO_FLASH is defined and non-NOR u-boot is building, it will cause compile error. Also, add CONFIG_SYS_FLASH_USE_BUFFER_WRITE for p2041, which will improve NOR flash write performance. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GBYork Sun
The fix for errata workaround is to avoid covering physical address 0xff000000 to 0xffffffff during the implementation. Early commit eb672e92 works until DDR size exceeds 4GB. This fix works for DDR size up to 64GB. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08powerpc/p1022ds: fix DIU/LBC switching with NAND enabledTimur Tabi
In order for indirect mode on the PIXIS to work properly, both chip selects need to be set to GPCM mode, otherwise writes to the chip select base addresses will not actually post to the local bus -- they'll go to the NAND controller instead. Therefore, we need to set BR0 and BR1 to GPCM mode before switching to indirect mode. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08powerpc/p1022ds: add support for SPI and SD bootMatthew McClintock
Add TLB mappings, board target options, and configuration items need for SPI/SD boot. Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit address flash, therefore, when SDHC/ESPI booting and access to eLBC, the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to 00b for them. Configure the PX_BRDCFG0[0~1] to 10b which is connected to SPI devices as SPI_CS(0:3)_B. Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-07-31powerpc/82xx: adapt SDRAM settings for mgcoge3neGerlando Falauto
The HW guys suggested to change these two values. And these values are now identical to the values we use on mgcoge. PSDMR_WRC was set to 1C as it should lead to better performance. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
2012-07-31powerpc/82xx: use SDRAM detection for mgcoge2neGerlando Falauto
mgcoge2ne was an intermediate step towards mgcoge3ne. One difference is the smaller SDRAM on mgcoge2ne (128MB). To support both boards with the same u-boot we use here the SDRAM detection. This patch enables SDRAM detection between 256MB and 128MB. So in addition to the existing 256MB geometry: 4 chips x 8M (13 rows, 10 cols) x 16 bit x 4 banks we can now also have 128MB geometry: 4 chips x 4M (13 rows, 9 cols) x 16 bit x 4 banks Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
2012-07-31powerpc/82xx: add SDRAM detection for km82xxGerlando Falauto
This patch adds SDRAM detection feature to km82xx boards. To enable this feature, define CONFIG_SYS_SDRAM_LIST as the initializer for an array of struct sdram_conf_s. These structs will expose the bitfields within registers PSDMR and OR1 which have to be different between configurations; common bitfields will be defined, as usual, within CONFIG_SYS_PSDMR and CONFIG_SYS_OR1. If CONFIG_SYS_SDRAM_LIST is not defined, then the usual behavior is retained. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
2012-07-31powerpc/82xx: move km/km82xx-common.h within km82xx.hGerlando Falauto
The only file including km82xx-common.h is km82xx.h. So there is no need to have it as a separate file. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
2012-07-31powerpc/82xx: merge mgcoge.h and mgcoge3ne.h into km82xx.hGerlando Falauto
Since mgcoge and mgcoge3ne are the only km82xx boards, there is no need to keep them as separate .h config files. Therefore, make mgcoge3ne.h and mgcoge.h converge into a single km82xx.h file. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
2012-07-31powerpc/82xx: move mgcoge, mgcoge3ne defines to ease subsequent mergeGerlando Falauto
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
2012-07-31powerpc/82xx: remove unused define for mgcoge3neHolger Brunck
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
2012-07-31SMDK6400: Add MAINTAINERS entryZhong Hongbo
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
2012-07-31Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk
* 'master' of git://git.denx.de/u-boot-i2c: km/common: remove printfs for i2c deblocking code CONFIG: SMDK5250: I2C: Enable I2C I2C: Add support for Multi channel I2C: Modify the I2C driver for EXYNOS5 I2C: Move struct s3c24x0_i2c to a common place. EXYNOS: PINMUX: Add pinmux support for I2C EXYNOS5: define EXYNOS5_I2C_SPACING EXYNOS: Add I2C base address. EXYNOS: CLK: Add i2c clock mx6qsabrelite: add i2c multi-bus support imx-common: add i2c.c for bus recovery support i.mx53: add definition for I2C3_BASE_ADDR i.mx: iomux-v3.c: move to imx-common directory i.mx: iomux-v3.h: move to imx-common include directory iomux-v3: remove include of mx6x_pins.h mxc_i2c: finish adding CONFIG_I2C_MULTI_BUS support mxc_i2c: add bus recovery support mxc_i2c: prep work for multiple busses support mxc_i2c: add i2c_regs argument to i2c_imx_stop mxc_i2c: add retries mxc_i2c: check for arbitration lost mxc_i2c: change slave addr if conflicts with destination. mxc_i2c: don't disable controller after every transaction mxc_i2c: place i2c_reset code inline mxc_i2c: place imx_start code inline mxc_i2c: remove redundant read mxc_i2c: combine i2c_imx_bus_busy and i2c_imx_trx_complete into wait_for_sr_state mxc_i2c.c: code i2c_probe as a 0 length i2c_write mxc_i2c: call i2c_imx_stop on error in i2c_read/i2c_write mxc_i2c: create i2c_init_transfer mxc_i2c: clear i2sr before waiting for bit mxc_i2c: create tx_byte function mxc_i2c: remove ifdef of CONFIG_HARD_I2C mxc_i2c: fix i2c_imx_stop i2c: deblock i2c bus also if accessed before realocation Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-31Merge branch 'master' of git://git.denx.de/u-boot-microblazeWolfgang Denk
* 'master' of git://git.denx.de/u-boot-microblaze: microblaze: Wire up SPI driver spi: microblaze: Adds driver for Xilinx SPI controller microblaze: intc: Clear interrupt code microblaze: Call serial multi initialization microblaze: Move __udelay implementation microblaze: Remove extern from board.c microblaze: Wire up dts configuration fdt: Add board specific dts inclusion microblaze: Move individual board linker scripts to common script in cpu tree. microblaze: Add gpio.h microblaze: Add missing undefs for UBI and UBIFS microblaze: Expand and correct configuration comments microblaze: Enable ubi support microblaze: Avoid compile error on systems without cfi flash microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTION Conflicts: drivers/spi/Makefile Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-31km/common: remove printfs for i2c deblocking codeHolger Brunck
This code will also be used before reallocation and during this time we are not allowed to do these printings. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Prafulla Wadaskar <Prafulla@marvell.com> Acked-by: Heiko Schocher <hs@denx.de>
2012-07-31CONFIG: SMDK5250: I2C: Enable I2CRajeshwari Shinde
This enables I2C support on smdk5250. Pinmux setting moved to board file to avoid repeated setting of gpio lines. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31I2C: Add support for Multi channelRajeshwari Shinde
This adds multiple i2c channel support for I2C. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31I2C: Modify the I2C driver for EXYNOS5Rajeshwari Shinde
This patch modifies the S3C I2C driver to suppport EXYNOS5. The cahnges made to driver are as follows: - I2C base address is passed as a parameter to many functions to avoid multiple #ifdef - Channel initialisation is moved to a commom funation as it is required by i2c_init. - Hardcoding for I2CCON_ACKGEN removed. - Replaced printf with debug. - Checkpatch issues resolved. - Pinmux setting will be done in board/samsung/smdk5250/smdk5250.c to avoid repeated setting of gpio lines, as it have multi bus support. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31I2C: Move struct s3c24x0_i2c to a common place.Rajeshwari Shinde
struct s3c24x0_i2c is being moved to common local header file so that the same can be used by s3c series and exynos series SoCs. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31EXYNOS: PINMUX: Add pinmux support for I2CRajeshwari Shinde
This patch adds pinmux code for I2C. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31EXYNOS5: define EXYNOS5_I2C_SPACINGRajeshwari Shinde
This patch defined EXYNOS5_I2C_SPACING used to calculate I2C channel base address. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31EXYNOS: Add I2C base address.Rajeshwari Shinde
This patch adds the base address for I2C. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31EXYNOS: CLK: Add i2c clockRajeshwari Shinde
This adds i2c clock information for EXYNOS5. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31mx6qsabrelite: add i2c multi-bus supportTroy Kisky
This includes bus recovery support. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Jason Liu <r64343@freescale.com>
2012-07-31imx-common: add i2c.c for bus recovery supportTroy Kisky
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31i.mx53: add definition for I2C3_BASE_ADDRTroy Kisky
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31i.mx: iomux-v3.c: move to imx-common directoryTroy Kisky
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31i.mx: iomux-v3.h: move to imx-common include directoryTroy Kisky
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31iomux-v3: remove include of mx6x_pins.hTroy Kisky
This include is not needed. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Jason Liu <r64343@freescale.com>
2012-07-31mxc_i2c: finish adding CONFIG_I2C_MULTI_BUS supportTroy Kisky
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31mxc_i2c: add bus recovery supportTroy Kisky
Add support for calling a function that will toggle the SCL line to return the bus to idle condition. The actual toggling function is added in a later patch. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31mxc_i2c: prep work for multiple busses supportTroy Kisky
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31mxc_i2c: add i2c_regs argument to i2c_imx_stopTroy Kisky
This is prep work for CONFIG_I2C_MULTI_BUS. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
2012-07-31mxc_i2c: add retriesTroy Kisky
Retry unexpected hardware errors. This will not retry a received NAK. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31mxc_i2c: check for arbitration lostTroy Kisky
No need to continue waiting if arbitration lost. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
2012-07-31mxc_i2c: change slave addr if conflicts with destination.Troy Kisky
The i2c controller cannot be both master and slave in the same transaction. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31mxc_i2c: don't disable controller after every transactionTroy Kisky
This helps in a multiple bus master environment which is why I also added a wait for bus idle. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31mxc_i2c: place i2c_reset code inlineTroy Kisky
imx_reset is only referenced once so move to that location. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
2012-07-31mxc_i2c: place imx_start code inlineTroy Kisky
imx_start is only referenced once so move to that location. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
2012-07-31mxc_i2c: remove redundant readTroy Kisky
wait_for_sr_state returns i2sr on success so no need to read again. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
2012-07-31mxc_i2c: combine i2c_imx_bus_busy and i2c_imx_trx_complete into ↵Troy Kisky
wait_for_sr_state Not using udelay gives a more accurate timeout. The current implementation of udelay in imx-common does not seem to wait at all for a udelay(1). Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> ---- V2: Added WATCHDOG_RESET as suggested by Marek Vasut add error message when stop fails mxc_i2c: code i2c_probe as a 0 length i2c_write Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-31mxc_i2c.c: code i2c_probe as a 0 length i2c_writeTroy Kisky
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-31mxc_i2c: call i2c_imx_stop on error in i2c_read/i2c_writeTroy Kisky
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31mxc_i2c: create i2c_init_transferTroy Kisky
Initial code of i2c_read and i2c_write is identical, move to subroutine. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
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