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2011-12-05tegra: Add a clock rate parameter to clock_early_init()Simon Glass
Since PLLP can be set to two different values, make it a parameter to the function that sets up the PLLs. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: I81ccc1cc3356796793ec2dd4ab22ed7fbd52f01d Reviewed-on: https://gerrit.chromium.org/gerrit/12245 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-02Adjust pllx_set_rate to remove delayBernie Thompson
This is using the latest patch recommendation from Dilan at Nvidia, we adjust the ordering to clear bypass earlier and remove the delay. This patch was run successfully for over 2000 reboots. BUG=chrome-os-partner:6145 TEST=Manual Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Change-Id: I9ef2f12d5c8abae86791f50b0f5e0e5a4249d947 Reviewed-on: https://gerrit.chromium.org/gerrit/12385 Reviewed-by: Micah Catlin <micahc@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org>
2011-12-01tegra: Move tegra_get_chip_type() to ap20.cSimon Glass
This function is better off in architecture code than board code. This is quite an invasive change unfortunately. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: I17764b134c25b684666d2c0fae2d255ac80e61b1 Reviewed-on: https://gerrit.chromium.org/gerrit/12244 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Simon Glass <sjg@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-12-01tegra: Add PLLP clock setting to fdtSimon Glass
This adds a setting for the required PLLP clock frequency. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: I02ab35fcd496d4ac4cfa6b732fdd9a9b7eb2cc88 Reviewed-on: https://gerrit.chromium.org/gerrit/12242 Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-11-30fdt: Add function to read a clock rate from fdtSimon Glass
This reads the frequency of a named clock from the fdt. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: Ib35bf7ef749f51862644218b1015057ca4e25203 Reviewed-on: https://gerrit.chromium.org/gerrit/12243 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-11-29fdt: uart: fix uart clock freq override; broke x86 uartTom Warren
CONFIG_SYS_PLLP_BASE_IS_408MHZ is meant only for T30 builds. Don't override to 216MHZ if not Tegra3 && not 408MHZ BUG=chromium-os:23521 TEST=built Seaboard, Waluigi and tested Waluigi. x86 build in queue. Signed-off-by: Tom Warren <twarren@nvidia.com> Change-Id: If9517c473e76b8a1a49c6ff81891946cdb263a44 Reviewed-on: https://gerrit.chromium.org/gerrit/12219 Commit-Ready: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2011-11-29Changing implementation of pllx_set_rate() to reduce possibility of ↵Micah Catlin
intermittent hang Currently with 200uS delay after PLL for stability. BUG=chrome-os-partner:6145 TEST=None Originaly-Reviewed-on: https://gerrit.chromium.org/gerrit/11091 Originaly-Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Originaly-Tested-by: Bernie Thompson <bhthompson@chromium.org> Originaly-Commit-Ready: Katie Roberts-Hoffman <katierh@chromium.org> Originaly-Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org> Signed-off-by: Doug Anderson <dianders@chromium.org> Change-Id: Idcb95d4698ea856785be8a8232c08c89309af887 Reviewed-on: https://gerrit.chromium.org/gerrit/12158
2011-11-28arm: Tegra3: update T30 clock_and_reset controller supportTom Warren
Signed-off-by: Tom Warren <twarren@nvidia.com> BUG=chromium-os:21033 TEST=built Seaboard & Waluigi OK. Booted my Waluigi to cmd prompt OK. MMC, SPI and I2C still work fine, as does UART. More can be done at a later date to cleanup AP20.c for T30 (and rename/move it, since AP20 is a T2x name) and use new T30 V/W clock enables/resets/sources/etc. Change-Id: Ia3a86c519481fffde6926e1fece1dcf898d199c9 Reviewed-on: https://gerrit.chromium.org/gerrit/11911 Tested-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-11-22Add support for specifying an initrd with the zboot commandGabe Black
This change finishes plumbing the initrd support built into the zboot mechanism out to the command interface. It also fixes a bug in the command declaration where the kernel size could be passed as an optional second parameter but not enough arguments were allowed. BUG=chrome-os-partner:6715 TEST=Built and booted on a Lumpy with the U-Boot command line exposed. Used the Linux kernel in the system partition and the initramfs used for recovery to boot the system. Observed that the recovery scripts in the initramfs ran. The hardest part about implementing this change was testing because it took many attempts to build/find an initrd/initramfs and command line that would actually work. I'm confident the problems I had were from not knowing how to set up or use an initramfs properly, not from the U-Boot support itself. Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: Iccc5ff62e170e738dfb429a6b0ef9e27f0e7d8a9 Reviewed-on: https://gerrit.chromium.org/gerrit/12027 Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-11-22Revert "Remove NAND support to reduce code size"Simon Glass
This reverts commit fab63e9aacc49a3d224df47b6d0e23dc6b73de40. Change-Id: I4ce3622871374baa7da19263cbe38603b4f9e356 Reviewed-on: https://gerrit.chromium.org/gerrit/11943 Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-11-22Remove second-stage U-Boot from 2MB firmware imageSimon Glass
There is barely enough space for U-Boot in the 2MB SPI flash. We are moving to eMMC firmware anyway, so for now let's remove the second-stage U-Boot from the image. This only affects Seaboard, not Kaen. BUG=chromium-os:19724 TEST=emerge chromeos-bootimage on Seaboard Change-Id: I6e3cadc2521b473cbea4ebbfeea2606780392fdb Reviewed-on: https://gerrit.chromium.org/gerrit/11942 Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-11-22UPSTREAM: config.mk: use memoization in cc-option macro to speed up compilationDaniel Schwierzeck
Apply memoization to cc-option macro by caching the results of the gcc calls. This macro is called very often so using cached results leads to faster compilation times. This feature can be enabled by setting CACHE_CC_OPTIONS=y in the environment. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> (cherry picked from commit f5fd7cd17552daf41677f6aa1c9eef48055c98a8) Change-Id: I76d9d6ccab7ba2aefc1e63a5f5e16c8a7aeadef7 Reviewed-on: https://gerrit.chromium.org/gerrit/11807 Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-11-22UPSTREAM: Reduce build timesWolfgang Denk
U-Boot Makefiles contain a number of tests for compiler features etc. which so far are executed again and again. On some architectures (especially ARM) this results in a large number of calls to gcc. This patch makes sure to run such tests only once, thus largely reducing the number of "execve" system calls. Example: number of "execve" system calls for building the "P2020DS" (Power Architecture) and "qong" (ARM) boards, measured as: -> strace -f -e trace=execve -o /tmp/foo ./MAKEALL <board> -> grep execve /tmp/foo | wc -l Before: After: Reduction: ================================== P2020DS 20555 15205 -26% qong 31692 14490 -54% As a result, built times are significantly reduced, typically by 30...50%. Change-Id: I6e8c7c37cd13c56cb64d0a410514f2b9dc2d5adb Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Albert Aribaud <albert.aribaud@free.fr> cc: Graeme Russ <graeme.russ@gmail.com> cc: Mike Frysinger <vapier@gentoo.org> (cherry picked from commit 77d94d2d86c055f015734cc4cd972a5de30fc5a2) Reviewed-on: https://gerrit.chromium.org/gerrit/11806 Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-11-18Fix bug introduced by hardware-mapped SPISimon Glass
This was missed at the time. BUG=chrome-os-partner:6585, chromium-os:22528 TEST=build and boot on Kaen, see that it doesn't cold reboot now Change-Id: Ied4f08a5078312dbee4ae4b0715e5c02d55f159a Reviewed-on: https://gerrit.chromium.org/gerrit/11879 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2011-11-18Tidy up fdt_decode_alloc_region() to make alloc separateSimon Glass
Move the malloc() out of fdt_decode_alloc_region() and rename it accordingly. This makes the code somewhat cleaner and allows us to print a sensible error message. BUG=chromium-os:17062 TEST=build and boot on Kaen Change-Id: I8edc8809baa42578e74c5e42cf47494b31b774e7 Reviewed-on: https://gerrit.chromium.org/gerrit/11878 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-11-18arm: Tegra3: complete 408MHz PLLP initTom Warren
Signed-off-by: Tom Warren <twarren@nvidia.com> BUG=chromium-os:21033 TEST=Built and booted OK on my Waluigi. UART is OK, mmc, spi, i2c OK. Note that this is only valid with CONFIG_SYS_PLLP_BASE_IS_408MHZ. No affect on Tegra2. Seaboard builds fine, BTW. Change-Id: I05a367afd1e78a2170d7308a658ce64017850ca0 Reviewed-on: https://gerrit.chromium.org/gerrit/11811 Tested-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
2011-11-17Remove NAND support to reduce code sizeSimon Glass
Perhaps due to a toolchain change or the recent TFTP changes, U-Boot no longer fits in the space available. This removes NAND support to give us time to expand the space and/or fix the toolchain. TBR=U-Boot suddenly grew for no immediately obvious reason, quick fix. http://build.chromium.org/p/chromiumos/builders/tegra2%20seaboard%20full/builds/924/steps/cbuildbot/logs/stdio TEST=build U-Boot and see that it is about 40KB smaller. Change-Id: Iec02cc4da57cac7e79355714000f3e5d31c326c4 Reviewed-on: https://gerrit.chromium.org/gerrit/11895 Reviewed-by: Yasuhiro Matsuda <mazda@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-11-17UPSTREAM: net: tftpput: add tftpput commandSimon Glass
This adds the tftpput command to U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> (cherry picked from commit 2d46cf291eae29a42bb5ca3d280d2b136339686b) Change-Id: I7d0dc1fd78d9269ed932899cb1c301771ee24fbf Reviewed-on: https://gerrit.chromium.org/gerrit/11802 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-11-17BACKPORT: net: tftpput: implement tftp logicSimon Glass
This adds logic to tftp.c to implement the tftp 'put' command, and updates the README. (cherry-picked from 1fb7cd4) Change-Id: I01fc2ca4d974416083e913597791676bbd0934ae Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/11801
2011-11-17UPSTREAM: tftpput: add save_addr and save_size global variablesSimon Glass
We need something akin to load_addr to handle saving data. Signed-off-by: Simon Glass <sjg@chromium.org> (cherry picked from commit 1aec244acf9daf0d4dad80fe86b2c2b7404251d6) Change-Id: I56c586abb3e075f0ab422c833637a3160d7e2a5f Reviewed-on: https://gerrit.chromium.org/gerrit/11800 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-11-17BACKPORT: net: tftpput: Support selecting get/put for tftpSimon Glass
TftpStart should support starting either a get or a put. (cherry-picked from 58f317d) Change-Id: Ic221520a1c7cb00536a42d3ab531efbcaba35bf6 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/11799
2011-11-17UPSTREAM: net: tftpput: Factor out start, restart and next block functionsSimon Glass
This code is required for tftpput, so move it into separate functions. Signed-off-by: Simon Glass <sjg@chromium.org> (cherry picked from commit e4cde2f70d2377fdf484cbbc1729b188f81b8ec8) Change-Id: Ie0398e05b13ea56dea70b270a812fe6dbbbe4bb4 Reviewed-on: https://gerrit.chromium.org/gerrit/11798 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-11-17BACKPORT: net: tftpput: move common code into separate functionsSimon Glass
We want to show block markers on completion of get and put, so move this common code into separate functions. (cherry-picked from f5329bb) Change-Id: I579a0db0e088ecd947bdfbf3049ec94a930fbed6 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/11797
2011-11-17BACKPORT: net: tftpput: Rename TFTP to TFTPGETSimon Glass
This is a better name for this protocol. Also remove the typedef to keep checkpatch happy, and move zeroing of NetBootFileXferSize a little earlier since TFTPPUT will need to change this. (cherry-picked from e4bf0c5) Change-Id: I90d03045de0231553a693f7119bdcc67a908e3c9 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/11796
2011-11-17UPSTREAM: sf: winbond: Add support for the Winbond W25X40James Le Cuirot
The Winbond W25X40 is now being used in the IP02 (and possibly IP04). Tested and working on the actual device. (cherry picked from commit ad8e3bd65766f670007bc5ae7c19b64e69e3dceb) Change-Id: I0e395dc6c10086a330d2a32e8f7601afe1a1792d Reviewed-on: https://gerrit.chromium.org/gerrit/11864 Reviewed-by: Taylor Hutt <thutt@chromium.org> Tested-by: Taylor Hutt <thutt@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-11-17UPSTREAM: net: tftpput: Add support for receiving ICMP packetsSimon Glass
ICMP packets can tell you when there is no server at the other end. It is useful for tftp to figure this out, so that a quick error can be displayed, rather than pointlessly retrying. This adds an ICMP packet handler to the net interface. Signed-off-by: Simon Glass <sjg@chromium.org> (cherry picked from commit 4793ee6522f10a3d108de7e47adbcf5f15eb3f46) Change-Id: I02bbd41b3852b92b06210db160a06c62f5bf414f Reviewed-on: https://gerrit.chromium.org/gerrit/11795 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-11-17UPSTREAM: Put common autoload code into auto_load() functionSimon Glass
This is a small clean-up patch. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Eric Bénard <eric@eukrea.com> (cherry picked from commit 093498669e77597635a24f326f11efeab213d394) Change-Id: Ib052e50e7e520c9d5c8c5344e94a4404b2ba0d30 Reviewed-on: https://gerrit.chromium.org/gerrit/11793 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-11-17UPSTREAM: net: tftpput: Move ICMP code into its own functionSimon Glass
NetReceive() is a very long function with a lot of indent. Before adding code to the ICMP bit, split it out. Signed-off-by: Simon Glass <sjg@chromium.org> (cherry picked from commit 8f79bb17a4251ec096a7184d1eaf6f5dea3d2623) Change-Id: Ic5599c5c7eedc7f00fc5d5aecdd051418e5c2e40 Reviewed-on: https://gerrit.chromium.org/gerrit/11794 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-11-16BACKPORT: Add setenv_ulong() and setenv_addr()Simon Glass
It seems we put numbers and addresses into environment variables a lot. We should have some functions to do this. (cherry picked from commit d67f10c) Change-Id: I922e72a7db872f26774459a6dc074a80016ef904 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/11792 Reviewed-by: Doug Anderson <dianders@chromium.org>
2011-11-16UPSTREAM: Move simple_itoa to vsprintfSimon Glass
This function is generally useful and shouldn't hide away in hush. It has been moved as is. Signed-off-by: Simon Glass <sjg@chromium.org> (cherry picked from commit 3cce8a5496452285e1828984ad3945417205cfc3) Change-Id: I014f58e901e6b035b5eeb694c62e6e881a7b75c2 Reviewed-on: https://gerrit.chromium.org/gerrit/11791 Reviewed-by: Doug Anderson <dianders@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-11-16arm: Tegra3: fdt: add display (LCD/PWFM) values for Tegra3Tom Warren
Signed-off-by: Tom Warren <twarren@nvidia.com> BUG=none TEST=Built Waluigi AOK, ran OK to cmd prompt Change-Id: I18ad5386958f456bf9bc819de5affc4cb5bae267 Reviewed-on: https://gerrit.chromium.org/gerrit/11716 Reviewed-by: Tom Warren <twarren@nvidia.com> Tested-by: Tom Warren <twarren@nvidia.com> Commit-Ready: Doug Anderson <dianders@chromium.org>
2011-11-15arm: Tegra: make some header files common for Tegra3 LCD useTom Warren
Signed-off-by: Tom Warren <twarren@nvidia.com> BUG=none TEST=built Seaboard and Waluigi AOK Change-Id: Ia860abf5ef3af66b3a39d4c57192455986b7a4f4 Reviewed-on: https://gerrit.chromium.org/gerrit/11704 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com> Commit-Ready: Doug Anderson <dianders@chromium.org>
2011-11-15tegra: enable SPI on Cardhu and WaluigiChe-Liang Chiou
BUG=chromium-os:21033 TEST=run `sf erase, write` and `sf read` on Waluigi verify the data it reads from SPI flash matches that it writes to Change-Id: Ibeefd3183e4fa367d68d0035a818e1c166e6d59d Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/11473 Commit-Ready: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org>
2011-11-15tegra: spi: add SFLASH and SLINK driversChe-Liang Chiou
BUG=chromium-os:21033 TEST=run `sf erase, write` and then `sf read` on seaboard verify the data it reads from SPI flash matches that it writes to Change-Id: I1b04afa4b54738cd93be29b70f428bdc3e6b234f Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/11472 Commit-Ready: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org>
2011-11-15spi: add TEGRA_SLINK4_BASE and TEGRA_SPIFLASH_BASE in prep for tegra3Che-Liang Chiou
BUG=chromium-os:21033 TEST=emerge-{tegra2_seaboard,waluigi} chromeos-u-boot Change-Id: Icee2c26f36937e96c24318979179ba3a0cbfc09c Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/11597
2011-11-15arm: Tegra: power: make power.c/.h common for future Tegra3 LCD useTom Warren
Signed-off-by: Tom Warren <twarren@nvidia.com> BUG=none TEST=built Seaboard and Waluigi OK. Booted Waluigi OK. Change-Id: I1bfbe03945d7dae44e0840349b9698fc08cef07d Reviewed-on: https://gerrit.chromium.org/gerrit/11504 Tested-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
2011-11-15arm: Tegra: add new clocks for T30 LCDTom Warren
Signed-off-by: Tom Warren <twarren@nvidia.com> BUG=none TEST=build Seaboard and Waluigi AOK Change-Id: Id8e7227de7898bb9d117bf8d0f293ee5da7dc501 Reviewed-on: https://gerrit.chromium.org/gerrit/11506 Tested-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
2011-11-15arm: Tegra3: clear IO_RESET bit in pinmux registersTom Warren
Based on Tegra3 TRM, once E_18V bits in PMC are programmed, all IO_RESETs need to be cleared on LV blocks. If not, GPIO settings on related LV pins will always be set to low even if it is set to high. Specifically, it is observed that when IO_RESET bit is not cleared in VI_D4 pinmux register, the output of GPIO on VI_D4 (PL.02) is always low. That causes LVDS shutdown all the time. Also needed for SDMMC4 pins when booting from SPI. BUG=none TEST=built and booted on Waluigi, read/write SD/MMC data OK Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Change-Id: Iaf84dc39375a49ceb3284dd1d48a8af3a0145175 Reviewed-on: https://gerrit.chromium.org/gerrit/11495 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
2011-11-14arm: tegra2: change initial CPU clock to 312MhzYen Lin
Set CPU clock initially to 312Mhz; once CPU voltage is raised, CPU clock will then be raied to 1.2GHz (for T25) or 1.0GHz (for T20). BUG=chrome-os-partner:5914 TEST=Build and test on Seaboard Change-Id: I0c95a1df6b87c896daca8c03c9dc33b245764621 Reviewed-on: https://gerrit.chromium.org/gerrit/11199 Tested-by: Yen Lin <yelin@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Doug Anderson <dianders@chromium.org>
2011-11-14ICH SPI: Use an atomic preop for Write EnableDuncan Laurie
The U-boot spi interface uses Software Sequencing and handles write transactions in three distinct steps: 1) issue Write Enable op 2) issue Page Program op 3) poll Read Status Reg for completion However in an Intel 6-series chipset the Management Engine is also issuing a lot of transactions through the same controller to the same chip. It is possible for an ME transaction to occur between the U-boot issuing WREN and sending the actual data, resulting in the host WREN being lost and the data not actually being written to the chip. This change intercepts WREN opcode and instead applies it as a prefix operator for the next issued transaction, ensuring that the two are issued back-to-back to the SPI chip. Unfortunately this register is not writable when the SPI contoller is locked down, so it is not always applicable. BUG=chrome-os-partner:6690 TEST=repeated manual testing on lumpy with boot/suspend/resume Change-Id: I75e353942fd6148a93be561ff422e37dfc6dc8c4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/11625 Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2011-11-13spi: rename tegra2_spi to tegra_spi in prep for tegra3Che-Liang Chiou
BUG=chromium-os:21033 TEST=build seaboard successfully Change-Id: Idbfbdbf0bdb1070f4a2b5f8205c1caff6ef0c811 Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/11471 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-11-04Introduce ability to use hardware SPI mapping for read accesses.Vadim Bendebury
On X86 systems the hardware maps the bootprom SPI flash chip into the top of memory address range. This could be used for accessing all information in the SPI flash. The vboot-reference code requires access to FMAP sections containing cryptographic information, and as of today, u-boot reads the whole sections, which are 64 KB in size, even though the actual areas accessed by vboot-reference are much smaller. A much faster way of accessing this information would be just passing around pointers to the appropriate memory areas. This would eliminate one copy, and also would make sure that only the areas actually accessed get fetched from SPI flash. This patch provides this ability trying to keep code changes to a minimum. New feature is enabled by defining CONFIG_HARDWARE_MAPPED_SPI. The firmware storage API for file reads changes when the new configuration option is set: a pointer to pointer to buffer is passed to the read_spi() function instead of a pointer to buffer. When the new feature is enabled the read_spi() function sets the pointer value to point to the requested data instead of copying the data into the buffer. A new data type is introduced (read_buf_type), which is set to be a (void *) if the new feature is not enabled, or (void **) otherwise. This type is used as the buffer pointer in the spi_read() function. Code allocating/freeing buffers used to keep data read from SPI flash is now conditionally compiled. Call sites for the spi_read() function are modified to adjust the buffer pointer parameter (pass the address of the parameter instead of the parameter, when the new feature is enabled). gbb field access functions can be aliased to gbb_init(), as they all in fact do the same - read a certain section of the gbb area. This change does not benefit the ARM implementations, and makes the code more complicated that it should be. Some u-boot rearchitecture along with vboot_reference API enhancements could address this. A tracking issue (http://code.google.com/p/chromium-os/issues/detail?id=22528) has been opened for that. BUG=chrome-os-partner:6585, chromium-os:22528 TEST=manual . build a new stumpy firmware image . boot the stumpy, observe it start up chromeos. . assess the boot timing using the cbmem.py utility (this modification shaves in excess of 100ms off the boot time). . disable the new feature, build a stumpy image, observe that is still boots chromeOs. . run emerge-terga2_kaen chromeos-u-boot to confirem that ARM version builds cleanly. Change-Id: I4e6ab530d24f5771b5a86a48d3f3135101b469a6 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/11152
2011-11-03tegra3: Add pinmux settings (do not submit)Jimmy Zhang
This adds pinmux config settings for a generic T30 board. This is just an example - real code should do pinmux setting in the driver which is the only thing that can know what the settings should be. BUG=chromium-os:21033 TEST=build and boot on Seaboard, Waluigi Change-Id: Ia56fcfc55e6cce8ac8b75c31d0618182aaa16bf6 Reviewed-on: https://gerrit.chromium.org/gerrit/8705 Commit-Ready: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org>
2011-11-03CHROMIUM: config: Config options to allow us to boot a kernelDoug Anderson
With this set of config options we can now boot the kernel. With the kernel I have, it doesn't work yet, but at least it prints out some messages to the UART. BUG=chromium-os:21540 TEST=If I have a reasonable kernel in MMC1, I see that it can boot quite a ways into the kernel w/ autoboot. Change-Id: I5918fff3d48f2ff9f2bac9261c84e08e60a1560a Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/10675
2011-11-03Clean up MTRR 7 right before jumping to the kernelStefan Reinauer
This cleans up the rom caching optimization implemented in coreboot (and needed throughout u-boot runtime. Signed-off-by: Stefan Reinauer <reinauer@google.com> BUG=chrome-os-partner:6585 TEST=boot coreboot on stumpy Change-Id: I7242c9c2b0546c633be8fb8ebc815ed6e6fda4d1 Reviewed-on: https://gerrit.chromium.org/gerrit/11138 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2011-11-02Move Memset from vboot_reference to vbexport/u-bootStefan Reinauer
All memory operations (except the "safe ones") live in the firmware so the fast operations can be used. Except Memset. This CL changes that problem. There is another CL for this issue (removing the function from vboot_reference) BUG=chrome-os-partner:6313 TEST=run coreboot/u-boot on Stumpy Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ic2ee5970d2ee9df64a9eda261a4348341cb4b31a Reviewed-on: https://gerrit.chromium.org/gerrit/10992 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
2011-10-28CHROMIUM: waluigi: config: Turn on MMC for waluigi.Doug Anderson
BUG=chromium-os:21540 TEST=Able to use mmc. Change-Id: I1d566f08f9dd115b5be1a05ffa0ff07b508e0cee Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/10663
2011-10-28Remove generic MMC support from the coreboot configGabe Black
The MMC reader looks like a USB device, so we don't need to support generic MMC devices directly. BUG=chrome-os-partner:6585 TEST=Built and booted on Stumpy. Change-Id: Id5729cd9d51e0c4cb2570b9b452f96bd23764b85 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/10755 Commit-Ready: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-10-28Add a high level option to the coreboot config to control network supportGabe Black
We aren't currently planning to have network support in production firmware. If we need it at some point, we can easily turn that support back on. BUG=chrome-os-partner:6585 TEST=Built and booted on Stumpy Change-Id: Iad265bb2bbae5360135eaa8577cc6dfde95045f9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/10754 Commit-Ready: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-10-28Add a high level option to the coreboot config to control IDE supportGabe Black
Disable it by default since we're using the SCSI interface now. Being able to turn IDE back on later might be necessary if we haven't gotten AHCI support working on a new platform yet. BUG=chrome-os-partner:6585 TEST=Built and booted on Stumpy. Change-Id: I07e80dc2673529f3f2ec52431e1c0958511539b0 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/10753 Commit-Ready: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
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