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When gracefully stopping the controller, the driver was continuing if
*either* RX or TX had stopped. We need to wait for both, or the
controller could get into an invalid state.
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Fix that so we actually update the device tree PCI nodes on P1_P2_RDB boards.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Reset the eSDHC controller first before initialize the eSDHC controller.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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To boot from preformatted SD card this environment variable is added on P1 and P2 RDB
platforms.
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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Use the same code between primary and secondary cores to init the
L1 cache. We were not enabling cache parity on the secondary cores.
Also, reworked the L1 cache init code to match the e500mc L2 init code
that first invalidates the cache and locks. Than enables the cache and
makes sure its enabled before continuing.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Sandeep Gopalpet <Sandeep.Kumar@freescale.com>
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Signed-off-by: Li Yang <leoli@freescale.com>
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Manual CMD12 command can cause the protocol violations and cause read to hang,
therefore, the Auto CMD12 is used to avoid it.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
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The hardware may take longer to timeout, but it's much better than having
a too-short timeout value.
This patch is derived from P2020DS BSP Release.
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
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After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.
Therefore, the field 'clock' is assigned the initial clock speed 400000Hz.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
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This patch is derived from P2020DS BSP Release.
Signed-off-by: Jin Qing <B24347@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
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The current code use all the voltage range support by the host
controller to do the validation. This will cause problem when
the host supports Low Voltage Range. Change the validation
voltage to be based on board setup.
This patch is derived from P2020DS BSP Release.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
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Reverted 1.8v voltage selection for eSDHC from P1 and P2 config
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
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Use a slighly larger value of CLK_CTRL for DDR at 667MHz
which fixes random crashes while linux booting.
Applicable for both NAND and NOR boot.
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
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Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
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This patch checks the version number and revision number
from the pvr register and sets the HID1[mbdd] bit accordingly.
HID1[mbdd] is found on the new revisions of the e500 cores
which will optimize eieio instruction.
By setting this bit, a 10% improvement is seen in
applications like IP forwarding.
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
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This patch adds the 2nd USB (muxed with eLBC) node
depending upon enabling the 'usb2' environment variable
via hwconfig i.e. "setenv hwconfig usb2", so that linux
has the 2nd USB controller enabled, which will lead to
the disabling of the eLBC (NAND, NOR etc).
Also the 2nd USB controller has been left disabled in
the u-boot, otherwise any changes in the environment
won't be saved. Enabled agent mode support in USB2
depending upon "setenv hwconfig usb2:dr_mode=peripheral"
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Harninder Rai <harninder.rai@freescale.com>
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Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
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Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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- P2020 Rev 2.0 eSDHC PIO support no longer needed.
- P2020 Rev 2.0 has same issue of eSDHC can't operate at 1.8v
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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On Rev 1.0 of P1022 and P1020 eSDHC controller can't work at 1.8v.
To remove the capability of the controller, this work around has
added to unset the 1.8v field in Host capabilities register.
Signed-off-by: Huang Changming <R66093@freescale.com>
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In a manner similar to passing stashing parameters into device tree
for "gianfar", extend the support to the new "fsl,etsec2" as well.
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
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Signed-off-by: Maneesh Gupta <maneesh.gupta@freescale.com>
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Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
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This patch adds the 2nd USB (muxed with eLBC) node
depending upon enabling the 'usb2' environment variable
via hwconfig i.e. 'setenv hwconfig usb2', so that linux
has the 2nd USB controller enabled, which will lead to
the disabling of the eLBC (NAND, NOR etc).
Also the 2nd USB controller has been left disabled in
the u-boot, otherwise any changes in the environment
won't be saved.
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
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Modified the default othbootargs to include the cache-sram-size
parameter.This parameter is needed as the L2 as SRAM is ON by
default in the P2020RDB kernel and used by the Gianfar driver.
And also modified nandboot uImage and dts partition offsets.
Signed-off-by: Rajesh Gumasta <Rajesh.Gumasta@freescale.com>
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To use,
tftp 11000000 u-boot.bin,
go 1107f000
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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Both the save env and load env operation will call this function
to get the address of env on the SDCard, so the user can control
where to put the env freely.
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
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Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
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If the environment variables are saved on the MMC/SD card,
env_relocat can't relocate env from MMC/SD card without mmc init.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
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Enable environment support for eSDHC/eSPI boot on P1 and P2 RDB platforms.
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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Take advantage of the latest full relocation commit of PPC platform
for boot from NAND.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
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1. Modified the tsec_mdio structure to include the new regs
2. Modified the MDIO_BASE_ADDR so that it will handle both
older version and new version of etsec.
Signed-off-by: Sandeep Kumar <Sandeep.Kumar@freescale.com>
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Moved the mdio regs out of the tsec structure,and
provided different offsets for tsec base and mdio
base so that provision for etsec2.0 can be provided.
This patch helps in providing the support for etsec2.0
In etsec2.0, the MDIO register space and the etsec reg
space are different.
Also, moved the TSEC_BASE_ADDR and MDIO_BASE_ADDR definitons into
platform specific files.
Signed-off-by: Sandeep Kumar <Sandeep.Kumar@freescale.com>
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This patch enables the eSPI configuration to use
the Spansion Flash on P1 and P2 RDB Platforms
This also enables the Intel Pro/1000 PT Gb Ethernet
PCI-E Network Adapter configuration support
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
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This patch has been borrowed from MPC8536DS SPI Support.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
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DDR support to boot from NAND/eSDHC/eSPI on P1 & P2 RDB platforms.
Specifically, this support is needed when
L2 Cache size is less than 512K.
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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This is a workaround for the hardware bug found on the P2020 Rev 1.0.
The DCR[DMA__AHB2MAG_IRQ_BYPASS]is not set automatically upon SoC reset.
This patch sets the bit.
Signed-off-by: Vishnu Suresh <Vishnu@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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On P1 and P2 RDB Platforms, read the I2C EEPROM to
get various board switch settings like NOR Flash
Bank selection, SD Data width etc.
Depending on,
switch SW5[6] - select width for eSDHC
ON - 4-bit [Enable eSPI]
OFF - 8-bit [Disable eSPI]
switch SW4[8] - NOR Flash Bank selection for Booting
OFF - Primary Bank
ON - Secondary Bank
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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On some Freescale SoCs, internal DMA of eSDHC controller has
a bug. Hence, CPU Programmed I/O mode has been introduced
for data transfer.
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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The gd->cpu pointer is set to an address located in flash when the
probecpu() function is called while U-Boot is executing from flash.
This pointer needs to be updated to point to an address in RAM after
relocation has occurred otherwise Linux may not be able to boot due to
"fdt board" crashing if flash has been erased or changed.
This bug was introduced in commit
a0e2066f392782730f0398095e583c87812d97f2.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Reported-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Tested-by: Kumar Gala <galak@kernel.crashing.org>
Tested on MPC8527DS.
Tested by: Ed Swarthout <Ed.Swarthout@freescale.com>
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Neither the MVBLUE nor its underlying architecture implement the
do_irqinfo() function which is required when CONFIG_CMD_IRQ is defined.
This change fixes the following MVBLUE compiler error:
-> ./MAKEALL MVBLUE
Configuring for MVBLUE board...
common/libcommon.a(cmd_irq.o):(.u_boot_cmd+0x24): undefined reference to `do_irqinfo'
make: *** [u-boot] Error 1
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
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The support for this was silently dropped by a configuration
split during the merge of the imx27lite board support in commit
864aa034f3a0e10ce710e8bbda171df3cab59414 (cmd_mtdparts: Move to common
handling of FLASH devices via MTD layer).
Signed-off-by: Detlev Zundel <dzu@denx.de>
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Currently, the last block of NAND devices can't be accessed. This patch
fixes this issue by correcting the boundary checking (off-by-one error).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
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Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR,
and LCRR bitfields) moved the LCRR assignment to after relocation
to RAM because of the potential problem with changing the local bus
clock while executing from flash.
This change unfortunately adversely affects the boot time, as running
all code up to cpu_init_r can cause significant slowdown.
E.G. on a 8347 board a bootup time increase of ~600ms has been observed:
0.020 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
0.168 RS: 232
0.172 I2C: ready
0.176 DRAM: 64 MB
1.236 FLASH: 32 MB
Versus:
0.016 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
0.092 RS: 232
0.092 I2C: ready
0.096 DRAM: 64 MB
0.644 FLASH: 32 MB
So far no boards have needed the late LCRR setup, so simply revert it
for now - If it is needed at a later time, those boards can either do
their own final LCRR setup in board code (E.G. in board_early_init_r),
or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do
the setup in cpu_init_r.
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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We are using generic implementation of ffs. This should
be part of Simon's commit 0413cfecea350000eab5e591a0965c3e3ee0ff00
Here is warning message which this patch removes.
In file included from /tmp/u-boot-microblaze/include/common.h:38,
from cmd_mtdparts.c:87:
/tmp/u-boot-microblaze/include/linux/bitops.h:123:1: warning: "ffs" redefined
In file included from /tmp/u-boot-microblaze/include/linux/bitops.h:110,
from /tmp/u-boot-microblaze/include/common.h:38,
from cmd_mtdparts.c:87:
/tmp/u-boot-microblaze/include/asm/bitops.h:269:1:
warning: this is the location of the previous definition
Signed-off-by: Michal Simek <monstr@monstr.eu>
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A typo caused the stack and malloc regions to overlap, which prevented
mem_malloc_init() from returning. This commit makes the memory layout match
the example described in include/configs/microblaze-generic.h
Signed-off-by: Graeme Smecher <graeme.smecher@mail.mcgill.ca>
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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