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CONFIG_SOC_AU1X00
Common Alchemy Au1x00 stuff. All Alchemy processor based machines
need to have this config as a system type specifier.
CONFIG_SOC_AU1000, CONFIG_SOC_AU1100, CONFIG_SOC_AU1200,
CONFIG_SOC_AU1500, CONFIG_SOC_AU1550
Machine type specifiers. Each port should have one of aboves.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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- Fix traditional KSEG names
- Replace PHYSADDR with CPHYSADDR
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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- Kill redundant `-pipe' (this will be added by $(TOPDIR)/config.mk)
- Modify comments
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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MIPS port has two problems in timer routines. One is now we assume CFG_HZ
equals to CP0 counter frequency, but this is wrong. CFG_HZ has to be 1000
in the U-Boot system.
The other is we don't have a proper time management counter like timestamp
other ARCHs have. We need the 32-bit millisecond clock counter.
This patch introduces timestamp and CYCLES_PER_JIFFY. timestamp is a
32-bit non-overflowing CFG_HZ counter, and CYCLES_PER_JIFFY is the number
of calculated CP0 counter cycles in a CFG_HZ.
STRATEGY:
* Fix improper CFG_HZ value to have 1000
* Use CFG_MIPS_TIMER_FREQ for timer counter frequency, instead.
* timer_init: initialize timestamp and set up the first timer expiration.
Note that we don't need to initialize CP0 count/compare registers here
as they have been already zeroed out on the system reset. Leave them as
they are.
* get_timer: calculate how many timestamps have been passed, then return
base-relative timestamp. Make sure we can easily count missed timestamps
regardless of CP0 count/compare value.
* get_ticks: return the current timestamp, that is get_timer(0).
Most parts are from good old Linux v2.6.16 kernel.
v2:
- Remove FIXME comments as they turned out to be trivial.
- Use CP0 compare register as a global variable for expirelo.
- Kill a global variable 'cycles_per_jiffy'. Use #define CYCLES_PER_JIFFY
instead.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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What we have to do is just to wait for given micro-seconds. No need to
take into account current time, get_timer and CFG_HZ.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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We already have many pre-defined CP0 access macros in <asm/mipsregs.h>.
This patch replaces mips_{compare,count}_set and mips_count_get with
existing macros.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
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Use correct field in block_dev_desc_t when writing interface type in
dev_print. Error introduced in 574b3195.
Also added fix from Martin Krause
Signed-off-by: Tor Krill <tor@excito.com>
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Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
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relocating
Removed unneeded command line history initialization. Also, the original
code would access the 'initted' variable before relocation to SDRAM
which resulted in erratic behavior since the bss is not initialized when
executing from flash.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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This patch simplifies post_word_{load,store} by using the preprocessor
to eliminate redundant, copy-and-pasted code.
Signed-off-by: Grant Erickson <gerickson@nuovations.com>
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On AD7414 the first value upon bootup is not read correctly.
This is most likely because of the 800ms update time of the
temp register in normal update mode. To get current values
each time we issue the "dtt" command including upon powerup
we switch into one-short mode.
This patch fixes the problem on AD7414 equipped boards (Sequoia,
Canyonlands etc), that temp value printed in the bootup log was
incorrect.
Signed-off-by: Stefan Roese <sr@denx.de>
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This is pretty incomplete...it doesn't handle reading the environment
before relocation, it doesn't support redundant environment, and it
doesn't support embedded environment. But apart from that, it does
seem to work.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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This adds a new command, "sf" which can be used to manipulate SPI
flash. Currently, initialization, reading, writing and erasing is
supported.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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This adds a new SPI flash subsystem.
Currently, only AT45 DataFlash in non-power-of-two mode is supported,
but some preliminary support for other flash types is in place as
well.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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This adds a driver for the SPI controller found on most AT91 and AVR32
chips, implementing the new SPI API.
Changed in v4:
- Update to new API
- Handle zero-length transfers appropriately. The user may send a
zero-length SPI transfer with SPI_XFER_END set in order to
deactivate the chip select after a series of transfers with chip
select active. This is useful e.g. when polling the status
register of DataFlash.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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This patch gets rid of the spi_chipsel table and adds a handful of new
functions that makes the SPI layer cleaner and more flexible.
Instead of the spi_chipsel table, each board that wants to use SPI
gets to implement three hooks:
* spi_cs_activate(): Activates the chipselect for a given slave
* spi_cs_deactivate(): Deactivates the chipselect for a given slave
* spi_cs_is_valid(): Determines if the given bus/chipselect
combination can be activated.
Not all drivers may need those extra functions however. If that's the
case, the board code may just leave them out (assuming they know what
the driver needs) or rely on the linker to strip them out (assuming
--gc-sections is being used.)
To set up communication parameters for a given slave, the driver needs
to call spi_setup_slave(). This returns a pointer to an opaque
spi_slave struct which must be passed as a parameter to subsequent SPI
calls. This struct can be freed by calling spi_free_slave(), but most
driver probably don't want to do this.
Before starting one or more SPI transfers, the driver must call
spi_claim_bus() to gain exclusive access to the SPI bus and initialize
the hardware. When all transfers are done, the driver must call
spi_release_bus() to make the bus available to others, and possibly
shut down the SPI controller hardware.
spi_xfer() behaves mostly the same as before, but it now takes a
spi_slave parameter instead of a spi_chipsel function pointer. It also
got a new parameter, flags, which is used to specify chip select
behaviour. This may be extended with other flags in the future.
This patch has been build-tested on all powerpc and arm boards
involved. I have not tested NIOS since I don't have a toolchain for it
installed, so I expect some breakage there even though I've tried
fixing up everything I could find by visual inspection.
I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and
DataFlash drivers posted as a follow-up. I'd like some help testing
other boards that use the existing SPI API.
But most of all, I'd like some comments on the new API. Is this stuff
usable for everyone? If not, why?
Changed in v4:
- Build fixes for various boards, drivers and commands
- Provide common struct spi_slave definition that can be extended by
drivers
- Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate
- Make default bus and mode build-time configurable
- Override default SPI bus ID and mode on mx32ads and imx31_litekit.
Changed in v3:
- Add opaque struct spi_slave for controller-specific data associated
with a slave.
- Add spi_claim_bus() and spi_release_bus()
- Add spi_free_slave()
- spi_setup() is now called spi_setup_slave() and returns a
struct spi_slave
- soft_spi now supports four SPI modes (CPOL|CPHA)
- Add bus parameter to spi_setup_slave()
- Convert the new i.MX32 SPI driver
- Convert the new MC13783 RTC driver
Changed in v2:
- Convert the mpc8xxx_spi driver and the mpc8349emds board to the
new API.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Tested-by: Guennadi Liakhovetski <lg@denx.de>
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AVR32 and AT91SAM9 both have their own identical definitions of
container_of() taken from the Linux kernel. Move it to common.h so
that all architectures can use it.
container_of() is already used by some drivers, and will be used
extensively by the new and improved SPI API.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Spotted by Dean Capindale.
Systems that support open-drain GPIO properly are allowed provide an
empty I2C_TRISTATE define. However, this means that we need to be
careful not to drive SDA low when the slave is expected to respond.
This patch adds a missing I2C_SDA(1) to read_byte() required to
tristate the SDA line on systems that support open-drain GPIO.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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* The cfi_flash.c memset fix actual allows the board to boot so there is
a bit more going on here than just resolving warnings associated with
uninitialized variables.
* include/asm/bitops.h:302: warning: '__swab32p' is static but used in
inline function 'ext2_find_next_zero_bit' which is not static
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Currently, END_OF_RAM is used by the trap code to determine if
we should attempt to access the stack pointer or not. However,
on systems with a lot of RAM, only a subset of the RAM is
guaranteed to be mapped in and accessible. Change END_OF_RAM
to use get_effective_memsize() instead of using the raw ram
size out of the bd.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
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If common.h isn't first we can get CONFIG_ options defined in the
board config file ignored. This can cause an issue if any of those
config options impact the size of types of data structures
(eg CONFIG_PHYS_64BIT).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Add logbuffer to reserved LMB areas to prevent initrd allocation
from overlaping with it.
Make sure to use correct logbuffer base address.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
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Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
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This function prints the values of all the BAT register
pairs - I needed this for debug earlier this week; adding it to
lib_ppc so others can use it (and add it to reginfo commands
if so desired).
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
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Currently, this code only deals with BATs 0-3, which makes
it useless on systems that support BATs 4-7. Add the
support for these registers.
Signed-off-by: Becky Bruce <Becky.bruce@freescale.com>
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Change all code that conditionally operates on high bat
registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS
instead of the myriad ways this is done now. Define the option
for every config for which high bats are supported (and
enabled by early boot, on parts where they're not always
enabled)
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
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All other u-boot architectures have an include/asm/errno.h, so
this change adds it to the mips include/asm-mips headers also.
Stolen from Linux 2.6.25.
Signed-off-by: Jason McMullan <mcmullan@netapp.com>
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Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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No functional changes.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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The mips architecture currently does not call 'spi_init()' in the generic
board initialization routine is CONFIG_CMD_SPI is defined.
This patch rectifies that problem.
Signed-off-by: Jason McMullan <mcmullan@netapp.com>
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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This patch adds the standard 'nand_init()' call to the mips generic
'board_init_r()' call, bringing MIPS in line with the other architectures.
Signed-off-by: Jason McMullan <mcmullan@netapp.com>
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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Likewise with onenand_init().
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Don't assume types are provided by previously included headers.
Signed-off-by: Scott Wood <scottwood@freescale.com>
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For NAND erase sizes smaller than one NAND erase block, erase
percentage output becomes grater than 100% e.g.
-- cut --
> nand info
Device 0: NAND 64MiB 1,8V 8-bit, sector size 16 KiB
> nand erase 0x100000 0x2000
NAND erase: device 0 offset 0x100000, size 0x2000
Erasing at 0x100000 -- 200% complete.
OK
>
-- cut --
Correct this and give user a warning that more is erased than specified:
-- cut --
> nand erase 0x100000 0x2000
NAND erase: device 0 offset 0x100000, size 0x2000
Warning: Erase size 0x00002000 smaller than one erase block 0x00004000
Erasing 0x00004000 instead
Erasing at 0x100000 -- 100% complete.
OK
>
-- cut --
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
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The nand_info array is declared as extern in several .c files.
Those days, nand.h contains a reference to the array, so there is
no need to declare it elsewhere.
Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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This allows the header to be included regardless of whether a board's
config file provides NAND-related defininitions.
Signed-off-by: Scott Wood <scottwood@freescale.com>
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If the specified delay is very short, the cycle counter may go past the
"end" time we are waiting for before we get around to reading it.
Fix it by checking the different between the cycle count "now" and the
cycle count at the beginning. This will work as long as the delay
measured in number of cycles is below 2^31.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Remove #ifdef CONFIG_MMC from the source file and use conditional
compilation in the Makefile instead.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Make sure we check for CRC errors when sending commands that use CRC
checking.
Reported-by: Gururaja Hebbar K R <gururajakr@sanyo.co.in>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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The warnings are harmless but annoying. Let's fix them.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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