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2012-09-29Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD
2012-09-29Merge remote-tracking branch 'u-boot-atmel/master'Albert ARIBAUD
2012-09-24mx28evk: Add missing 'setexpr' commandOtavio Salvador
The environment now uses expressions but we missed the setexpr command was not being include. This patch adds it. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-24i.MX: shut down video before launch of O/SEric Nelson
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-09-24i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU frame bufferEric Nelson
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-24mx28evk: Remove fecmxc_mii_postcall()Fabio Estevam
fecmxc_mii_postcall() is specific to the KSZ9021 PHY on m28evk and should not be used on mx28evk, which has LAN8270 instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
2012-09-23KARO TX25: Fix NAND Flash R/W cycle timesBenoît Thébaudeau
The NAND Flash of the KARO TX25 board is a Samsung K9F1G08U0B with 25-ns R/W cycle times. However, the NFC clock for this board was set to 66.5 MHz, so using the NFC driver in symmetric mode (i.e. 1 NFC clock cycle = 1 NF R/W cycle) resulted in NF R/W cycle times of 15 ns, hence corrupted NF accesses. This patch fixes this issue by setting the NFC clock to the highest frequency complying to the 25-ns NF R/W cycle times specification, i.e. 33.25 MHz. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: John Rigby <jcrigby@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Daniel Gachet <Daniel.Gachet@hefr.ch> Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-23mx51evk: Add CONFIG_REVISION_TAGBenoît Thébaudeau
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. If this data is not present, the kernel misconfigures the TZIC, which results in the timer interrupt handler never being called, so the kernel deadlocks while calibrating its delay. Suggested-by: Greg Topmiller <Greg.Topmiller@jdsu.com> Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-21Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD
2012-09-17Atmel: sam9g10/9m10/9x5: Add support to boot DT kernelBo Shen
The mainline linux kernel is moving to flatten device tree support Add the CONFIG_OF_LIBFDT option to support booting DT linux kernel Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-17spiflash: at25: using common spi flash operationBo Shen
Using common spi flash operation function to replace private operation funtion Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-17spi: add atmel at25df321 serial flash supportBo Shen
Add atmel at25df321 serial flash support Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-17mx35pdk: README: Remove NAND referencesFabio Estevam
Booting from NAND is currently not supported, so remove its references. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-17mx28evk: extend default environmentOtavio Salvador
The environment has been based on mx53loco and m28evk but keeping the possibility to easy change the default console device as Freescale and mainline kernels differ on the device name. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-17MX6: drop binary constants from iomux headerStefano Babic
Constants set with binary value (0b...) are not compiled from old toolchain when used by the clrsetbits_le32 macro. Replaces them with the corresponding hex value. The error reported (for example with the mx6qsabrelite board) is something like: mx6qsabrelite.c:369:1: error: invalid suffix "b101" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10010" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b0000" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10001" on integer constant Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-09-13atmel_nand: fix the U-Boot output information about nand flash with PMECC ↵Wu, Josh
enable. Before the patch, it looks like: |U-Boot 2012.07-00441-gd578d6f-dirty (Sep 10 2012 - 16:11:06) | |CPU: AT91SAM9G35 |Crystal frequency: 12 MHz |CPU clock : 400 MHz |Master clock : 133.333 MHz |DRAM: 128 MiB |WARNING: Caches not enabled > |NAND: Initialize PMECC params, cap: 2, sector: 512 > |256 MiB |MMC: mci: 0 |In: serial |Out: serial |Err: serial |Net: macb0 |Hit any key to stop autoboot: 0 After the patch: |U-Boot 2012.07-00441-gd578d6f-dirty (Sep 10 2012 - 16:18:11) | |CPU: AT91SAM9G35 |Crystal frequency: 12 MHz |CPU clock : 400 MHz |Master clock : 133.333 MHz |DRAM: 128 MiB |WARNING: Caches not enabled > |NAND: 256 MiB | ... ... |Hit any key to stop autoboot: 0 Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-13at91sam9x5: set default EBI I/O drive configuration.Wu, Josh
This patch configure at91sam9x5's EBI drive I/O. Without this, When SD card boot, the nand flash read/write are not stable. Which will cause kernel MTD test fail (Since mainline kernel doesn't configure the EBI register). Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-10NAND: MXS: include common.h first so cache.h is included in correct orderTom Warren
With Simon Glass's include/nand.h alignment changes, some mxs builds were generating errors. Fix is to ensure asm/cache.h is included before linux/mtd/nand.h. Moving common.h to top of include list does that. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
2012-09-10Tegra: Change Tegra20 to Tegra in common code, prep for T30Tom Warren
Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate. Convert tegra20_ source file and function names to tegra_, also. Upcoming Tegra30 port will use common code/defines/names where possible. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2012-09-10tegra20: usb: rework set_host_modeLucas Stach
This allows for two things: - VBus GPIO may be used on other ports than the OTG one - VBus GPIO may be low active if specified by DT Signed-off-by: Lucas Stach <dev@lynxeye.de> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Tom Warren <TWarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-10MX35: mx35pdk: add support for MMCStefano Babic
Add support for SD card and change the default environment due to increased u-boot size. Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-09-10mx6qsabrelite:Use IMX_GPIO_NR MacroAshok Kumar Reddy
Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
2012-09-10MX: set a common place to share code for Freescale i.MXStefano Babic
Up now only MX5 and MX6 can share code, because they have a common source directory in cpu/armv7. Other not armv7 i.MX can profit of the same shared code. Move these files into a directory accessible for all, similar to plat-mxc in linux. Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-09-10ima3-mx53:Rename CONFIG_PRIME => CONFIG_ETHPRME, removeAshok Kumar Reddy
unused macro CONFIG_DISCOVER_PHY Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-07ARM: tegra: fix Ventana standalone buildStephen Warren
Ventana always pulls in files from the Seaboard directory, so needs to mkdir $(obj)../seaboard unconditionally. This fixes: git clean -f -d -x ./MAKEALL ventana "MAKEALL -s tegra20" passes without this change, because Seaboard happens to be built before Ventana, and hence the directory has already been created. I believe the mkdir is only needed for out-of-tree builds, since the seaboard directory is part of the source tree. However, since we always build an SPL for Tegra now, which I believe is effectively an out-of-tree build, we will always need this at some time. The overhead of just uncondtionally executing the mkdir is minimal, and simplifies the Makefile, since we don't need to code up the exact minimal condition to execute the mkdir. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07ARM: tegra: remove redundant mkdirs from board MakefilesStephen Warren
None of harmony, seaboard, ventana, whistler directly build files from ../common/, so there's no need to mkdir the obj directory for such files. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07tegra: put eMMC environment into the boot sectorsStephen Warren
When I set up Tegra's config files to put the environment into eMMC, I assumed that CONFIG_ENV_OFFSET was a linearized address relative to the start of the eMMC device, and spanning HW partitions boot0, boot1, general* and the user area in order. However, it turns out that the offset is actually relative to the beginning of the user area. Hence, the environment block ended up in a different location to expected and documented. Set CONFIG_SYS_MMC_ENV_PART=2 (boot1) to solve this, and adjust CONFIG_ENV_OFFSET to be relative to the start of boot1, not the entire eMMC. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07env_mmc: allow environment to be in an eMMC partitionStephen Warren
eMMC devices may have hardware-level partitions: 2 boot partitions, up to 4 general partitions, plus the user area. This change introduces optional config variable CONFIG_SYS_MMC_ENV_PART to indicate which partition the environment should be stored in: 0=user, 1=boot0, 2=boot1, 4..7=general0..3. This allows the environment to be kept out of the user area, which simplifies the management of OS-/user-level (MBR/GPT) partitions within the user area. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07mmc: detect boot sectors using EXT_CSD_BOOT_MULT tooStephen Warren
Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set. Note that the Linux kernel enables access to boot partitions solely based on the value of EXT_CSD_BOOT_MULT; EXT_CSD_PARTITIONING_SUPPORT only influences access to "general" partitions. eMMC devices affected by this issue exist on various NVIDIA Tegra platforms (and presumably many others too), such as Harmony (plug-in eMMC), Seaboard, Springbank, and Whistler (plug-in eMMC). Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07tegra: Enable NAND on TECThierry Reding
This commit enables NAND support on the Tamonten Evaluation Carrier and adds the corresponding device tree nodes. Furthermore, the U-Boot environment can now be stored in NAND. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07cmd_nand: dump: Align data and OOB buffersThierry Reding
In order for cache invalidation and flushing to work properly, the data and OOB buffers must be aligned to full cache lines. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07tegra: enable NAND on HarmonyStephen Warren
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07tegra: Enable NAND on SeaboardSimon Glass
This enables NAND support for the Seaboard. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07tegra: nand: Add Tegra NAND driverJim Lin
A device tree is used to configure the NAND, including memory timings and block/pages sizes. If this node is not present or is disabled, then NAND will not be initialized. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07tegra: fdt: Add NAND definitions to fdtSimon Glass
Add a flash node to handle the NAND, including memory timings and page / block size information. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07tegra: fdt: Add NAND controller binding and definitionsSimon Glass
Add a NAND controller along with a bindings file for review. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07tegra: Add NAND support to funcmuxSimon Glass
Add selection of NAND flash pins to the funcmux. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07nand: Try to align the default buffersSimon Glass
The NAND layer needs to use cache-aligned buffers by default. Towards this goal. align the default buffers and their members according to the minimum DMA alignment defined for the architecture. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Scott Wood <scottwood@freescale.com>
2012-09-06mx31: Define default SoC input clock frequenciesBenoît Thébaudeau
Define default SoC input clock frequencies for i.MX31 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Helmut Raiger <helmut.raiger@hale.at>
2012-09-06MX28: MMC: Avoid DMA DCache race conditionMarek Vasut
This patch prevents dcache-related problem. The problem manifested itself on the SPI driver, this is just a port to the MMC driver. The scenario is the same. In case an "mmc read" is issued to a buffer which was written right before it and data cache is enabled, the cache eviction might happen during the DMA transfer into the buffer, therefore corrupting the buffer. Clear any cache lines that might contain the buffer to prevent such issue. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
2012-09-06MX28: SPI: Fix the DMA chainingMarek Vasut
It turns out that in order for the SPI DMA to properly support continuous transfers longer than 65280 bytes, there are some very important parts that were left out from the documentation. Firstly, the XFER_SIZE register is not written with the whole length of a transfer, but is written by each and every chained descriptor with the length of the descriptors data buffer. Next, unlike the demo code supplied by FSL, which only writes one PIO word per descriptor, this does not apply if the descriptors are chained, since the XFER_SIZE register must be written. Therefore, it is essential to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are written with zero, since they don't apply. The DMA programs the PIO words in an incrementing order, so four PIO words. Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC must not be set during the whole transfer, but it must be set only on the last descriptor in the chain. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
2012-09-06MX28: SPI: Fix the DMA DCache race conditionMarek Vasut
This patch fixes dcache-related problem. The problem manifested when dcache was enabled and the following command issued twice: mw 0x42000000 0 0x4000 ; sf probe ; sf read 0x42000000 0x0 0x10000 ; sha1sum 0x42000000 0x10000 The SHA1 checksum was correct during the first call. Yet with every subsequent call of the above command, it differed and was wrong. It turns out this was because of a race condition. On the first time the command was called, no cacheline contained any data from the destination memory location. The DMA transfered data into the location and the cache above the location was invalidated. Then the checksum was computed, but that meant the data were loaded into data cache. On any subsequent call, the DMA again transfered data into the same destination. Yet during the transfer, some of the DCache lines were evicted and written back into the main memory. Once the DMA transfer completed, the data cache was invalidated over the memory location as usual. But the data that were to be loaded back into the data cache by subsequent SHA1 checksuming were corrupted. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
2012-09-06Fix mx31_decode_pllBenoît Thébaudeau
The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
2012-09-06mx35 timer: Switch to 32-kHz sourceBenoît Thébaudeau
Switch the mx35 timer driver to the 32-kHz clock source to avoid calling mxc_get_clock() again and again, and to be consistent with the timer drivers of other i.MX SoCs. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-06mx35: Define default SoC input clock frequenciesBenoît Thébaudeau
Define default SoC input clock frequencies for i.MX35 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-06mx25: Define default SoC input clock frequenciesBenoît Thébaudeau
Define default SoC input clock frequencies for i.MX25 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Matthias Weisser <weisserm@arcor.de>
2012-09-06mx35: Fix clock dividersBenoît Thébaudeau
The clock dividers that were used do not match at all the reference manual. They were either completely broken, or came from an early silicon revision incompatible with the current one. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
2012-09-06mx35: Add definitions for clock gate valuesBenoît Thébaudeau
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
2012-09-06mx35: Fix decode_pllBenoît Thébaudeau
The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
2012-09-05Merge remote-tracking branch 'u-boot-ti/master' into mAlbert ARIBAUD
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