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2021-06-24net: ti: icssg-prueth: Add ICSSG ethernet driverRoger Quadros
This is the PURSS Ethernet driver for TI AM654 Sr2.0 and laterSoCs with the ICSSG PRU Sub-system running EMAC firmware. This driver caters to either of the slices(pru/rtu pair) of the icssg subsystem. One and exactly one of the slices is supported as the u-boot ethernet supports probing one interface at a time. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-06-23remoteproc: pru: Add support for various PRU cores on K3 AM65x SoCsKeerthy
The K3 AM65x family of SoCs have the next generation of the PRU-ICSS processor subsystem, commonly referred to as ICSSG. Each ICSSG processor subsystem on AM65x SR1.0 contains two primary PRU cores and two new auxiliary PRU cores called RTUs. The AM65x SR2.0 SoCs have a revised ICSSG IP that is based off the subsequent IP revision used on J721E SoCs. This IP instance has two new custom auxiliary PRU cores called Transmit PRUs (Tx_PRUs) in addition to the existing PRUs and RTUs. Each RTU and Tx_PRU cores have their own dedicated IRAM (smaller than a PRU), Control and debug feature sets, but is different in terms of sub-modules integrated around it and does not have the full capabilities associated with a PRU core. The RTU core is typically used to aid a PRU core in accelerating data transfers, while the Tx_PRU cores is normally used to control the TX L2 FIFO if enabled in Ethernet applications. Both can also be used to run independent applications. The RTU and Tx_PRU cores though share the same Data RAMs as the PRU cores, so the memories have to be partitioned carefully between different applications. The new cores also support a new sub-module called Task Manager to support two different context thread executions. The driver currently supports the AM65xx SoC Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-06-23soc: ti: pruss: Add a platform driver for PRUSS in TI SoCsKeerthy
The Programmable Real-Time Unit - Industrial Communication Subsystem (PRU-ICSS) is present of various TI SoCs such as AM335x or AM437x or the AM654x family. Each SoC can have one or more PRUSS instances that may or may not be identical. The PRUSS consists of dual 32-bit RISC cores called the Programmable Real-Time Units (PRUs), some shared, data and instruction memories, some internal peripheral modules, and an interrupt controller. The programmable nature of the PRUs provide flexibility to implement custom peripheral interfaces, fast real-time responses, or specialized data handling. Add support for pruss driver. Currently am654x family is supported. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-06-23board: ti: Include sr1 base board as an overlayLokesh Vutla
Add sr1.0 overlay as part of k3_dtbo_list, so that SPL can apply sr1.0 overlay to U-Boot. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-06-23misc: uclass: Introduce misc_init_by_ofnodeKeerthy
Introduce misc_init_by_ofnode to probe a misc device using its ofnode. Signed-off-by: Keerthy <j-keerthy@ti.com>
2021-06-23net: eth-uclass: call stop only for active devicesKeerthy
Currently stop is being called unconditionally without even checking if start is called which will result in crash where multiple instances are present and stop gets called even without calling start. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-06-23net: eth-uclass: eth_get_dev based on SEQ_ALIAS instead of probe orderKeerthy
In case of multiple eth interfaces currently eth_get_dev fetches the device based on the probe order which can be random hence try with the alias. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-06-23configs: am65x_evm_a53: Re order the overlay filesLokesh Vutla
In case of SPL_LOAD_FIT_APPLY_OVERLAY, overlay files are applied in the order as specified in overlay structure in board/ti/am65x/evm.c: - k3-am654-gp.dtbo - k3-am654-idk.dtbo - k3-am654-pcie-usb2.dtbo - k3-am654-pcie-usb3.dtbo - k3-am654-evm-oldi-lcd1evm.dtbo Since it is peripheral boot and overlays are applied on the fly, if the above order is not maintained, specific overlays cannot be applied as images would have already loaded and got discarded. So create u-boot.img with the above order. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-06-23ARM: DRA7: Enable OPP_HIGH for GPU voltage domainSubhajit Paul
Enable the OPP_HIGH configuration for GPU voltage domain by default for various TI DRA7xx and AM57xx boards. This is being done to meet the performance needs of 1080p GFX/MultiMedia usecases. This domain does not support DVFS and the kernel will continue to run at the boot OPP chosen here. Based on logic similar to that of DSPEVE and IVA voltage domains in commit 58a8921fe34fd5 ("ARM: DRA7: Enable OPP_HIGH for DSPEVE and IVA voltage domains") Signed-off-by: Subhajit Paul <subhajit_paul@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2021-06-23ARM: DRA7: Enable OPP_HIGH for DSPEVE and IVA voltage domainsSuman Anna
Enable the OPP_HIGH configuration for DSPEVE and IVA voltage domains by default for various TI DRA7xx and AM57xx boards. This is being done to meet the performance needs of 1080p MultiMedia usecases and other DSP usecases. These domains do not support DVFS and the kernel will continue to run at the boot OPPs chosen here. Signed-off-by: Suman Anna <s-anna@ti.com>
2021-06-23board: ti: k2g: Program PadConfig_202 before locking RSTMUX8Suman Anna
The PADCONFIG_202 register (0x02621328) is affected by the locking of the RSTMUX8 register (0x02620328), and so cannot be configured in kernel. This has been confirmed as a hardware bug and affects all K2G SoCs. Setup the pinmux for this pin before locking the RSTMUX8 register to allow the ICSS1 PRU1 Ethernet PHY port to work properly. The workaround was added only for the K2G-ICE board to configure the pins needed for the PRUSS Ethernet usecase. Signed-off-by: Suman Anna <s-anna@ti.com>
2021-06-23HACK: arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS ↵Roger Quadros
Northbridge NB0 is bridge to SRAM and NB1 is bridge to DDR. To ensure that SRAM transfers are not stalled due to delays during DDR refreshes, SRAM traffic should be higher priority (threadmap=2) than DDR traffic (threadmap=0). This patch does just that. This is required to fix ICSSG TX lock-ups due to delays in MSMC transfers due to incorrect Northbridge configuration. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Andrew F. Davis <afd@ti.com> Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Benoit Parrot <bparrot@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-06-18arm: dts: k3-j7200: ddr: Update to 0.6.0 version of DDR config toolKevin Scholz
Update the ddr settings to use the DDR reg config tool rev 0.6.0. This enables 2666MTs DDR configuration. Signed-off-by: Kevin Scholz <k-scholz@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-06-18arm: dts: k3-j721e: ddr: Update to 0.6.0 version of DDR config toolKevin Scholz
Update the ddr settings to use the DDR reg config tool rev 0.6.0. Signed-off-by: Kevin Scholz <k-scholz@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-06-18arm: dts: k3-j721e-ddr: Add ti,ddr-freq0Kevin Scholz
Add ti,ddr-freq0 entry for the DDR controller used by j721e and j7200 and provide a value in the corresponding SoC specific configuration files. Signed-off-by: Kevin Scholz <k-scholz@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-06-18ram: k3-ddrss: Allow use of dt provided initial frequencyDave Gerlach
Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR frequency that is set for lpddr4 before initialization of the controller. Make this optional and continue to use bypass frequency if ti,ddr-freq0 is not provided. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> [praneeth@ti.com: fix minor build error] Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
2021-06-06configs: j721e_evm_a72: Disable UHS modeSuman Anna
The J721E PM1 SoM board uses a TPS65917 PMIC with the MMC card IO supply provided by LDO1 regulator. This regulator comes up in bypass mode by default with the input supply at 3.3V. As such, the board fails to boot with UHS mode enabled. This can probably work if the regulator is switched into regular operating mode, but there is no support for this PMIC in U-Boot. So disable the UHS mode to have the boot functional on this board. Signed-off-by: Suman Anna <s-anna@ti.com>
2021-06-06configs: j721e_evm: Add support for loading PM1 SOM dtbSuman Anna
Customize the findfdt command to find the appropriate dtb for J721E PM1 SOM boards leveraging the board_name variable. Signed-off-by: Suman Anna <s-anna@ti.com>
2021-06-06board: ti: j721e: evm: Update board_name to reflect the right SoMKeerthy
Update board_name to reflect the right SoM Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2021-06-06arm: dts: k3-j721e: Add a PM1 SoM specific dts fileKeerthy
The J721E PM1 SoM board uses a TPS65917 PMIC. The MMC SDCard IO supply is provided by the LDO1 regulator from this PMIC. Add a separate PM1 SoM specific dts file with this PMIC, and make the necessary adjustments for the regulator consumer usage changes. Signed-off-by: Keerthy <j-keerthy@ti.com> [s-anna@ti.com: port to 2021 LTS and split up the A72 dts] Signed-off-by: Suman Anna <s-anna@ti.com>
2021-06-06HACK: arm: mach-k3: j721e: Fix AVS Class 0 for PM1 SoMKeerthy
The J721E PM1 SoM uses TPS65917 PMIC, and uses a different regulator (SMPS12) as the supply for A72 AVS Class 0. Add support for this by fixing up the DT supply dynamically based on the board version to get the right phandle for avs supply regulator. The same k3-j721e-r5-common-proc-board.dts file is used to avoid dynamic detection for R5 SPL DTB, with the TPS65917 PMIC nodes added. Both PMIC nodes are present (not at all ideal), but their sole usage is to provide for AVS Class 0 functionality. There is no plan to upstream this support, and hence the simpler HACK approach is taken. Signed-off-by: Keerthy <j-keerthy@ti.com> [s-anna@ti.com: port to 2021 LTS and split up the R5 portion] Signed-off-by: Suman Anna <s-anna@ti.com>
2021-06-06board: ti: j721e: evm: Add board detection for PM1 and PM2 SoMsKeerthy
Add PM1 & PM2 SoM detection support. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2021-06-06configs: j721e_evm_a72/r5: Resync defconfigs using savedefconfigSuman Anna
Resync the j721e_evm_a72_defconfig and j721e_evm_r5_defconfig using savedefconfig. CONFIG_K3_DM_FW gets auto-selected due to default option in its Kconfig, otherwise all the others are just relocated. The commented out CONFIG_TI_SCI_POWER_DOMAIN and CONFIG_CLK_TI_SCI are cleaned up. Signed-off-by: Suman Anna <s-anna@ti.com>
2021-06-06configs: am64: Add and enable configs required for USB DFU boot mode supportAswath Govindraju
Add and enable configs required to add support for USB DFU boot mode. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-06-06arm: dts: k3-am64-main: Update the location of ATF in SRAM and increase its ↵Aswath Govindraju
max size Due to a limitation for USB DFU boot mode, SPL load address has to be less than or equal to 0x70001000. So, load address of SPL and ATF have been moved to 0x70000000 and 0x701a0000 respectively. Also, the maximum size of ATF has been increased to 0x1c000 [1]. Therefore, update ATF's location and maximum size accordingly in the device tree file. [1] - https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=2fb5312f61a7de8b7a70e1639199c4f14a10b6f9 Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-06-06configs: am64x_evm_*_defconfig: Rearrange the components in SRAM to satisfy ↵Aswath Govindraju
the limitations for USB DFU boot mode For USB DFU boot mode there is a limitation on the load address of boot images that they have to be less than 0x70001000. Therefore, move the SPL_TEXT_BASE address to 0x70000000. Currently ATF is being loaded at 0x70000000, if the SPL is being loaded at 0x70000000 then ATF would overwrite SPL image when loaded. Therefore, move the location of ATF to a latter location in SRAM, past the SPL image. Also rearrange the EEPROM and BSS data on top of ATF. Given below is the placement of various data sections in SRAM ┌──────────────────────────────────────┐0x70000000 │ │ │ │ │ │ │ SPL IMAGE (Max size 1.5 MB) │ │ │ │ │ │ │ ├──────────────────────────────────────┤0x7017FFFF │ │ │ SPL STACK │ │ │ ├──────────────────────────────────────┤0x70192727 │ GLOBAL DATA(216 B) │ ├──────────────────────────────────────┤0x701927FF │ │ │ INITIAL HEAP (32 KB) │ │ │ ├──────────────────────────────────────┤0x7019A7FF │ │ │ BSS (20 KB) │ ├──────────────────────────────────────┤0x7019F7FF │ EEPROM DATA (2 KB) │ ├──────────────────────────────────────┤0x7019FFFF │ │ │ │ │ ATF (123 KB) │ │ │ │ │ ├──────────────────────────────────────┤0x701BEBFB │ BOOT PARAMETER INDEX TABLE (5124 B)│ ├──────────────────────────────────────┤0x701BFFFF │ │ │SYSFW FIREWALLED DUE TO A BUG (128 KB)│ │ │ ├──────────────────────────────────────┤0x701DFFFF │ │ │ DMSC CODE AREA (128 KB) │ │ │ └──────────────────────────────────────┘0x701FFFFF Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-06-06tools: k3_fit_atf: Add support for providing ATF load address using a ↵Aswath Govindraju
Kconfig symbol Add support for providing ATF load address with a Kconfig symbol. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
2021-06-06ddr: k3-j7200: EMIF Tool update for LPDDR with 2666MTs configurationKevin Scholz
EMIF tool for J7200 is now updated to 0.5.0 * Includes LPDDR with 2666MTs configuration Signed-off-by: Kevin Scholz <k-scholz@ti.com> Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Tested-by: Suman Anna <s-anna@ti.com>
2021-06-03arch:arm:dts:k3-am64-sk remove 800MHz lp4ddr configSinthu Raja
AM64x SK lp4ddr 800MHz frequency configuration was initial data which is still under investigation for random failures and is expected to be tweaked. Lets delete this initial configuration for now till the final values are stabilized. Suggested-by: Lokesh Vutla <lokeshvutla@ti.com> Suggested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2021-06-03arch:arm:dts:k3-am64-sk Add lp4ddr config for 667MHzSinthu Raja
AM64x SK lp4ddr with 800MHz frequency config which was initial data facing random failures. Alternatively, lp4ddr configuration with 667MHz frequency is functioning stable. Lets Add AM64x SK lp4ddr configuration data for 667MHz frequency. Also, Update k3-am642-r5-sk.dts file to use the 667MHz dtsi file. Validated memtester test on 900MB of lp4 ddr memory with multiple iterations. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Reviewed-by: James Doublesin <doublesin@ti.com>
2021-06-01arm: dts: k3-j7200: Add wkup gpio nodeVignesh Raghavendra
Add wkup_gpio0 node required for detecting whether board mux is set to HyperFlash. Fixes: b4916daf24f7 ("arm: dts: k3-j7200: Sync Linux v5.11-rc6 dts into U-Boot") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-05-31arm: dts: k3-j721e: Fix up MAIN R5FSS cluster mode back to Split-modeSuman Anna
The default U-Boot environment variables and design are all set up for both the MAIN R5FSS clusters to be in Split-mode. This is the setting in v2021.01 U-Boot and the dt nodes are synched with the newer kernel binding property names in commit c118d255460f ("remoteproc: k3_r5: Sync to upstreamed kernel DT property names"). The modes for both the clusters got switched back to LockStep mode by mistake in commit 16c0c844600d ("arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-Boot"). This throws the following warning messages when early-booting the cores using default env variables, k3_r5f_rproc r5f@5d00000: Invalid op: Trying to start secondary core 7 in lockstep mode Load Remote Processor 3 with data@addr=0x82000000 98484 bytes: Failed! k3_r5f_rproc r5f@5f00000: Invalid op: Trying to start secondary core 9 in lockstep mode Load Remote Processor 5 with data@addr=0x82000000 98484 bytes: Failed! Fix this by switching back both the clusters to the expected Split-mode. Make this mode change in the u-boot specific dtsi file to avoid such sync overrides in the future until the kernel dts is also switched to Split-mode by default. Fixes: 16c0c844600d ("arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-Boot") Reported-by: Minas Hambardzumyan <minas@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2021-05-31ARM: dts: k3-am642/am654/j72xx: Fix ethernet alias for U-BootVignesh Raghavendra
While Kernel expects ethernetX alias to point to individual ethernet ports in case of multi MAC ethernet controller, U-Boot DM core expects ethernetX alias to point to the node that ethernet (am65-cpsw-nuss) driver binds to. Hence aliases copied from kernel DT will leads to 3 issues: - ethernet interfaces on K3 SoCs get a different seq number than that of intended alias (eg.: CPSW port0 on AM65x get eth1 instead of eth0). - "ethaddr" env variable is no longer set to eFuse MAC address. - U-Boot FDT fixup code won't update MAC address in Kernel's DT due to missing "ethaddr" variable. Fix this by updating alias to point to CPSW node in -u-boot.dtsi file for all K3 SoCs to match U-Boot's expectation. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-14configs: am64x_sk: Drop un used defconfigsLokesh Vutla
Now that sk and evm can be used in single defconfig, remove sk related defconfigs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-14configs: am64x_evm: Enable sk related defconfigs in evm defconfigLokesh Vutla
Enable all the relevant defconfigs for SK in EVM defconfigs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-14configs: am64x_evm_a53: Enable support for building multiple dtbsLokesh Vutla
Enable all relevant configs for building multiple dtbs into a single fit image and load the right dtb for next stage. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-14configs: am64x_evm_a53: Sync defconfig with savedefconfigLokesh Vutla
Sync defconfig with savedefconfig. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-14configs: am64x_evm_r5: Enable support for building multiple device treesLokesh Vutla
Enable defconfigs for building multiple device trees into a single FIT image. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-14configs: am64x_evm_r5: Enable checks for spl and stack sizesLokesh Vutla
Enable relevant configs that checks for the size of image and stack: BSS: 4KB Initial MALLOC: 512KB Initial Stack: 8K SPL Image size can be: ~960KB Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-14configs: am64x_evm_r5: Sync defconfigs with savedefconfigLokesh Vutla
Sync defconfig with savedefconfig Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-14include: configs: Update env for selecting right dtbLokesh Vutla
Now that single defconfig can be used for booting AM64 EVM and SK, default device tree will not work for selecting dtb for kernel. Update the env to select right dtb based on eeprom. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-14include: configs: am64x_evm: Optimize size of SPL BSSLokesh Vutla
Current BSS allocation of SPL is as below: size spl/u-boot-spl text data bss dec hex filename 144572 5484 1752 151808 25100 spl/u-boot-spl But 20KB is allocated currently for BSS. Reduce it to 4KB and save some space for stack. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-14arm: dts: k3-am642-r5-evm: Do not use power-domains for I2CLokesh Vutla
I2C EEPROM will be probed before SYSFW is available. So drop the power-domains property for I2C. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-14arm: am64x: Add support for selecting DT based on EEPROMLokesh Vutla
Enable support for selecting DTB within SPL based on EEPROM. This will help to use single defconfig for both EVM and SK Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-14board: ti: am64x: Add support for detecting multiple device treesLokesh Vutla
Update the board_fit_config_name_match() to choose the right dtb. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-14board: ti: am64x: Enable support for reading EEPROM in R5 SPLLokesh Vutla
Include the relevant configs to enable support for reading EEPROM in R5SPL. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-14board: ti: am64x: Enable support for reading EEPROM at next alternate addressLokesh Vutla
AM64 EVM has EEPROM populated at 0x50. Am64 SK has EEPROM populated at next address 0x51 in order to be compatible with RBPi. So start looking for TI specific EEPROM at 0x50, if not found look for EEPROM at 0x51. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-14board: ti: am64x: Guard functions with right #ifdef to avoid build warningsLokesh Vutla
setup_board_eeprom_env() and setup_serial() is called only under CONFIG_BOARD_LATE_INIT, so guard these functions with the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-06arm: dts: k3-am642-sk: Add sysreset controller nodeSuman Anna
The AM64x SoC uses a central Device Management and Security Controller (DMSC) processor that manages all the low-level device controls including the system-wide SoC reset. The system-wide reset is managed through the system reset driver. Add a sysreset controller node as a child of the dmsc node to enable the "reset" command from U-Boot prompt for the K3 AM642 SK. Signed-off-by: Suman Anna <s-anna@ti.com>
2021-05-06arm: dts: k3-am642-evm: Add sysreset controller nodeSuman Anna
The AM64x SoC uses a central Device Management and Security Controller (DMSC) processor that manages all the low-level device controls including the system-wide SoC reset. The system-wide reset is managed through the system reset driver. Add a sysreset controller node as a child of the dmsc node to enable the "reset" command from U-Boot prompt for the K3 AM642 EVM. Signed-off-by: Suman Anna <s-anna@ti.com>
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