diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-blackfin/arch-bf533/anomaly.h | 100 | ||||
| -rw-r--r-- | include/asm-blackfin/arch-bf533/defBF532.h | 2 | ||||
| -rw-r--r-- | include/asm-blackfin/arch-common/cdef_LPBlackfin.h | 31 | ||||
| -rw-r--r-- | include/asm-blackfin/mem_init.h | 32 | ||||
| -rw-r--r-- | include/configs/bf533-ezkit.h | 156 | ||||
| -rw-r--r-- | include/configs/bf533-stamp.h | 378 |
6 files changed, 337 insertions, 362 deletions
diff --git a/include/asm-blackfin/arch-bf533/anomaly.h b/include/asm-blackfin/arch-bf533/anomaly.h index 0e5f9194386..4fe425c9c16 100644 --- a/include/asm-blackfin/arch-bf533/anomaly.h +++ b/include/asm-blackfin/arch-bf533/anomaly.h @@ -46,126 +46,126 @@ /* Issues that are common to 0.5, 0.4, and 0.3 silicon */ #if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in - slot1 and store of a P register in slot 2 is not - supported */ + slot1 and store of a P register in slot 2 is not + supported */ #define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on - every corresponding match */ + every corresponding match */ #define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive - Channel DMA stops */ + Channel DMA stops */ #define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR - registers. */ + registers. */ #define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out - upper bits*/ + upper bits*/ #define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ #define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame - syncs */ + syncs */ #define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not - functional */ + functional */ #define ANOMALY_05000219 /* NMI event at boot time results in unpredictable - state */ + state */ #define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */ #define ANOMALY_05000272 /* Certain data cache write through modes fail for - VDDint <=0.9V */ + VDDint <=0.9V */ #define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */ #define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after - an edge is detected may clear interrupt */ + an edge is detected may clear interrupt */ #define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause - DMA system instability */ + DMA system instability */ #define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is - not restored */ + not restored */ #define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic - control */ + control */ #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when - killed in a particular stage*/ + killed in a particular stage*/ #endif /* These issues only occur on 0.3 or 0.4 BF533 */ #if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) #define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not - updated at the same time. */ + updated at the same time. */ #define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data - Cache Fill can be corrupted after or during - Instruction DMA if certain core stalls exist */ + Cache Fill can be corrupted after or during + Instruction DMA if certain core stalls exist */ #define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General - Purpose TX or RX modes */ + Purpose TX or RX modes */ #define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by - preceding memory read */ + preceding memory read */ #define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during - inactive channels in certain conditions */ + inactive channels in certain conditions */ #define ANOMALY_05000202 /* Possible infinite stall with specific dual dag - situation */ + situation */ #define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ #define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ #define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect - data*/ + data*/ #define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate - Differences in certain Conditions */ + Differences in certain Conditions */ #define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ #define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to - hardware reset */ + hardware reset */ #define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or - IDLE around a Change of Control causes - unpredictable results */ + IDLE around a Change of Control causes + unpredictable results */ #define ANOMALY_05000245 /* Spurious Hardware Error from an access in the - shadow of a conditional branch */ + shadow of a conditional branch */ #define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware - errors */ + errors */ #define ANOMALY_05000253 /* Maximum external clock speed for Timers */ #define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event - interrupt not functional */ + interrupt not functional */ #define ANOMALY_05000257 /* An interrupt or exception during short Hardware - loops may cause the instruction fetch unit to - malfunction */ + loops may cause the instruction fetch unit to + malfunction */ #define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of - the ICPLB Data registers differ */ + the ICPLB Data registers differ */ #define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ #define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ #define ANOMALY_05000262 /* Stores to data cache may be lost */ #define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */ #define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE - instruction will cause an infinite stall in the - second to last instruction in a hardware loop */ + instruction will cause an infinite stall in the + second to last instruction in a hardware loop */ #define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on - SPORT external receive and transmit clocks. */ + SPORT external receive and transmit clocks. */ #define ANOMALY_05000269 /* High I/O activity causes the output voltage of the - internal voltage regulator (VDDint) to increase. */ + internal voltage regulator (VDDint) to increase. */ #define ANOMALY_05000270 /* High I/O activity causes the output voltage of the - internal voltage regulator (VDDint) to decrease */ + internal voltage regulator (VDDint) to decrease */ #endif /* These issues are only on 0.4 silicon */ #if (defined(CONFIG_BF_REV_0_4)) #define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */ #define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel - (TDM) */ + (TDM) */ #endif /* These issues are only on 0.3 silicon */ #if defined(CONFIG_BF_REV_0_3) #define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with - External Frame Syncs */ + External Frame Syncs */ #define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative - Instruction or Data Fetches, or by Fetches at the - boundary of reserved memory space */ + Instruction or Data Fetches, or by Fetches at the + boundary of reserved memory space */ #define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs - when polarity setting is changed */ + when polarity setting is changed */ #define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data - corruption */ + corruption */ #define ANOMALY_05000199 /* DMA current address shows wrong value during carry - fix */ + fix */ #define ANOMALY_05000201 /* Receive frame sync not ignored during active - frames in sport MCM */ + frames in sport MCM */ #define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA - stopping */ + stopping */ #if defined(CONFIG_BF533) #define ANOMALY_05000204 /* Incorrect data read with write-through cache and - allocate cache lines on reads only mode */ + allocate cache lines on reads only mode */ #endif /* CONFIG_BF533 */ #define ANOMALY_05000207 /* Recovery from "brown-out" condition */ #define ANOMALY_05000209 /* Speed-Path in computational unit affects certain - instructions */ + instructions */ #define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame - Sync Transmit Mode */ + Sync Transmit Mode */ #define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */ #endif diff --git a/include/asm-blackfin/arch-bf533/defBF532.h b/include/asm-blackfin/arch-bf533/defBF532.h index 312ff2bf5c8..25a74e68466 100644 --- a/include/asm-blackfin/arch-bf533/defBF532.h +++ b/include/asm-blackfin/arch-bf533/defBF532.h @@ -88,7 +88,7 @@ #define UART_LCR 0xFFC0040C /* Line Control Register */ #define UART_MCR 0xFFC00410 /* Modem Control Register */ #define UART_LSR 0xFFC00414 /* Line Status Register */ -/* #define UART_MSR 0xFFC00418 *//* Modem Status Register (UNUSED in ADSP-BF532) */ +/* #define UART_MSR 0xFFC00418 */ /* Modem Status Register (UNUSED in ADSP-BF532) */ #define UART_SCR 0xFFC0041C /* SCR Scratch Register */ #define UART_GCTL 0xFFC00424 /* Global Control Register */ diff --git a/include/asm-blackfin/arch-common/cdef_LPBlackfin.h b/include/asm-blackfin/arch-common/cdef_LPBlackfin.h index f82ccbe4ec2..90b21e525ba 100644 --- a/include/asm-blackfin/arch-common/cdef_LPBlackfin.h +++ b/include/asm-blackfin/arch-common/cdef_LPBlackfin.h @@ -14,14 +14,11 @@ #endif #include <asm/arch-common/def_LPBlackfin.h> -// Cache & SRAM Memory +/* Cache & SRAM Memory */ #define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS) #define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL) #define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS) #define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR) -/* -#define MMR_TIMEOUT 0xFFE00010 // Memory-Mapped Register Timeout Register -*/ #define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0) #define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1) #define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2) @@ -55,15 +52,8 @@ #define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14) #define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15) #define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND) -/* -#define DTEST_INDEX 0xFFE00304 // Data Test Index Register -*/ #define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0) #define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1) -/* -#define DTEST_DATA2 0xFFE00408 // Data Test Data Register -#define DTEST_DATA3 0xFFE0040C // Data Test Data Register -*/ #define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL) #define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS) #define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR) @@ -100,13 +90,10 @@ #define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14) #define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15) #define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND) -/* -#define ITEST_INDEX 0xFFE01304 // Instruction Test Index Register -*/ #define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0) #define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1) -// Event/Interrupt Registers +/* Event/Interrupt Registers */ #define pEVT0 ((volatile void **)EVT0) #define pEVT1 ((volatile void **)EVT1) #define pEVT2 ((volatile void **)EVT2) @@ -127,24 +114,24 @@ #define pIPEND ((volatile unsigned long *)IPEND) #define pILAT ((volatile unsigned long *)ILAT) -// Core Timer Registers +/* Core Timer Registers */ #define pTCNTL ((volatile unsigned long *)TCNTL) #define pTPERIOD ((volatile unsigned long *)TPERIOD) #define pTSCALE ((volatile unsigned long *)TSCALE) #define pTCOUNT ((volatile unsigned long *)TCOUNT) -// Debug/MP/Emulation Registers +/* Debug/MP/Emulation Registers */ #define pDSPID ((volatile unsigned long *)DSPID) #define pDBGCTL ((volatile unsigned long *)DBGCTL) #define pDBGSTAT ((volatile unsigned long *)DBGSTAT) #define pEMUDAT ((volatile unsigned long *)EMUDAT) -// Trace Buffer Registers +/* Trace Buffer Registers */ #define pTBUFCTL ((volatile unsigned long *)TBUFCTL) #define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT) #define pTBUF ((volatile void **)TBUF) -// Watch Point Control Registers +/* Watch Point Control Registers */ #define pWPIACTL ((volatile unsigned long *)WPIACTL) #define pWPIA0 ((volatile void **)WPIA0) #define pWPIA1 ((volatile void **)WPIA1) @@ -165,13 +152,9 @@ #define pWPDACNT1 ((volatile unsigned long *)WPDACNT1) #define pWPSTAT ((volatile unsigned long *)WPSTAT) -// Performance Monitor Registers +/* Performance Monitor Registers */ #define pPFCTL ((volatile unsigned long *)PFCTL) #define pPFCNTR0 ((volatile unsigned long *)PFCNTR0) #define pPFCNTR1 ((volatile unsigned long *)PFCNTR1) -/* -#define IPRIO 0xFFE02110 // Core Interrupt Priority Register -*/ - #endif /* _CDEF_LPBLACKFIN_H */ diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h index a9baacdfb84..d9d8bf9ba25 100644 --- a/include/asm-blackfin/mem_init.h +++ b/include/asm-blackfin/mem_init.h @@ -26,7 +26,7 @@ CONFIG_MEM_MT48LC64M4A2FB_7E || \ CONFIG_MEM_MT48LC16M8A2TG_75 || \ CONFIG_MEM_MT48LC8M16A2TG_7E || \ - CONFIG_MEM_MT48LC8M32B2B5_7 || \ + CONFIG_MEM_MT48LC8M32B2B5_7 || \ CONFIG_MEM_MT48LC32M8A2_75) #if ( CONFIG_SCLK_HZ > 119402985 ) @@ -105,43 +105,43 @@ #if (CONFIG_MEM_MT48LC16M16A2TG_75) /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ #define SDRAM_CL CL_3 #endif #if (CONFIG_MEM_MT48LC64M4A2FB_7E) /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ #define SDRAM_CL CL_2 #endif #if (CONFIG_MEM_MT48LC16M8A2TG_75) - /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ - #define SDRAM_CL CL_3 + /*SDRAM INFORMATION: */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ + #define SDRAM_CL CL_3 #endif #if (CONFIG_MEM_MT48LC32M8A2_75) - /*SDRAM INFORMATION: */ -#define SDRAM_Tref 64 /* Refresh period in milliseconds */ -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ +/*SDRAM INFORMATION: */ +#define SDRAM_Tref 64 /* Refresh period in milliseconds */ +#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ #define SDRAM_CL CL_3 #endif #if (CONFIG_MEM_MT48LC8M16A2TG_7E) /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ #define SDRAM_CL CL_2 #endif #if (CONFIG_MEM_MT48LC8M32B2B5_7) /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ #define SDRAM_CL CL_3 #endif diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index 7afc1a17fe1..3e165f24956 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -9,13 +9,13 @@ #define CONFIG_STAMP 1 #define CONFIG_BOOTDELAY 5 -#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */ +#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */ -#define CFG_LONGHELP 1 +#define CFG_LONGHELP 1 #define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_LOADADDR 0x01000000 /* default load address */ +#define CONFIG_LOADADDR 0x01000000 /* default load address */ #define CONFIG_BOOTCOMMAND "tftp $(loadaddr) linux" -//#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" +/* #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" */ #define CONFIG_DRIVER_SMC91111 1 #define CONFIG_SMC91111_BASE 0x20310300 @@ -32,12 +32,12 @@ * Boot Mode Set * Blackfin can support several boot modes */ -#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ -#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ -#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */ +#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ +#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ +#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */ /* Define the boot mode */ #define BFIN_BOOT_MODE BF533_BYPASS_BOOT -//#define BFIN_BOOT_MODE BF533_SPI_BOOT +/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */ #define CONFIG_PANIC_HANG 1 @@ -53,46 +53,46 @@ /* Define where the uboot will be loaded by on-chip boot rom */ #define APP_ENTRY 0x00001000 -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 27000000 -/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ -/* 1=CLKIN/2 */ -#define CONFIG_CLKIN_HALF 0 -/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ -/* 1=bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ -/* Values can range from 1-64 */ -#define CONFIG_VCO_MULT 22 -/* CONFIG_CCLK_DIV controls what the core clock divider is */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 27000000 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 22 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 -/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ -/* Values can range from 2-65535 */ -/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ -#define CONFIG_SPI_BAUD 2 -#define CONFIG_SPI_BAUD_INITBLOCK 4 +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ +/* Values can range from 2-65535 */ +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ +#define CONFIG_SPI_BAUD 2 +#define CONFIG_SPI_BAUD_INITBLOCK 4 #if ( CONFIG_CLKIN_HALF == 0 ) -#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) #else -#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) #endif #if (CONFIG_PLL_BYPASS == 0) -#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) -#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) #else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ #endif -#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ -#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ -#define CONFIG_MEM_MT48LC16M16A2TG_75 1 +#define CONFIG_MEM_SIZ 32 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC16M16A2TG_75 1 #define CONFIG_LOADS_ECHO 1 @@ -146,16 +146,16 @@ #define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ /* JFFS Partition offset set */ -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_NUM_BANKS 1 +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 /* 512k reserved for u-boot */ -#define CFG_JFFS2_FIRST_SECTOR 11 +#define CFG_JFFS2_FIRST_SECTOR 11 /* * Stack sizes */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ #define POLL_MODE 1 #define FLASH_TOT_SECT 40 @@ -171,50 +171,50 @@ * I2C settings * By default PF1 is used as SDA and PF0 as SCL on the Stamp board */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ /* * Software (bit-bang) I2C driver configuration */ -#define PF_SCL PF0 -#define PF_SDA PF1 - -#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") -#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") -#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") -#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") -#define I2C_SDA(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SDA; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SDA; \ - asm("ssync;"); \ - } -#define I2C_SCL(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SCL; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SCL; \ - asm("ssync;"); \ - } -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xFE +#define PF_SCL PF0 +#define PF_SDA PF1 + +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE #define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ /* 0xFF, 0x7BB07BB0, 0x22547BB0 */ -/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) -#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ - ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) -#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ - B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) +/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ + ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) +#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ + B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) */ -#define AMGCTLVAL 0xFF -#define AMBCTL0VAL 0x7BB07BB0 -#define AMBCTL1VAL 0xFFC27BB0 +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0x7BB07BB0 +#define AMBCTL1VAL 0xFFC27BB0 #define CONFIG_VDSP 1 diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 353a43c286a..cde2c245c87 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -12,12 +12,12 @@ * Boot Mode Set * Blackfin can support several boot modes */ -#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ -#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ -#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */ +#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ +#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ +#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */ /* Define the boot mode */ #define BFIN_BOOT_MODE BF533_BYPASS_BOOT -//#define BFIN_BOOT_MODE BF533_SPI_BOOT +/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */ #define CONFIG_PANIC_HANG 1 @@ -41,65 +41,61 @@ /* * Board settings - * */ -#define CONFIG_DRIVER_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20300300 +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20300300 /* FLASH/ETHERNET uses the same address range */ -#define SHARED_RESOURCES 1 +#define SHARED_RESOURCES 1 /* Is I2C bit-banged? */ -#define CONFIG_SOFT_I2C 1 +#define CONFIG_SOFT_I2C 1 /* * Software (bit-bang) I2C driver configuration */ -#define PF_SCL PF3 -#define PF_SDA PF2 +#define PF_SCL PF3 +#define PF_SDA PF2 /* * Video splash screen support */ -#define CONFIG_VIDEO 0 +#define CONFIG_VIDEO 0 -#define CONFIG_VDSP 1 +#define CONFIG_VDSP 1 /* * Clock settings - * */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 11059200 -/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ -/* 1=CLKIN/2 */ -#define CONFIG_CLKIN_HALF 0 -/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ -/* 1=bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ -/* Values can range from 1-64 */ -#define CONFIG_VCO_MULT 36 -/* CONFIG_CCLK_DIV controls what the core clock divider is */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 -/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ -/* Values can range from 2-65535 */ -/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ -#define CONFIG_SPI_BAUD 2 +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 11059200 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 36 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ +/* Values can range from 2-65535 */ +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ +#define CONFIG_SPI_BAUD 2 #if (BFIN_BOOT_MODE == BF533_SPI_BOOT) -#define CONFIG_SPI_BAUD_INITBLOCK 4 +#define CONFIG_SPI_BAUD_INITBLOCK 4 #endif - /* * Network settings - * */ #if (CONFIG_DRIVER_SMC91111) @@ -108,92 +104,90 @@ #endif /* network support */ -#define CONFIG_IPADDR 192.168.0.15 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_HOSTNAME STAMP -#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME STAMP +#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs /* To remove hardcoding and enable MAC storage in EEPROM */ -/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ #endif /* CONFIG_DRIVER_SMC91111 */ /* * Flash settings - * */ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_CFI_AMD_RESET -#define CFG_FLASH_BASE 0x20000000 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ +#define CFG_FLASH_BASE 0x20000000 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0x20004000 -#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x20004000 +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_ENV_OFFSET 0x4000 -#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */ +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */ #endif -#define CFG_ENV_SIZE 0x2000 -#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */ #define ENV_IS_EMBEDDED -#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ +#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ #define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ /* JFFS Partition offset set */ #define CFG_JFFS2_FIRST_BANK 0 #define CFG_JFFS2_NUM_BANKS 1 /* 512k reserved for u-boot */ -#define CFG_JFFS2_FIRST_SECTOR 11 +#define CFG_JFFS2_FIRST_SECTOR 11 /* * following timeouts shall be used once the * Flash real protection is enabled */ -#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ +#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ /* * SDRAM settings & memory map - * */ -#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ -#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ #define CONFIG_MEM_MT48LC64M4A2FB_7E 1 #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ #endif -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 #define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024) #define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1) #define CONFIG_LOADADDR 0x01000000 -#define CFG_LOAD_ADDR CONFIG_LOADADDR -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#define CFG_LOAD_ADDR CONFIG_LOADADDR +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ #define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - 0x40000) -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) /* Check to make sure everything fits in SDRAM */ #if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE) @@ -201,17 +195,17 @@ #endif #if ( CONFIG_CLKIN_HALF == 0 ) -#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) #else -#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) #endif #if (CONFIG_PLL_BYPASS == 0) -#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) -#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) #else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ #endif #if (BFIN_BOOT_MODE == BF533_SPI_BOOT) @@ -221,71 +215,71 @@ #undef CONFIG_SPI_FLASH_FAST_READ #endif #endif + /* * Command settings - * */ -#define CFG_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) -#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */ +#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */ #endif - /* configuration lookup from the BOOTP/DHCP server, */ - /* but not try to load any image using TFTP */ -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ +/* configuration lookup from the BOOTP/DHCP server, */ +/* but not try to load any image using TFTP */ + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) -#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_BOOTCOMMAND "run ramboot" #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) -#define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000" +#define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000" #endif -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600" #if (CONFIG_DRIVER_SMC91111) -#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ - CFG_CMD_PING | \ - CFG_CMD_ELF | \ - CFG_CMD_CACHE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DATE) +#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DATE) #else -#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ - CFG_CMD_ELF | \ - CFG_CMD_CACHE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DATE) - +#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ + CFG_CMD_ELF | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DATE) #endif #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) #if (CONFIG_DRIVER_SMC91111) #define CONFIG_EXTRA_ENV_SETTINGS \ - "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \ - "$(rootpath) console=ttyBF0,57600\0" \ - "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ - "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \ - "ramboot=tftpboot $(loadaddr) linux; " \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \ + "$(rootpath) console=ttyBF0,57600\0" \ + "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ + "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux; " \ "run ramargs;run addip;bootelf\0" \ - "nfsboot=tftpboot $(loadaddr) linux; " \ + "nfsboot=tftpboot $(loadaddr) linux; " \ "run nfsargs;run addip;bootelf\0" \ - "flashboot=bootm 0x20100000\0" \ - "update=tftpboot $(loadaddr) u-boot.bin; " \ - "protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \ - "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \ - "" + "flashboot=bootm 0x20100000\0" \ + "update=tftpboot $(loadaddr) u-boot.bin; " \ + "protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \ + "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \ + "" #else #define CONFIG_EXTRA_ENV_SETTINGS \ - "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ - "flashboot=bootm 0x20100000\0" \ - "" + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "flashboot=bootm 0x20100000\0" \ + " #endif #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) @@ -328,40 +322,39 @@ /* * Console settings - * */ -#define CONFIG_BAUDRATE 57600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_BAUDRATE 57600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #if (BFIN_BOOT_MODE == BF533_SPI_BOOT) #if (BFIN_CPU == ADSP_BF531) -#define CFG_PROMPT "serial_bf531> " /* Monitor Command Prompt */ +#define CFG_PROMPT "serial_bf531> " /* Monitor Command Prompt */ #elif (BFIN_CPU == ADSP_BF532) -#define CFG_PROMPT "serial_bf532> " /* Monitor Command Prompt */ +#define CFG_PROMPT "serial_bf532> " /* Monitor Command Prompt */ #else -#define CFG_PROMPT "serial_bf533> " /* Monitor Command Prompt */ +#define CFG_PROMPT "serial_bf533> " /* Monitor Command Prompt */ #endif #else #if (BFIN_CPU == ADSP_BF531) -#define CFG_PROMPT "bf531> " /* Monitor Command Prompt */ +#define CFG_PROMPT "bf531> " /* Monitor Command Prompt */ #elif (BFIN_CPU == ADSP_BF532) -#define CFG_PROMPT "bf532> " /* Monitor Command Prompt */ +#define CFG_PROMPT "bf532> " /* Monitor Command Prompt */ #else -#define CFG_PROMPT "bf533> " /* Monitor Command Prompt */ +#define CFG_PROMPT "bf533> " /* Monitor Command Prompt */ #endif #endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_LOADS_ECHO 1 +#define CONFIG_LOADS_ECHO 1 /* * I2C settings @@ -369,30 +362,30 @@ */ #if (CONFIG_SOFT_I2C) -#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") -#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") -#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") -#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") -#define I2C_SDA(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SDA; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SDA; \ - asm("ssync;"); \ - } -#define I2C_SCL(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SCL; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SCL; \ - asm("ssync;"); \ - } -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xFE +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE #endif /* CONFIG_SOFT_I2C */ /* @@ -400,48 +393,48 @@ */ /* Enabled below option for CF support */ -/* #define CONFIG_STAMP_CF 1 */ +/* #define CONFIG_STAMP_CF 1 */ #if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE) -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_DOS_PARTITION 1 /* * IDE/ATA stuff */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ -#define CFG_ATA_BASE_ADDR 0x20200000 -#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_BASE_ADDR 0x20200000 +#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ -#define CFG_ATA_STRIDE 2 +#define CFG_ATA_STRIDE 2 #endif /* * Miscellaneous configurable options */ -#define CFG_HZ 1000 /* 1ms time tick */ +#define CFG_HZ 1000 /* 1ms time tick */ -#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ +#define CFG_BOOTM_LEN 0x4000000/* Large Image Length, set to 64 Meg */ -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ #define CONFIG_SPI #ifdef CONFIG_VIDEO #if (CONFIG_VIDEO) -#define CONFIG_SPLASH_SCREEN 1 -#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_SPLASH_SCREEN 1 +#define CONFIG_SILENT_CONSOLE 1 #else #undef CONFIG_VIDEO #endif @@ -450,19 +443,19 @@ /* * FLASH organization and environment definitions */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */ /* 0xFF, 0xBBC3BBc3, 0x99B39983 */ -/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) -#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ - B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) -#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ - B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) +/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ + B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) +#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ + B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) */ -#define AMGCTLVAL 0xFF -#define AMBCTL0VAL 0xBBC3BBC3 -#define AMBCTL1VAL 0x99B39983 -#define CF_AMBCTL1VAL 0x99B3ffc2 +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0xBBC3BBC3 +#define AMBCTL1VAL 0x99B39983 +#define CF_AMBCTL1VAL 0x99B3ffc2 #ifdef CONFIG_VDSP #define ET_EXEC_VDSP 0x8 @@ -471,5 +464,4 @@ #define VDSP_ENTRY_ADDR 0xFFA00000 #endif - #endif |