diff options
Diffstat (limited to 'include')
159 files changed, 2657 insertions, 12031 deletions
diff --git a/include/bitfield.h b/include/bitfield.h index b884c74600..a59f3c279a 100644 --- a/include/bitfield.h +++ b/include/bitfield.h @@ -27,6 +27,12 @@ * old = bitfield_extract(old_reg_val, 10, 5); * new_reg_val = bitfield_replace(old_reg_val, 10, 5, new); * + * or + * + * mask = bitfield_mask(10, 5); + * old = bitfield_extract_by_mask(old_reg_val, mask); + * new_reg_val = bitfield_replace_by_mask(old_reg_val, mask, new); + * * The numbers 10 and 5 could for example come from data * tables which describe all bitfields in all registers. */ @@ -56,3 +62,29 @@ static inline uint bitfield_replace(uint reg_val, uint shift, uint width, return (reg_val & ~mask) | ((bitfield_val << shift) & mask); } + +/* Produces a shift of the bitfield given a mask */ +static inline uint bitfield_shift(uint mask) +{ + return mask ? ffs(mask) - 1 : 0; +} + +/* Extract the value of a bitfield found within a given register value */ +static inline uint bitfield_extract_by_mask(uint reg_val, uint mask) +{ + uint shift = bitfield_shift(mask); + + return (reg_val & mask) >> shift; +} + +/* + * Replace the value of a bitfield found within a given register value + * Returns the newly modified uint value with the replaced field. + */ +static inline uint bitfield_replace_by_mask(uint reg_val, uint mask, + uint bitfield_val) +{ + uint shift = bitfield_shift(mask); + + return (reg_val & ~mask) | ((bitfield_val << shift) & mask); +} diff --git a/include/common.h b/include/common.h index c12f402f77..ecb1f0682e 100644 --- a/include/common.h +++ b/include/common.h @@ -826,6 +826,9 @@ int gzwrite(unsigned char *src, int len, u64 startoffs, u64 szexpected); +/* lib/lz4_wrapper.c */ +int ulz4fn(const void *src, size_t srcn, void *dst, size_t *dstn); + /* lib/qsort.c */ void qsort(void *base, size_t nmemb, size_t size, int(*compar)(const void *, const void *)); @@ -974,102 +977,6 @@ int cpu_release(int nr, int argc, char * const argv[]); #define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1)) /* - * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It - * is used to align DMA buffers. - */ -#ifndef __ASSEMBLY__ -#include <asm/cache.h> -#endif - -/* - * The ALLOC_CACHE_ALIGN_BUFFER macro is used to allocate a buffer on the - * stack that meets the minimum architecture alignment requirements for DMA. - * Such a buffer is useful for DMA operations where flushing and invalidating - * the cache before and after a read and/or write operation is required for - * correct operations. - * - * When called the macro creates an array on the stack that is sized such - * that: - * - * 1) The beginning of the array can be advanced enough to be aligned. - * - * 2) The size of the aligned portion of the array is a multiple of the minimum - * architecture alignment required for DMA. - * - * 3) The aligned portion contains enough space for the original number of - * elements requested. - * - * The macro then creates a pointer to the aligned portion of this array and - * assigns to the pointer the address of the first element in the aligned - * portion of the array. - * - * Calling the macro as: - * - * ALLOC_CACHE_ALIGN_BUFFER(uint32_t, buffer, 1024); - * - * Will result in something similar to saying: - * - * uint32_t buffer[1024]; - * - * The following differences exist: - * - * 1) The resulting buffer is guaranteed to be aligned to the value of - * ARCH_DMA_MINALIGN. - * - * 2) The buffer variable created by the macro is a pointer to the specified - * type, and NOT an array of the specified type. This can be very important - * if you want the address of the buffer, which you probably do, to pass it - * to the DMA hardware. The value of &buffer is different in the two cases. - * In the macro case it will be the address of the pointer, not the address - * of the space reserved for the buffer. However, in the second case it - * would be the address of the buffer. So if you are replacing hard coded - * stack buffers with this macro you need to make sure you remove the & from - * the locations where you are taking the address of the buffer. - * - * Note that the size parameter is the number of array elements to allocate, - * not the number of bytes. - * - * This macro can not be used outside of function scope, or for the creation - * of a function scoped static buffer. It can not be used to create a cache - * line aligned global buffer. - */ -#define PAD_COUNT(s, pad) (((s) - 1) / (pad) + 1) -#define PAD_SIZE(s, pad) (PAD_COUNT(s, pad) * pad) -#define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad) \ - char __##name[ROUND(PAD_SIZE((size) * sizeof(type), pad), align) \ - + (align - 1)]; \ - \ - type *name = (type *) ALIGN((uintptr_t)__##name, align) -#define ALLOC_ALIGN_BUFFER(type, name, size, align) \ - ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, 1) -#define ALLOC_CACHE_ALIGN_BUFFER_PAD(type, name, size, pad) \ - ALLOC_ALIGN_BUFFER_PAD(type, name, size, ARCH_DMA_MINALIGN, pad) -#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \ - ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) - -/* - * DEFINE_CACHE_ALIGN_BUFFER() is similar to ALLOC_CACHE_ALIGN_BUFFER, but it's - * purpose is to allow allocating aligned buffers outside of function scope. - * Usage of this macro shall be avoided or used with extreme care! - */ -#define DEFINE_ALIGN_BUFFER(type, name, size, align) \ - static char __##name[ALIGN(size * sizeof(type), align)] \ - __aligned(align); \ - \ - static type *name = (type *)__##name -#define DEFINE_CACHE_ALIGN_BUFFER(type, name, size) \ - DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) - -#ifndef __ASSEMBLY__ -#include <malloc.h> - -static inline void *malloc_cache_aligned(size_t size) -{ - return memalign(ARCH_DMA_MINALIGN, ALIGN(size, ARCH_DMA_MINALIGN)); -} -#endif - -/* * check_member() - Check the offset of a structure member * * @structure: Name of structure (e.g. global_data) diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 9ed6c61ab7..17bd18031d 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -406,7 +406,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ -#define CONFIG_SYS_NAND_QUIET_TEST 1 #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index cd5b3e2ada..5b61b56a4e 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -759,7 +759,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg /* Enable VSC9953 L2 Switch driver on T1040 SoC */ #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) #define CONFIG_VSC9953 -#define CONFIG_VSC9953_CMD +#define CONFIG_CMD_ETHSW #ifdef CONFIG_T1040RDB #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index e89c49e1e3..3cf768e662 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -70,6 +70,7 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ "boot_fdt=try\0" \ "bootpart=0:2\0" \ "bootdir=/boot\0" \ @@ -80,15 +81,8 @@ "uuid_disk=${uuid_gpt_disk};" \ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ "optargs=\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 ro\0" \ - "mmcrootfstype=ext4 rootwait\0" \ "ramroot=/dev/ram0 rw\0" \ "ramrootfstype=ext2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ "spiroot=/dev/mtdblock4 rw\0" \ "spirootfstype=jffs2\0" \ "spisrcaddr=0xe0000\0" \ @@ -112,7 +106,7 @@ "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "mmcloados=run mmcargs; " \ + "mmcloados=run args_mmc; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ "bootz ${loadaddr} - ${fdtaddr}; " \ diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h new file mode 100644 index 0000000000..f655e69f90 --- /dev/null +++ b/include/configs/am335x_sl50.h @@ -0,0 +1,138 @@ +/* + * am335x_sl50.h + * + * Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_AM335X_EVM_H +#define __CONFIG_AM335X_EVM_H + +#include <configs/ti_am335x_common.h> +#undef CONFIG_BOOTDELAY + +#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_FIT +# define CONFIG_FIT +#endif +# define CONFIG_TIMESTAMP +# define CONFIG_LZO +#endif + +#define CONFIG_SYS_BOOTM_LEN (16 << 20) + +/*#define CONFIG_MACH_TYPE 3589 Until the next sync */ +#define CONFIG_BOARD_LATE_INIT + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifndef CONFIG_SPL_BUILD + +#include <config_distro_defaults.h> + +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x80000000\0" \ + "pxefile_addr_r=0x80100000\0" \ + "kernel_addr_r=0x82000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x88080000\0" \ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#define AM335XX_BOARD_FDTFILE \ + "fdtfile=am335x-sl50.dtb\0" \ + +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + AM335XX_BOARD_FDTFILE \ + MEM_LAYOUT_ENV_SETTINGS \ + BOOTENV + +#endif + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + +/* PMIC support */ +#define CONFIG_POWER_TPS65217 +#define CONFIG_POWER_TPS65910 + +/* SPL */ +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT + +/* Bootcount using the RTC block */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_BOOTCOUNT_AM33XX +#define CONFIG_SYS_BOOTCOUNT_BE + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#ifndef CONFIG_SPL_USBETH_SUPPORT +/* To support eMMC booting */ +#define CONFIG_STORAGE_EMMC +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 +#endif + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) +/* Remove other SPL modes. */ +#undef CONFIG_SPL_YMODEM_SUPPORT +#undef CONFIG_SPL_NAND_SUPPORT +#undef CONFIG_SPL_MMC_SUPPORT +#define CONFIG_ENV_IS_NOWHERE +#undef CONFIG_ENV_IS_IN_NAND +/* disable host part of MUSB in SPL */ +#undef CONFIG_MUSB_HOST +/* disable EFI partitions and partition UUID support */ +#undef CONFIG_PARTITION_UUIDS +#undef CONFIG_EFI_PARTITION +/* General network SPL */ +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" +#endif + +#if defined(CONFIG_EMMC_BOOT) +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET 0x0 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#endif + +/* Network. */ +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC + +#endif /* ! __CONFIG_AM335X_SL50_H */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 15fa3e3fec..67d5c48dde 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -216,6 +216,7 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ "fdtfile=undefined\0" \ "bootpart=0:2\0" \ "bootdir=/boot\0" \ @@ -225,18 +226,11 @@ "uuid_disk=${uuid_gpt_disk};" \ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ "optargs=\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ "usbroot=/dev/sda2 rw\0" \ "usbrootfstype=ext4 rootwait\0" \ "usbdev=0\0" \ "ramroot=/dev/ram0 rw\0" \ "ramrootfstype=ext2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ "usbargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${usbroot} " \ @@ -268,7 +262,7 @@ "if run loadimage; then " \ "run loadfdt; " \ "echo Booting from mmc${mmcdev} ...; " \ - "run mmcargs; " \ + "run args_mmc; " \ "bootz ${loadaddr} - ${fdtaddr}; " \ "fi;" \ "fi;\0" \ @@ -335,6 +329,7 @@ #define CONFIG_DRIVER_TI_CPSW #define CONFIG_PHYLIB +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_NET_VCI_STRING "AM43xx U-Boot SPL" diff --git a/include/configs/apf27.h b/include/configs/apf27.h index 43fbdd3d11..49fbcac776 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -317,6 +317,8 @@ #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */ #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */ diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index 20afdd6bc0..f03297e137 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -189,6 +189,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0x7f diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 437a745414..b08f341227 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -49,6 +49,10 @@ /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 +/* CPU Errata */ +#define CONFIG_ARM_ERRATA_773022 +#define CONFIG_ARM_ERRATA_774769 + /* Power */ #define CONFIG_POWER #define CONFIG_POWER_I2C diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 3d6b0ae0c3..a5990cec03 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -53,6 +53,13 @@ #define CONFIG_CMD_DHCP #ifdef CONFIG_SYS_USE_MMC + +#ifdef CONFIG_ENV_IS_IN_MMC +/* Use raw reserved sectors to save environment */ +#define CONFIG_ENV_OFFSET 0x2000 +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#else /* u-boot env in sd/mmc card */ #define CONFIG_ENV_IS_IN_FAT #define CONFIG_FAT_WRITE @@ -60,6 +67,7 @@ #define FAT_ENV_DEVICE_AND_PART "0" #define FAT_ENV_FILE "uboot.env" #define CONFIG_ENV_SIZE 0x4000 +#endif #define CONFIG_BOOTCOMMAND "if test ! -n ${dtb_name}; then " \ "setenv dtb_name at91-${board_name}.dtb; " \ diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h deleted file mode 100644 index 124a7663d6..0000000000 --- a/include/configs/balloon3.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Balloon3 configuration file - * - * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ -#define CONFIG_BALLOON3 1 /* Balloon3 board */ - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_MALLOC_LEN (128*1024) -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_BOOTCOMMAND \ - "fpga load 0x0 0x50000 0x62638; " \ - "if usb reset && fatload usb 0 0xa4000000 uImage; then " \ - "bootm 0xa4000000; " \ - "fi; " \ - "bootm 0xd0000;" -#define CONFIG_BOOTARGS "console=tty0 console=ttyS2,115200" -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_TEXT_BASE 0x0 -#define CONFIG_LZMA /* LZMA compression support */ - -/* - * Serial Console Configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_STUART 1 -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* - * Bootloader Components Configuration - */ -#undef CONFIG_CMD_ENV -#define CONFIG_CMD_USB -#define CONFIG_CMD_FPGA_LOADMK -#undef CONFIG_LCD - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#endif - -/* - * HUSH Shell Configuration - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP -#undef CONFIG_SYS_PROMPT -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " -#else -#endif -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ - -/* - * DRAM Map - */ -#define CONFIG_NR_DRAM_BANKS 3 /* 3 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x18000000 /* 384 MB DRAM */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xa1000000 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR \ - (PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048) - -/* - * NOR FLASH - */ -#ifdef CONFIG_CMD_FLASH -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 -#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_ENV_IS_IN_FLASH -#else -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_NOWHERE -#endif - -#define CONFIG_SYS_MONITOR_BASE 0x000000 -#define CONFIG_SYS_MONITOR_LEN 0x40000 - -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x10000 - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPSR0_VAL 0x307dc7fd -#define CONFIG_SYS_GPSR1_VAL 0x03cffa4e -#define CONFIG_SYS_GPSR2_VAL 0x7131c000 -#define CONFIG_SYS_GPSR3_VAL 0x01e1f3ff - -#define CONFIG_SYS_GPCR0_VAL 0x0 -#define CONFIG_SYS_GPCR1_VAL 0x0 -#define CONFIG_SYS_GPCR2_VAL 0x0 -#define CONFIG_SYS_GPCR3_VAL 0x0 - -#define CONFIG_SYS_GPDR0_VAL 0xc0f98e02 -#define CONFIG_SYS_GPDR1_VAL 0xfcffa8b7 -#define CONFIG_SYS_GPDR2_VAL 0x22e3ffff -#define CONFIG_SYS_GPDR3_VAL 0x000201fe - -#define CONFIG_SYS_GAFR0_L_VAL 0x96c00000 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5e5459b -#define CONFIG_SYS_GAFR1_L_VAL 0x699b759a -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a5aa -#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x01f9a6aa -#define CONFIG_SYS_GAFR3_L_VAL 0x54510003 -#define CONFIG_SYS_GAFR3_U_VAL 0x00001599 - -#define CONFIG_SYS_PSSR_VAL 0x30 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0xffffffff -#define CONFIG_SYS_CCCR 0x00000290 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x7ff07ff8 -#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0 -#define CONFIG_SYS_MSC2_VAL 0x74a42491 -#define CONFIG_SYS_MDCNFG_VAL 0x89d309d3 -#define CONFIG_SYS_MDREFR_VAL 0x001d8018 -#define CONFIG_SYS_MDMRS_VAL 0x00220022 -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00014307 -#define CONFIG_SYS_MCMEM1_VAL 0x00014307 -#define CONFIG_SYS_MCATT0_VAL 0x0001c787 -#define CONFIG_SYS_MCATT1_VAL 0x0001c787 -#define CONFIG_SYS_MCIO0_VAL 0x0001430f -#define CONFIG_SYS_MCIO1_VAL 0x0001430f - -/* - * LCD - */ -#ifdef CONFIG_LCD -#define CONFIG_BALLOON3LCD -#define CONFIG_VIDEO_LOGO -#define CONFIG_CMD_BMP -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) -#endif - -/* - * USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "balloon3" -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#endif - -/* - * FPGA - */ -#ifdef CONFIG_CMD_FPGA -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_SPARTAN3 -#define CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_SYS_FPGA_WAIT 1000 -#define CONFIG_MAX_FPGA_DEVICES 1 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 838ef1f00a..c6960920b2 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -14,18 +14,16 @@ /* ------------------------------------------------------------------------- */ #define BUR_COMMON_ENV \ "usbscript=usb start && fatload usb 0 0x80000000 usbscript.img && source\0" \ -"defaultip=192.168.60.253\0" \ -"defaultsip=192.168.60.254\0" \ +"brdefaultip=if test -r ${ipaddr}; then; else" \ +" setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;" \ +" setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;\0" \ "netconsole=echo switching to network console ...; " \ -"if dhcp; then setenv ncip ${serverip}; " \ -"else " \ -"setenv ncip 192.168.60.254; setenv serverip 192.168.60.254; " \ -"setenv gatewayip 192.168.60.254; setenv ipaddr 192.168.60.1; " \ -"fi; " \ +"if dhcp; then; else run brdefaultip; fi; setenv ncip ${serverip}; " \ "setcurs 1 9; lcdputs myip; setcurs 10 9; lcdputs ${ipaddr};" \ "setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \ "setenv stdout nc;setenv stdin nc;setenv stderr nc\0" +#define CONFIG_PREBOOT "run brdefaultip" #define CONFIG_CMD_TIME #define CONFIG_SYS_GENERIC_BOARD diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 92930c8f72..e0aa4b0894 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -33,17 +33,14 @@ #define CONFIG_CMD_BMODE /* Thermal support */ -#define CONFIG_IMX6_THERMAL - -#define CONFIG_CMD_FUSE -#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL) -#define CONFIG_MXC_OCOTP -#endif +#define CONFIG_IMX_THERMAL /* I2C Configs */ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_SPEED 100000 @@ -68,6 +65,20 @@ #define CONFIG_USB_KEYBOARD #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP +#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED + +#define CONFIG_USB_GADGET +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 +#define CONFIG_G_DNL_MANUFACTURER "Congatec" + /* Framebuffer */ #define CONFIG_VIDEO #define CONFIG_VIDEO_IPUV3 diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 12734a10bf..05132047b7 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -198,6 +198,8 @@ /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_MXC_I2C3_SPEED 400000 diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 281d614de1..e5fb474afc 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -147,7 +147,6 @@ /* * Board NAND Info. */ -#define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index 33b22a72b9..f3d1f4352e 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -36,6 +36,8 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap.h> +#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517 + /* * Display CPU and Board information */ @@ -66,7 +68,7 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) /* @@ -152,7 +154,6 @@ /* * Board NAND Info. */ -#define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ @@ -170,6 +171,7 @@ "loadaddr=0x82000000\0" \ "baudrate=115200\0" \ "console=ttyO2,115200n8\0" \ + "netretry=yes\0" \ "mpurate=auto\0" \ "vram=12M\0" \ "dvimode=1024x768MR-16@60\0" \ @@ -274,6 +276,8 @@ #define CONFIG_SMC911X #define CONFIG_SMC911X_32_BIT #define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20)) +#define CONFIG_ARP_TIMEOUT 200UL +#define CONFIG_NET_RETRY_COUNT 5 #endif /* CONFIG_CMD_NET */ /* additions for new relocation code, must be added to all boards */ diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h deleted file mode 100644 index 82f4fe7d3c..0000000000 --- a/include/configs/cpu9260.h +++ /dev/null @@ -1,485 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - * Ilko Iliev <www.ronetix.at> - * - * (C) Copyright 2009 - * Eric Benard <eric@eukrea.com> - * - * Configuration settings for the Eukrea CPU9260 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* to be removed once maemory-map.h is fixed */ -#define AT91_BASE_SYS 0xffffe800 -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) - -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 - -#if defined(CONFIG_CPU9G20) -#define CONFIG_AT91SAM9G20 -#elif defined(CONFIG_CPU9260) -#define CONFIG_AT91SAM9260 -#else -#error "Unknown board" -#endif - -#include <asm/arch/hardware.h> - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#if defined(CONFIG_NANDBOOT) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TEXT_BASE 0x23f00000 -#else -#define CONFIG_SYS_TEXT_BASE 0x00000000 -#endif - -/* clocks */ -#if defined(CONFIG_CPU9G20) -#define MASTER_PLL_DIV 0x01 -#define MASTER_PLL_MUL 0x2B -#elif defined(CONFIG_CPU9260) -#define MASTER_PLL_DIV 0x09 -#define MASTER_PLL_MUL 0x61 -#endif - -/* CKGR_MOR - enable main osc. */ -#define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOSCEN | \ - (255 << 8)) /* Main Oscillator Start-up Time */ -#if defined(CONFIG_CPU9G20) -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) -#elif defined(CONFIG_CPU9260) -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_OUT | \ - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) -#endif - -#if defined(CONFIG_CPU9G20) -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_6 | \ - AT91_PMC_PDIV_2) -#define CONFIG_SYS_MCKR2_VAL \ - CONFIG_SYS_MCKR1_VAL -#elif defined(CONFIG_CPU9260) -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) -#endif - -/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 -/* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 - -/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ -#define CONFIG_SYS_MATRIX_EBICSA_VAL \ - (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \ - AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V) - -/* SDRAM */ -/* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL -/* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x287 -/* SDRAMC_CR - Configuration register*/ -#if defined(CONFIG_CPU9G20) -#define CONFIG_SYS_SDRC_CR_VAL_64MB \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_2 | \ - AT91_SDRAMC_DBW_32 | \ - (2 << 8) | /* Write Recovery Delay */ \ - (9 << 12) | /* Row Cycle Delay */ \ - (3 << 16) | /* Row Precharge Delay */ \ - (3 << 20) | /* Row to Column Delay */ \ - (6 << 24) | /* Active to Precharge Delay */ \ - (10 << 28)) /* Exit Self Refresh to Active Delay */ - -#define CONFIG_SYS_SDRC_CR_VAL_128MB \ - (AT91_SDRAMC_NC_10 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_2 | \ - AT91_SDRAMC_DBW_32 | \ - (2 << 8) | /* Write Recovery Delay */ \ - (9 << 12) | /* Row Cycle Delay */ \ - (3 << 16) | /* Row Precharge Delay */ \ - (3 << 20) | /* Row to Column Delay */ \ - (6 << 24) | /* Active to Precharge Delay */ \ - (10 << 28)) /* Exit Self Refresh to Active Delay */ -#elif defined(CONFIG_CPU9260) -#define CONFIG_SYS_SDRC_CR_VAL_64MB \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_2 | \ - AT91_SDRAMC_DBW_32 | \ - (2 << 8) | /* Write Recovery Delay */ \ - (7 << 12) | /* Row Cycle Delay */ \ - (2 << 16) | /* Row Precharge Delay */ \ - (2 << 20) | /* Row to Column Delay */ \ - (5 << 24) | /* Active to Precharge Delay */ \ - (8 << 28)) /* Exit Self Refresh to Active Delay */ - -#define CONFIG_SYS_SDRC_CR_VAL_128MB \ - (AT91_SDRAMC_NC_10 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_2 | \ - AT91_SDRAMC_DBW_32 | \ - (2 << 8) | /* Write Recovery Delay */ \ - (7 << 12) | /* Row Cycle Delay */ \ - (2 << 16) | /* Row Precharge Delay */ \ - (2 << 20) | /* Row to Column Delay */ \ - (5 << 24) | /* Active to Precharge Delay */ \ - (8 << 28)) /* Exit Self Refresh to Active Delay */ -#endif - -/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ - -/* setup SMC0, CS0 (NOR Flash) - 16-bit */ -#if defined(CONFIG_CPU9G20) -#define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \ - AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) | \ - AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ - AT91_SMC_MODE_DBW_16 | \ - AT91_SMC_MODE_TDF | \ - AT91_SMC_MODE_TDF_CYCLE(3)) -#elif defined(CONFIG_CPU9260) -#define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \ - AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) | \ - AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ - AT91_SMC_MODE_DBW_16 | \ - AT91_SMC_MODE_TDF | \ - AT91_SMC_MODE_TDF_CYCLE(2)) -#endif - -/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ - (AT91_RSTC_KEY | \ - AT91_RSTC_CR_PROCRST | \ - AT91_RSTC_MR_ERSTL(1) | \ - AT91_RSTC_MR_ERSTL(2)) - -/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ - AT91_WDT_MR_WDV(0xfff) | \ - AT91_WDT_MR_WDDIS | \ - AT91_WDT_MR_WDD(0xfff)) - -/* - * Hardware drivers - */ -#define CONFIG_AT91SAM9_WATCHDOG -#define CONFIG_AT91_GPIO -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -#define CONFIG_BOOTDELAY 3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NAND -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_CMD_MII - -/* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M) -#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) -#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB -#else -#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) -#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB -#endif - -/* NAND flash */ -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 -#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PC(13) -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) - -/* NOR flash */ -#if defined(CONFIG_NANDBOOT) -#define CONFIG_SYS_NO_FLASH -#else -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define PHYS_FLASH_1 0x10000000 -#define PHYS_FLASH_2 0x12000000 -#define CONFIG_SYS_FLASH_BANKS_LIST \ - { PHYS_FLASH_1, PHYS_FLASH_2 } -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_SECT (255+4) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#endif - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY -#define CONFIG_AT91_WANTS_COMMON_PHY - -/* LEDS */ -/* Status LED */ -#define CONFIG_STATUS_LED -#define CONFIG_BOARD_SPECIFIC_LED -#define STATUS_LED_RED 0 -#define STATUS_LED_GREEN 1 -#define STATUS_LED_YELLOW 2 -#define STATUS_LED_BLUE 3 -/* Red */ -#define STATUS_LED_BIT STATUS_LED_RED -#define STATUS_LED_STATE STATUS_LED_OFF -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -/* Green */ -#define STATUS_LED_BIT1 STATUS_LED_GREEN -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) -/* Yellow */ -#define STATUS_LED_BIT2 STATUS_LED_YELLOW -#define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) -/* Blue */ -#define STATUS_LED_BIT3 STATUS_LED_BLUE -#define STATUS_LED_STATE3 STATUS_LED_ON -#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2) -/* Optional value */ -#define STATUS_LED_BOOT STATUS_LED_BIT - -#define CONFIG_RED_LED AT91_PIO_PORTC, 11 -#define CONFIG_GREEN_LED AT91_PIO_PORTC, 12 -#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7 -#define CONFIG_BLUE_LED AT91_PIO_PORTC, 9 - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#if defined(CONFIG_CPU9G20) -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20" -#elif defined(CONFIG_CPU9260) -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#endif -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024) - -#if defined(CONFIG_NANDBOOT) -#define CONFIG_SYS_USE_NANDFLASH -#undef CONFIG_SYS_USE_FLASH -#else -#define CONFIG_SYS_USE_FLASH -#undef CONFIG_SYS_USE_NANDFLASH -#endif - -#if defined(CONFIG_CPU9G20) -#define CONFIG_SYS_BASEDIR "cpu9G20" -#elif defined(CONFIG_CPU9260) -#define CONFIG_SYS_BASEDIR "cpu9260" -#endif - -#if defined(CONFIG_SYS_USE_FLASH) -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BOOTCOMMAND "run flashboot" - -#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand" -#define MTDPARTS_DEFAULT \ - "mtdparts=physmap-flash.0:" \ - "256k(u-boot)ro," \ - "128k(u-boot-env)ro," \ - "1792k(kernel)," \ - "-(rootfs);" \ - "atmel_nand:-(nand)" - -#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 " - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "partition=nand0,0\0" \ - "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ - "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \ - "run ramargs;bootm 22000000\0" \ - "flashboot=run ramargs;bootm 0x10060000\0" \ - "basedir=" CONFIG_SYS_BASEDIR "\0" \ - "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \ - "off 0x10000000 0x1003ffff;erase 0x10000000 " \ - "0x1003ffff;cp.b 0x24000000 0x10000000 " \ - "$(filesize)\0" \ - "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \ - " 0x10060000 0x1021ffff;erase 0x10060000 " \ - "0x1021ffff;cp.b 0x24000000 0x10060000 " \ - "$(filesize)\0" \ - "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \ - "protect off 0x10220000 0x13ffffff;erase " \ - "0x10220000 0x13ffffff;cp.b 0x24000000 " \ - "0x10220000 $(filesize)\0" \ - "" -#elif defined(CONFIG_NANDBOOT) -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_OFFSET_REDUND 0x80000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BOOTCOMMAND "run flashboot" - -#define MTDIDS_DEFAULT "nand0=atmel_nand" -#define MTDPARTS_DEFAULT \ - "mtdparts=atmel_nand:" \ - "128k(bootstrap)ro," \ - "256k(u-boot)ro," \ - "128k(u-boot-env)ro," \ - "128k(u-boot-env2)ro," \ - "2M(kernel)," \ - "-(rootfs)" - -#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \ - "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "partition=nand0,5\0" \ - "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ - "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \ - "run ramargs;bootm 22000000\0" \ - "flashboot=run ramargs; nand read 0x22000000 0xA0000 " \ - "0x200000; bootm 0x22000000\0" \ - "basedir=" CONFIG_SYS_BASEDIR "\0" \ - "u-boot=u-boot-eukrea-cpu9260.bin\0" \ - "kernel=uImage-eukrea-cpu9260.bin\0" \ - "rootfs=image-eukrea-cpu9260.ubi\0" \ - "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \ - "nand erase 20000 40000; " \ - "nand write ${loadaddr} 20000 40000\0" \ - "updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \ - "nand erase a0000 200000; " \ - "nand write ${loadaddr} a0000 200000\0" \ - "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \ - "nand erase 2a0000 fd60000; " \ - "nand write ${loadaddr} 2a0000 ${filesize}\0" -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SILENT_CONSOLE -#define CONFIG_NETCONSOLE - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \ - GENERATED_GBL_DATA_SIZE) - -#endif diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h deleted file mode 100644 index 29cd842cec..0000000000 --- a/include/configs/cpuat91.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * CPUAT91 by (C) Copyright 2006-2010 Eric Benard - * eric@eukrea.com - * - * Configuration settings for the CPUAT91 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_CPUAT91_H -#define _CONFIG_CPUAT91_H - -#include <linux/sizes.h> - -#ifdef CONFIG_RAMBOOT -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TEXT_BASE 0x21F00000 -#else -#define CONFIG_BOOTDELAY 1 -#define CONFIG_SYS_TEXT_BASE 0 -#endif - -#define AT91C_XTAL_CLOCK 18432000 -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) -#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3) -#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) - -#define CONFIG_AT91RM9200 -#define CONFIG_CPUAT91 -#define USE_920T_MMU - -#include <asm/hardware.h> /* needed for port definitions */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_BOARD_EARLY_INIT_F - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_USE_MAIN_OSCILLATOR -/* flash */ -#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 -#define CONFIG_SYS_MC_PUP_VAL 0x00000000 -#define CONFIG_SYS_MC_PUER_VAL 0x00000000 -#define CONFIG_SYS_MC_ASR_VAL 0x00000000 -#define CONFIG_SYS_MC_AASR_VAL 0x00000000 -#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 -#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ -#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB */ -#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock */ - -/* sdram */ -#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as D16/D31 */ -#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 -#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 -#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define CONFIG_SYS_SDRC_CR_VAL 0x2188C155 /* set up the SDRAM */ -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */ -#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */ -#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID 0/* ignored in arm */ - -#undef CONFIG_HARD_I2C -#define AT91_PIN_SDA (1<<25) -#define AT91_PIN_SCL (1<<26) - -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 - -#define I2C_INIT i2c_init_board(); -#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr); -#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder); -#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0) -#define I2C_SDA(bit) \ - if (bit) \ - writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \ - else \ - writel(AT91_PMX_AA_TWD, &pio->pioa.codr); -#define I2C_SCL(bit) \ - if (bit) \ - writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \ - else \ - writel(AT91_PMX_AA_TWCK, &pio->pioa.codr); - -#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII -#define CONFIG_CMD_CACHE -#undef CONFIG_CMD_USB -#undef CONFIG_CMD_DHCP - -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#endif - -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024) - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024) - -#define CONFIG_DRIVER_AT91EMAC -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RMII -#define CONFIG_MII -#define CONFIG_DRIVER_AT91EMAC_PHYADDR 1 -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_KS8721_PHY - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_PROTECTION -#define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define PHYS_FLASH_SIZE (16 * 1024 * 1024) -#define CONFIG_SYS_FLASH_BANKS_LIST \ - { PHYS_FLASH_1 } - -#if defined(CONFIG_CMD_USB) -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_AT91C_PQFP_UHPBU -#undef CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#endif - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 128 * 1024) -#define CONFIG_ENV_SIZE (128 * 1024) -#define CONFIG_ENV_SECT_SIZE (128 * 1024) - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_CMDLINE_EDITING - -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 4 * 1024) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_DEVICE_NULLDEV -#define CONFIG_SILENT_CONSOLE - -#define CONFIG_VERSION_VARIABLE - -#define MTDIDS_DEFAULT "nor0=physmap-flash.0" -#define MTDPARTS_DEFAULT \ - "mtdparts=physmap-flash.0:" \ - "128k(u-boot)ro," \ - "128k(u-boot-env)," \ - "1792k(kernel)," \ - "-(rootfs)" - -#define CONFIG_BOOTARGS \ - "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,115200" - -#define CONFIG_BOOTCOMMAND "run flashboot" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdid=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "flub=tftp 21000000 cpuat91/u-boot.bin; protect off 10000000 " \ - "1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 " \ - "10000000 ${filesize}\0" \ - "flui=tftp 21000000 cpuat91/uImage; protect off 10040000 " \ - "1019ffff; erase 10040000 101fffff; cp.b 21000000 " \ - "10040000 ${filesize}\0" \ - "flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off " \ - "10200000 10ffffff; erase 10200000 10ffffff; cp.b " \ - "21000000 10200000 ${filesize}\0" \ - "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ - "flashboot=run ramargs;bootm 10040000\0" \ - "netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;" \ - "bootm 21000000\0" -#endif /* _CONFIG_CPUAT91_H */ diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h deleted file mode 100644 index 7ac3224e6e..0000000000 --- a/include/configs/da830evm.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com> - * - * Based on davinci_dvevm.h. Original Copyrights follow: - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Board - */ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_USE_SPIFLASH - -/* - * SoC Configuration - */ -#define CONFIG_MACH_DAVINCI_DA830_EVM -#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ -#define CONFIG_SOC_DA830 /* TI DA830 SoC */ -#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TEXT_BASE 0xc1080000 - -/* - * Memory Info - */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Start */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - (32 << 20)) -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ - -/* - * Serial Driver info - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ -#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ - -/* - * I2C Configuration - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */ -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ - -/* - * I2C EEPROM definitions for catalyst 24W256 EEPROM chip - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * Network & Ethernet Configuration - */ -#ifdef CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#endif - -/* - * Flash & Environment - */ -#ifdef CONFIG_USE_NAND -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ -#define CONFIG_ENV_OFFSET (512 << 10) -#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_NAND_CS 3 -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_NAND_MASK_CLE 0x10 -#define CONFIG_SYS_NAND_MASK_ALE 0x8 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#endif - -#ifdef CONFIG_USE_NOR -#define CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ -#define CONFIG_SYS_FLASH_SECT_SZ (64 << 10) /* 64KB */ -#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3) -#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE -#define PHYS_FLASH_SIZE (32 << 20) /* Flash size 32MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) -#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ -#define CONFIG_SYS_FLASH_SPL_ACCESS -#endif - -#ifdef CONFIG_USE_SPIFLASH -#undef CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SIZE (16 << 10) -#define CONFIG_ENV_OFFSET (256 << 10) -#define CONFIG_ENV_SECT_SIZE 4096 -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SPI -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_DAVINCI_SPI -#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED -#endif - -/* - * USB configuration - */ -#define CONFIG_USB_DA8XX /* Platform hookup to MUSB controller */ -#define CONFIG_USB_MUSB_HCD - -/* - * U-Boot general configuration - */ -#undef CONFIG_MISC_INIT_R -#undef CONFIG_BOOTDELAY -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC - -/* - * Linux Information - */ -#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock/2 rw noinitrd ip=dhcp" -#define CONFIG_BOOTCOMMAND "" -#define CONFIG_BOOTDELAY 3 - -/* - * U-Boot commands - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#ifndef CONFIG_DRIVER_TI_EMAC -#undef CONFIG_CMD_DHCP -#undef CONFIG_CMD_MII -#undef CONFIG_CMD_PING -#endif - -#ifdef CONFIG_USE_NAND -#define CONFIG_CMD_NAND -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE -#endif - -#ifdef CONFIG_USE_SPIFLASH -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF -#endif - -/* SD/MMC configuration */ -#ifndef CONFIG_USE_NAND -#define CONFIG_MMC -#define CONFIG_DAVINCI_MMC_SD1 -#define CONFIG_GENERIC_MMC -#define CONFIG_DAVINCI_MMC -#endif - -/* - * Enable MMC commands only when - * MMC support is present - */ -#if defined(CONFIG_MMC) || defined(CONFIG_USB_DA8XX) -#define CONFIG_DOS_PARTITION /* include support for FAT/storage */ -#define CONFIG_CMD_FAT /* include support for FAT cmd */ -#endif - -#ifdef CONFIG_MMC -#define CONFIG_CMD_MMC -#define CONFIG_CMD_EXT2 -#endif - -#if !defined(CONFIG_USE_NAND) && \ - !defined(CONFIG_USE_NOR) && \ - !defined(CONFIG_USE_SPIFLASH) -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_SIZE (16 << 10) -#undef CONFIG_CMD_ENV -#endif - -#ifdef CONFIG_USB_DA8XX - -#ifdef CONFIG_USB_MUSB_HCD /* include support for usb host */ -#define CONFIG_CMD_USB /* include support for usb cmd */ - -#define CONFIG_USB_STORAGE /* MSC class support */ -#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */ - -#ifdef CONFIG_USB_KEYBOARD /* HID class support */ -#define CONFIG_SYS_USB_EVENT_POLL -#define CONFIG_PREBOOT "usb start" -#endif /* CONFIG_USB_KEYBOARD */ - -#endif /* CONFIG_USB_MUSB_HCD */ - -#ifdef CONFIG_USB_MUSB_UDC -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "DA830EVM" -#endif /* CONFIG_USB_MUSB_UDC */ - -#endif /* CONFIG_USB_DA8XX */ - -#ifdef CONFIG_MTD_PARTITIONS -#define MTDIDS_DEFAULT "nand0=davinci_nand.1" -#define PART_BOOT "512k(bootloader)ro," -#define PART_PARAMS "512k(params)ro," -#define PART_KERNEL "4m(kernel)," -#define PART_REST "-(filesystem)" -#define MTDPARTS_DEFAULT \ - "mtdparts=davinci_nand.1:" PART_BOOT PART_PARAMS PART_KERNEL PART_REST -#endif - -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h deleted file mode 100644 index 72296a03dd..0000000000 --- a/include/configs/davinci_dm355evm.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (C) 2009 David Brownell - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Spectrum Digital TMS320DM355 EVM board */ -#define DAVINCI_DM355EVM - -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ -#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET - -/* SoC Configuration */ -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ -#define CONFIG_SOC_DM355 - -/* Memory Info */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */ - -/* Serial Driver info: UART0 for console */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 0x01c20000 -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* Ethernet: external DM9000 */ -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x04014000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 2) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ - -/* NAND: socketed, two chipselects, normally 2 GBytes */ -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_PAGE_2K - -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, } -/* socket has two chipselects, nCE0 gated by address BIT(14) */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_MAX_CHIPS 2 - -/* SD/MMC */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_DAVINCI_MMC -#define CONFIG_DAVINCI_MMC_SD1 -#define CONFIG_MMC_MBLOCK - -/* USB: OTG connector */ -/* NYET -- #define CONFIG_USB_DAVINCI */ - -/* U-Boot command configuration */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#ifdef CONFIG_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_MMC -#endif - -#ifdef CONFIG_NAND_DAVINCI -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE -#define CONFIG_CMD_NAND -#define CONFIG_CMD_UBI -#define CONFIG_RBTREE -#endif - -#ifdef CONFIG_USB_DAVINCI -#define CONFIG_USB_MUSB_HCD -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#else -#undef CONFIG_USB_MUSB_HCD -#undef CONFIG_CMD_USB -#undef CONFIG_USB_STORAGE -#endif - -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC - -/* U-Boot general configuration */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE /* Print buffer size */ \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP - -#ifdef CONFIG_NAND_DAVINCI -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x3C0000 -#undef CONFIG_ENV_IS_IN_FLASH -#endif - -#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_CMD_ENV -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ -#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ -#define CONFIG_ENV_IS_IN_MMC -#undef CONFIG_ENV_IS_IN_FLASH -#endif - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTCOMMAND \ - "dhcp;bootm" -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200n8 " \ - "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro" - -#define CONFIG_CMDLINE_EDITING -#define CONFIG_VERSION_VARIABLE -#define CONFIG_TIMESTAMP - -#define CONFIG_NET_RETRY_COUNT 10 - -/* U-Boot memory configuration */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ -#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ -#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ - -/* Linux interfacing */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ - - -/* NAND configuration ... socketed with two chipselects. It normally comes - * with a 2GByte SLC part with 2KB pages (and 128KB erase blocks); other - * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC - * pretty much demands the 4-bit ECC support.) You can of course swap in - * other parts, including small page ones. - * - * This presents a single read-only partition for all bootloader stuff. - * UBL (1+ block), U-Boot (256KB+), U-Boot environment (one block), and - * some extra space to help cope with bad blocks in that data. Linux - * shouldn't care about its detailed layout, and will probably want to use - * UBI/UBFS for the rest (except maybe on smallpage chips). It's easy to - * override this default partitioning using MTDPARTS and cmdlinepart. - */ -#define MTDIDS_DEFAULT "nand0=davinci_nand.0" - -#ifdef CONFIG_SYS_NAND_LARGEPAGE -/* Use same layout for 128K/256K blocks; allow some bad blocks */ -#define PART_BOOT "2m(bootloader)ro," -#else -/* Assume 16K erase blocks; allow a few bad ones. */ -#define PART_BOOT "512k(bootloader)ro," -#endif - -#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */ -#define PART_REST "-(filesystem)" - -#define MTDPARTS_DEFAULT \ - "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h deleted file mode 100644 index e3ff9431dc..0000000000 --- a/include/configs/davinci_dm355leopard.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Incorporated - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define DAVINCI_DM355LEOPARD - -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ -#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET - -/* SoC Configuration */ -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ -#define CONFIG_SOC_DM355 /* DM355 based board */ - -/* Memory Info */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */ - -/* Serial Driver info: UART0 for console */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 0x01c20000 -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* Ethernet: external DM9000 */ -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x04000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 16) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 - -/* NAND */ -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_HW_ECC - -#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* U-Boot command configuration */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#ifdef CONFIG_NAND_DAVINCI -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE -#define CONFIG_CMD_NAND -#define CONFIG_CMD_UBI -#define CONFIG_RBTREE -#endif - -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC - -/* U-Boot general configuration */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE /* Print buffer size */ \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP - -#ifdef CONFIG_NAND_DAVINCI -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x3C0000 -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OVERWRITE -#endif - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTCOMMAND "dhcp;bootm" -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200n8 " \ - "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro" - -#define CONFIG_CMDLINE_EDITING -#define CONFIG_VERSION_VARIABLE -#define CONFIG_TIMESTAMP - -#define CONFIG_NET_RETRY_COUNT 10 - -/* U-Boot memory configuration */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ -#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ -#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ - -/* Linux interfacing */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ - -#define MTDIDS_DEFAULT "nand0=davinci_nand.0" - -#ifdef CONFIG_SYS_NAND_LARGEPAGE -#define PART_BOOT "2m(bootloader)ro," -#else -/* Assume 16K erase blocks; allow a few bad ones. */ -#define PART_BOOT "512k(bootloader)ro," -#endif - -#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */ -#define PART_REST "-(filesystem)" - -#define MTDPARTS_DEFAULT \ - "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h deleted file mode 100644 index bbc801b4db..0000000000 --- a/include/configs/davinci_dm365evm.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Incorporated - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Spectrum Digital TMS320DM365 EVM board */ -#define DAVINCI_DM365EVM - -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ -#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET - -/* SoC Configuration */ -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ -#define CONFIG_SOC_DM365 - -/* Memory Info */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */ - -/* Serial Driver info: UART0 for console */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 0x01c20000 -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* EEPROM definitions for EEPROM on DM365 EVM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* Network Configuration */ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ - -/* NAND: socketed, two chipselects, normally 2 GBytes */ -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_PAGE_2K - -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, } -/* socket has two chipselects, nCE0 gated by address BIT(14) */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_MAX_CHIPS 2 - -/* SD/MMC */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_DAVINCI_MMC -#define CONFIG_DAVINCI_MMC_SD1 -#define CONFIG_MMC_MBLOCK - -#define PINMUX4_USBDRVBUS_BITCLEAR 0x3000 -#define PINMUX4_USBDRVBUS_BITSET 0x2000 - -/* USB Configuration */ -#define CONFIG_USB_DAVINCI -#define CONFIG_USB_MUSB_HCD - -#ifdef CONFIG_USB_DAVINCI -#define CONFIG_CMD_USB /* include support for usb */ -#define CONFIG_CMD_STORAGE /* include support for usb */ -#define CONFIG_CMD_FAT /* include support for FAT/storage*/ -#define CONFIG_DOS_PARTITION /* include support for FAT/storage*/ -#endif - -#ifdef CONFIG_USB_MUSB_HCD /* include support for usb host */ -#define CONFIG_CMD_USB /* include support for usb cmd */ -#define CONFIG_USB_STORAGE /* MSC class support */ -#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */ -#define CONFIG_CMD_FAT /* inclue support for FAT/storage */ -#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */ - -#ifdef CONFIG_USB_KEYBOARD /* HID class support */ -#define CONFIG_SYS_USB_EVENT_POLL - -#define CONFIG_PREBOOT "usb start" -#endif /* CONFIG_USB_KEYBOARD */ -#endif /* CONFIG_USB_MUSB_HCD */ - -#ifdef CONFIG_USB_MUSB_UDC -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "DM365VM" -#endif /* CONFIG_USB_MUSB_UDC */ - -/* U-Boot command configuration */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#ifdef CONFIG_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_MMC -#endif - -#ifdef CONFIG_NAND_DAVINCI -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE -#define CONFIG_CMD_NAND -#define CONFIG_CMD_UBI -#define CONFIG_RBTREE -#endif - -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC - -/* U-Boot general configuration */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE /* Print buffer size */ \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP - -#ifdef CONFIG_NAND_DAVINCI -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x3C0000 -#undef CONFIG_ENV_IS_IN_FLASH -#endif - -#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_CMD_ENV -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ -#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ -#define CONFIG_ENV_IS_IN_MMC -#undef CONFIG_ENV_IS_IN_FLASH -#endif - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTCOMMAND \ - "dhcp;bootm" -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200n8 " \ - "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro" - -#define CONFIG_CMDLINE_EDITING -#define CONFIG_VERSION_VARIABLE -#define CONFIG_TIMESTAMP - -/* U-Boot memory configuration */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ -#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ -#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ - -/* Linux interfacing */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ - - -/* NAND configuration issocketed with two chipselects just like the DM355 EVM. - * It normally comes with a 2GByte SLC part with 2KB pages - * (and 128KB erase blocks); other - * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC - * pretty much demands the 4-bit ECC support.) You can of course swap in - * other parts, including small page ones. - */ -#define MTDIDS_DEFAULT "nand0=davinci_nand.0" - -#ifdef CONFIG_SYS_NAND_LARGEPAGE -/* Use same layout for 128K/256K blocks; allow some bad blocks */ -#define PART_BOOT "2m(bootloader)ro," -#else -/* Assume 16K erase blocks; allow a few bad ones. */ -#define PART_BOOT "512k(bootloader)ro," -#endif - -#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */ -#define PART_REST "-(filesystem)" - -#define MTDPARTS_DEFAULT \ - "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h deleted file mode 100644 index 6346422b49..0000000000 --- a/include/configs/davinci_dm6467evm.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Incorporated - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Spectrum Digital TMS320DM6467 EVM board */ -#define DAVINCI_DM6467EVM -#define CONFIG_SYS_USE_NAND -#define CONFIG_SYS_NAND_SMALLPAGE - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* SoC Configuration */ - -/* Clock rates detection */ -#ifndef __ASSEMBLY__ -extern unsigned int davinci_arm_clk_get(void); -#endif - -/* Arm Clock frequency */ -#define CONFIG_SYS_CLK_FREQ davinci_arm_clk_get() -/* Timer Input clock freq */ -#define CONFIG_SYS_HZ_CLOCK (CONFIG_SYS_CLK_FREQ/2) -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SOC_DM646X - -/* EEPROM definitions for EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE (256 << 20) /* DDR size 256MB */ - -/* Linux interfacing */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_BARGSIZE 1024 /* Bootarg Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ -#define CONFIG_REVISION_TAG - -/* Serial Driver info */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 4 -#define CONFIG_SYS_NS16550_COM1 0x01c20000 -#define CONFIG_SYS_NS16550_CLK 24000000 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* I2C Configuration */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 - -/* Network & Ethernet Configuration */ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 - -/* Flash & Environment */ -#define CONFIG_SYS_NO_FLASH -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_MASK_CLE 0x80000 -#define CONFIG_SYS_NAND_MASK_ALE 0x40000 -#define CONFIG_SYS_NAND_CS 2 -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ -#define CONFIG_SYS_NAND_BASE_LIST {0x42000000, } -#define CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_ENV_OFFSET 0 -#else -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE (4 << 10) /* 4 KiB */ -#endif - -/* U-Boot general configuration */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -#define CONFIG_BOOTCOMMAND "source 0x82080000; dhcp; bootm" -#define CONFIG_BOOTARGS \ - "mem=120M console=ttyS0,115200n8 " \ - "root=/dev/hda1 rw noinitrd ip=dhcp" - -/* U-Boot commands */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_CMD_NAND -#endif - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h deleted file mode 100644 index 15d815084b..0000000000 --- a/include/configs/davinci_dvevm.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Define this to make U-Boot skip low level initialization when loaded - * by initial bootloader. Not required by NAND U-Boot version but IS - * required for a NOR version used to burn the real NOR U-Boot into - * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive - * so it is NOT possible to build a U-Boot with both NAND and NOR routines. - * NOR U-Boot is loaded directly from Flash so it must perform all the - * low level initialization itself. NAND version is loaded by an initial - * bootloader (UBL in TI-ese) that performs such an initialization so it's - * skipped in NAND version. The third DaVinci boot mode loads a bootloader - * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever) - * performing low level init prior to loading. All that means we can NOT use - * NAND version to put U-Boot into NOR because it doesn't have NOR support and - * we can NOT use NOR version because it performs low level initialization - * effectively destroying itself in DDR memory. That's why a separate NOR - * version with this define is needed. It is loaded via UART, then one uses - * it to somehow download a proper NOR version built WITHOUT this define to - * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze - * NOR support into the initial bootloader so it won't be needed but DaVinci - * static RAM might be too small for this (I have something like 2Kbytes left - * as of now, without NOR support) so this might've not happened... - * -#define CONFIG_NOR_UART_BOOT - */ - -/*=======*/ -/* Board */ -/*=======*/ -#define DV_EVM -#define CONFIG_SYS_NAND_SMALLPAGE -#define CONFIG_SYS_USE_NAND -/*===================*/ -/* SoC Configuration */ -/*===================*/ -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ -#define CONFIG_SOC_DM644X -/*====================================================*/ -/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ -/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ -/*====================================================*/ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -/*=============*/ -/* Memory Info */ -/*=============*/ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */ -#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */ - -#define DDR_8BANKS /* 8-bank DDR2 (256MB) */ -/*====================*/ -/* Serial Driver info */ -/*====================*/ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */ -#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */ -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -/*===================*/ -/* I2C Configuration */ -/*===================*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ -/*==================================*/ -/* Network & Ethernet Configuration */ -/*==================================*/ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -/*=====================*/ -/* Flash & Environment */ -/*=====================*/ -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_CS 2 -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ -#ifdef CONFIG_SYS_NAND_SMALLPAGE -#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ -#define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT \ - "nand0=davinci_nand.0" -#define MTDPARTS_DEFAULT \ - "mtdparts=davinci_nand.0:384k(bootloader)ro,4m(kernel),-(filesystem)" -#else -#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#endif -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ -#define CONFIG_SYS_NAND_BASE 0x02000000 -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -#elif defined(CONFIG_SYS_USE_NOR) -#ifdef CONFIG_NOR_UART_BOOT -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ -#else -#undef CONFIG_SKIP_LOWLEVEL_INIT -#endif -#define CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_SYS_NO_FLASH -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ -#define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */ -#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3) -#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ -#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) -#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */ -#endif -/*==============================*/ -/* U-Boot general configuration */ -/*==============================*/ -#define CONFIG_MISC_INIT_R -#undef CONFIG_BOOTDELAY -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -#define CONFIG_USB_MUSB_HCD -#define CONFIG_USB_DAVINCI -/*===================*/ -/* Linux Information */ -/*===================*/ -#define LINUX_BOOT_PARAM_ADDR 0x80000100 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" -#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2050000" -/*=================*/ -/* U-Boot commands */ -/*=================*/ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_EEPROM - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_CMD_NAND -#elif defined(CONFIG_SYS_USE_NOR) -#define CONFIG_CMD_JFFS2 -#else -#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!" -#endif -/*==========================*/ -/* USB MSC support (if any) */ -/*==========================*/ -#ifdef CONFIG_USB_DAVINCI -#define CONFIG_CMD_USB -#ifdef CONFIG_USB_MUSB_HCD -#define CONFIG_USB_STORAGE -#define CONFIG_CMD_STORAGE -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif -#ifdef CONFIG_USB_KEYBOARD -#define CONFIG_SYS_USB_EVENT_POLL -#define CONFIG_PREBOOT "usb start" -#endif -#endif - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h deleted file mode 100644 index bc5e1ca697..0000000000 --- a/include/configs/davinci_schmoogie.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*=======*/ -/* Board */ -/*=======*/ -#define SCHMOOGIE -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_USE_NAND -#define MACH_TYPE_SCHMOOGIE 1255 -#define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE - -/*===================*/ -/* SoC Configuration */ -/*===================*/ -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ -#define CONFIG_SOC_DM644X -/*=============*/ -/* Memory Info */ -/*=============*/ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */ -#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ -#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ -/*====================*/ -/* Serial Driver info */ -/*====================*/ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */ -#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */ -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -/*===================*/ -/* I2C Configuration */ -/*===================*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ -/*==================================*/ -/* Network & Ethernet Configuration */ -/*==================================*/ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_OVERWRITE_ETHADDR_ONCE -/*=====================*/ -/* Flash & Environment */ -/*=====================*/ -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_SYS_NO_FLASH -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ -#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ -#define CONFIG_SYS_NAND_BASE 0x02000000 -#define CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -/*=====================*/ -/* Board related stuff */ -/*=====================*/ -#define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */ -#define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */ -#define CONFIG_SYS_UID_ADDR 0x50 /* UID chip I2C address */ -/*==============================*/ -/* U-Boot general configuration */ -/*==============================*/ -#define CONFIG_MISC_INIT_R -#undef CONFIG_BOOTDELAY -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -/*===================*/ -/* Linux Information */ -/*===================*/ -#define LINUX_BOOT_PARAM_ADDR 0x80000100 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" -#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot" -/*=================*/ -/* U-Boot commands */ -/*=================*/ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NAND -#undef CONFIG_CMD_EEPROM - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h deleted file mode 100644 index e719388722..0000000000 --- a/include/configs/davinci_sffsdr.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * Copyright (C) 2008 Lyrtech <www.lyrtech.com> - * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Board */ -#define SFFSDR -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_USE_NAND -#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */ -/* SoC Configuration */ -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ -#define CONFIG_SOC_DM644X -/* EEPROM definitions for Atmel 24LC64 EEPROM chip */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -/* Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */ -#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ -#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ -/* Serial Driver info */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */ -#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */ -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -/* I2C Configuration */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ -/* Network & Ethernet Configuration */ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_OVERWRITE_ETHADDR_ONCE -/* Flash & Environment */ -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_SYS_NO_FLASH -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ -#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ -#define CONFIG_SYS_NAND_BASE 0x02000000 -#define CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -/* I2C switch definitions for PCA9543 chip */ -#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70 -#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */ -#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */ -/* U-Boot general configuration */ -#define CONFIG_MISC_INIT_R -#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* Default Linux kernel - * load address. */ -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, - * may be later */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -/* Linux Information */ -#define LINUX_BOOT_PARAM_ADDR 0x80000100 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS \ - "mem=56M " \ - "console=ttyS0,115200n8 " \ - "root=/dev/nfs rw noinitrd ip=dhcp " \ - "nfsroot=${serverip}:/nfsroot/sffsdr " \ - "eth0=${ethaddr}" -#define CONFIG_BOOTCOMMAND \ - "nand read 87A00000 100000 300000;" \ - "bootelf 87A00000" -/* U-Boot commands */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_NAND -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */ - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h deleted file mode 100644 index b85c988b5d..0000000000 --- a/include/configs/davinci_sonata.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Define this to make U-Boot skip low level initialization when loaded - * by initial bootloader. Not required by NAND U-Boot version but IS - * required for a NOR version used to burn the real NOR U-Boot into - * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive - * so it is NOT possible to build a U-Boot with both NAND and NOR routines. - * NOR U-Boot is loaded directly from Flash so it must perform all the - * low level initialization itself. NAND version is loaded by an initial - * bootloader (UBL in TI-ese) that performs such an initialization so it's - * skipped in NAND version. The third DaVinci boot mode loads a bootloader - * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever) - * performing low level init prior to loading. All that means we can NOT use - * NAND version to put U-Boot into NOR because it doesn't have NOR support and - * we can NOT use NOR version because it performs low level initialization - * effectively destroying itself in DDR memory. That's why a separate NOR - * version with this define is needed. It is loaded via UART, then one uses - * it to somehow download a proper NOR version built WITHOUT this define to - * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze - * NOR support into the initial bootloader so it won't be needed but DaVinci - * static RAM might be too small for this (I have something like 2Kbytes left - * as of now, without NOR support) so this might've not happened... - * -#define CONFIG_NOR_UART_BOOT - */ - -/*=======*/ -/* Board */ -/*=======*/ -#define SONATA_BOARD -#define CONFIG_SYS_NAND_SMALLPAGE -#define CONFIG_SYS_USE_NOR -#define MACH_TYPE_SONATA 1254 -#define CONFIG_MACH_TYPE MACH_TYPE_SONATA -/*===================*/ -/* SoC Configuration */ -/*===================*/ -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ -#define CONFIG_SOC_DM644X -/*====================================================*/ -/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ -/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ -/*====================================================*/ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -/*=============*/ -/* Memory Info */ -/*=============*/ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */ -#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ -#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ -/*====================*/ -/* Serial Driver info */ -/*====================*/ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */ -#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */ -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -/*===================*/ -/* I2C Configuration */ -/*===================*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ -/*==================================*/ -/* Network & Ethernet Configuration */ -/*==================================*/ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -/*=====================*/ -/* Flash & Environment */ -/*=====================*/ -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_CS 2 -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_OVERWRITE /* instead if obsoleted forceenv() */ -#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ -#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ -#define CONFIG_SYS_NAND_BASE 0x02000000 -#define CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -#elif defined(CONFIG_SYS_USE_NOR) -#ifdef CONFIG_NOR_UART_BOOT -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ -#else -#undef CONFIG_SKIP_LOWLEVEL_INIT -#endif -#define CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_SYS_NO_FLASH -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ -#define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */ -#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*2) -#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ -#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ -#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) -#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */ -#endif -/*==============================*/ -/* U-Boot general configuration */ -/*==============================*/ -#define CONFIG_MISC_INIT_R -#undef CONFIG_BOOTDELAY -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -/*===================*/ -/* Linux Information */ -/*===================*/ -#define LINUX_BOOT_PARAM_ADDR 0x80000100 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" -#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000" -/*=================*/ -/* U-Boot commands */ -/*=================*/ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_EEPROM -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_CMD_NAND -#elif defined(CONFIG_SYS_USE_NOR) -#define CONFIG_CMD_JFFS2 -#else -#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!" -#endif - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/dig297.h b/include/configs/dig297.h deleted file mode 100644 index 98205adde0..0000000000 --- a/include/configs/dig297.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * (C) Copyright 2011 Comelit Group SpA - * Luca Ceresoli <luca.ceresoli@comelit.it> - * - * Based on omap3_beagle.h: - * (C) Copyright 2006-2008 - * Texas Instruments. - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * - * Configuration settings for the Comelit DIG297 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/mach-types.h> -#ifdef MACH_TYPE_OMAP3_CPS -#error "MACH_TYPE_OMAP3_CPS has been defined properly, please remove this." -#else -#define MACH_TYPE_OMAP3_CPS 2751 -#endif -#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 - -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON - -#define CONFIG_SYS_TEXT_BASE 0x80008000 - -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap.h> - -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* UBI needs >= 512 kB */ - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration: UART3 (ttyO2) - */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION - -/* library portions to compile in */ -#define CONFIG_RBTREE -#define CONFIG_MTD_PARTITIONS -#define CONFIG_LZO - -/* commands to include */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_UBI /* UBI Support */ -#define CONFIG_CMD_UBIFS /* UBIFS Support */ -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define MTDIDS_DEFAULT "nand0=omap2-nand.0" -#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:896k(uboot),"\ - "128k(uboot-env),3m(kernel),252m(ubi)" - -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_NAND /* NAND support */ - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_OMAP34XX - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER -#define CONFIG_TWL4030_LED - -/* - * Board NAND Info. - */ -#define CONFIG_NAND_OMAP_GPMC -#define CONFIG_SYS_NAND_BUSWIDTH_16BIT -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ - /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - -#if defined(CONFIG_CMD_NET) -/* - * SMSC9220 Ethernet - */ - -#define CONFIG_SMC911X -#define CONFIG_SMC911X_32_BIT -#define CONFIG_SMC911X_BASE 0x2C000000 - -#endif /* (CONFIG_CMD_NET) */ - -/* Environment information */ -#define CONFIG_BOOTDELAY 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyO2,115200n8\0" \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "partition=nand0,3\0"\ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "nandroot=ubi0:rootfs ro\0" \ - "nandrootfstype=ubifs\0" \ - "nfspath=/srv/nfs\0" \ - "tftpfilename=uImage\0" \ - "gatewayip=0.0.0.0\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${mtdparts} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}::off\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${mtdparts} " \ - "ubi.mtd=3 " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}::off\0" \ - "netargs=setenv bootargs console=${console} " \ - "${mtdparts} " \ - "root=/dev/nfs rw " \ - "nfsroot=${serverip}:${nfspath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}::off\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 100000 300000; " \ - "bootm ${loadaddr}\0" \ - "netboot=echo Booting from network ...; " \ - "run netargs; " \ - "tftp ${loadaddr} ${serverip}:${tftpfilename}; " \ - "bootm ${loadaddr}\0" \ - "resetenv=nand erase e0000 20000\0"\ - -#define CONFIG_BOOTCOMMAND \ - "run nandboot" - -#define CONFIG_AUTO_COMPLETE -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ - /* works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ - /* load address */ - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_SYS_FLASH_BASE boot_flash_base - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_ENV_IS_IN_NAND -#define SMNAND_ENV_OFFSET 0x0E0000 /* environment starts here */ - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET -#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h index dff3f2a357..998a69aba1 100644 --- a/include/configs/e2220-1170.h +++ b/include/configs/e2220-1170.h @@ -13,7 +13,6 @@ #include "tegra210-common.h" /* High-level configuration options */ -#define V_PROMPT "Tegra210 (E2220-1170) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA E2220-1170" /* Board-specific serial config */ @@ -60,6 +59,4 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define COUNTER_FREQUENCY 38400000 - #endif /* _E2220_1170_H */ diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h deleted file mode 100644 index d27f7e0452..0000000000 --- a/include/configs/eb_cpux9k2.h +++ /dev/null @@ -1,400 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de> - * Jens Scharsig <esw@bus-elektronik.de> - * - * Configuation settings for the EB+CPUx9K2 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_EB_CPUx9K2_H_ -#define _CONFIG_EB_CPUx9K2_H_ - -/*--------------------------------------------------------------------------*/ - -#define CONFIG_AT91RM9200 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_EB_CPUX9K2 /* on an EP+CPUX9K2 Board */ -#define USE_920T_MMU - -#define CONFIG_VERSION_VARIABLE -#define CONFIG_IDENT_STRING " on EB+CPUx9K2" - -#include <asm/hardware.h> /* needed for port definitions */ - -#define CONFIG_MISC_INIT_R -#define CONFIG_BOARD_EARLY_INIT_F - -#define MACH_TYPE_EB_CPUX9K2 1977 -#define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2 - -#define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_SYS_DCACHE_OFF - -/*--------------------------------------------------------------------------*/ -#ifndef CONFIG_RAMBOOT -#define CONFIG_SYS_TEXT_BASE 0x00000000 -#else -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TEXT_BASE 0x21800000 -#endif -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ -#define CONFIG_STANDALONE_LOAD_ADDR 0x21000000 - -#define CONFIG_BOOT_RETRY_TIME 30 -#define CONFIG_CMDLINE_EDITING - -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ - -/* - * ARM asynchronous clock - */ - -#define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */ -#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3) -#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) - -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 -/* flash */ -#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 -#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define CONFIG_SYS_PLLAR_VAL 0x20483E05 /* 179.4048 MHz for PCK */ -#define CONFIG_SYS_PLLBR_VAL 0x104C3E0A /* 47.3088 MHz (for USB) */ -#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Clock */ - -/* - * Size of malloc() pool - */ - -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* - * sdram - */ - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ -#define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \ - CONFIG_SYS_MALLOC_LEN) - -#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */ -#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 -#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 -#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define CONFIG_SYS_SDRC_CR_VAL 0x2188c159 /* set up the SDRAM */ -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */ -#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */ -#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ - -/* - * Command line configuration - */ -#define CONFIG_CMD_BMP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING -#define CONFIG_I2C_CMD_TREE -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_CMD_UBI -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_UBIFS - -#define CONFIG_SYS_LONGHELP - -/* - * MTD defines - */ - -#define CONFIG_FLASH_CFI_MTD -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS -#define CONFIG_RBTREE -#define CONFIG_LZO - -#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand" -#define MTDPARTS_DEFAULT "mtdparts=" \ - "physmap-flash.0:" \ - "512k(U-Boot)," \ - "128k(Env)," \ - "128k(Splash)," \ - "4M(Kernel)," \ - "384k(MiniFS)," \ - "-(FS)" \ - ";" \ - "atmel_nand:" \ - "1M(emergency)," \ - "-(data)" -/* - * Hardware drivers - */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_AT91C_PQFP_UHPBUG -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_EFI_PARTITION - -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00300000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" - -/* - * UART/CONSOLE - */ - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID 0/* ignored in arm */ - -/* - * network - */ - -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_RESET_PHY_R 1 - -#define CONFIG_DRIVER_AT91EMAC 1 -#define CONFIG_DRIVER_AT91EMAC_QUIET 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 -#define CONFIG_MII 1 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * I2C-Bus - */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0 - -/* Software I2C driver configuration */ - -#define AT91_PIN_SDA (1<<25) /* AT91C_PIO_PA25 */ -#define AT91_PIN_SCL (1<<26) /* AT91C_PIO_PA26 */ - -#define CONFIG_SYS_I2C_INIT_BOARD - -#define I2C_INIT i2c_init_board(); -#define I2C_ACTIVE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr); -#define I2C_TRISTATE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder); -#define I2C_READ ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0) -#define I2C_SDA(bit) \ - if (bit) \ - writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr); \ - else \ - writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr); -#define I2C_SCL(bit) \ - if (bit) \ - writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr); \ - else \ - writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr); - -#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SOFT_SPEED) - -/* I2C-RTC */ - -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#endif - -/* EEPROM */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 - -/* FLASH organization */ - -/* NOR-FLASH */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 - -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define PHYS_FLASH_1 0x10000000 -#define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main flash */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_FLASH_PROTECTION 1 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CONFIG_SYS_FLASH_ERASE_TOUT 6000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 - -/* NAND */ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 - -/* Status LED's */ - -#define CONFIG_STATUS_LED 1 -#define CONFIG_BOARD_SPECIFIC_LED 1 - -#define STATUS_LED_BOOT 1 -#define STATUS_LED_ACTIVE 0 - -#define STATUS_LED_BIT 1 /* AT91C_PIO_PD0 green LED */ -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -#define STATUS_LED_STATE STATUS_LED_OFF /* BLINKING */ -#define STATUS_LED_BIT1 2 /* AT91C_PIO_PD1 red LED */ -#define STATUS_LED_STATE1 STATUS_LED_ON /* BLINKING */ -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 4) - -#define CONFIG_VIDEO 1 - -/* Options */ - -#ifdef CONFIG_VIDEO - -#define CONFIG_VIDEO_VCXK 1 - -#define CONFIG_SPLASH_SCREEN 1 - -#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 4 -#define CONFIG_SYS_VCXK_BASE 0x30000000 - -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN (1<<3) -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT piob -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR odr - -#define CONFIG_SYS_VCXK_ENABLE_PIN (1<<5) -#define CONFIG_SYS_VCXK_ENABLE_PORT piob -#define CONFIG_SYS_VCXK_ENABLE_DDR oer - -#define CONFIG_SYS_VCXK_REQUEST_PIN (1<<2) -#define CONFIG_SYS_VCXK_REQUEST_PORT piob -#define CONFIG_SYS_VCXK_REQUEST_DDR oer - -#define CONFIG_SYS_VCXK_INVERT_PIN (1<<4) -#define CONFIG_SYS_VCXK_INVERT_PORT piob -#define CONFIG_SYS_VCXK_INVERT_DDR oer - -#define CONFIG_SYS_VCXK_RESET_PIN (1<<6) -#define CONFIG_SYS_VCXK_RESET_PORT piob -#define CONFIG_SYS_VCXK_RESET_DDR oer - -#endif /* CONFIG_VIDEO */ - -/* Environment */ - -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x80000) -#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTCOMMAND "run nfsboot" - -#define CONFIG_NFSBOOTCOMMAND \ - "dhcp $(copy_addr) uImage_cpux9k2;" \ - "run bootargsdefaults;" \ - "set bootargs $(bootargs) boot=nfs " \ - ";echo $(bootargs)" \ - ";bootm" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "displaywidth=256\0" \ - "displayheight=512\0" \ - "displaybsteps=1023\0" \ - "ubootaddr=10000000\0" \ - "splashimage=100A0000\0" \ - "kerneladdr=100C0000\0" \ - "kernelsize=00400000\0" \ - "rootfsaddr=10520000\0" \ - "copy_addr=21200000\0" \ - "rootfssize=00AE0000\0" \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "bootargsdefaults=set bootargs " \ - "console=ttyS0,115200 " \ - "video=vcxk_fb:xres:${displaywidth}," \ - "yres:${displayheight}," \ - "bres:${displaybsteps} " \ - "mem=62M " \ - "panic=10 " \ - "uboot=\\\"${ver}\\\" " \ - "\0" \ - "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \ - "dhcp $(copy_addr) uImage_cpux9k2;" \ - "erase $(kerneladdr) +$(kernelsize);" \ - "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \ - "protect on $(kerneladdr) +$(kernelsize)" \ - "\0" \ - "update_root=protect off $(rootfsaddr) +$(rootfssize);" \ - "dhcp $(copy_addr) rfs;" \ - "erase $(rootfsaddr) +$(rootfssize);" \ - "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \ - "\0" \ - "update_uboot=protect off 10000000 1007FFFF;" \ - "dhcp $(copy_addr) u-boot_eb_cpux9k2;" \ - "erase 10000000 1007FFFF;" \ - "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \ - "protect on 10000000 1007FFFF;reset\0" \ - "update_splash=protect off $(splashimage) +20000;" \ - "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \ - "erase $(splashimage) +20000;" \ - "cp.b $(fileaddr) $(splashimage) $(filesize);" \ - "protect on $(splashimage) +20000;reset\0" \ - "emergency=run bootargsdefaults;" \ - "set bootargs $(bootargs) root=initramfs boot=emergency " \ - ";bootm $(kerneladdr)\0" \ - "netemergency=run bootargsdefaults;" \ - "dhcp $(copy_addr) uImage_cpux9k2;" \ - "set bootargs $(bootargs) root=initramfs boot=emergency " \ - ";bootm $(copy_addr)\0" \ - "norboot=run bootargsdefaults;" \ - "set bootargs $(bootargs) root=initramfs boot=local " \ - ";bootm $(kerneladdr)\0" \ - "nandboot=run bootargsdefaults;" \ - "set bootargs $(bootargs) root=initramfs boot=nand " \ - ";bootm $(kerneladdr)\0" \ - " " - -/*--------------------------------------------------------------------------*/ - -#endif - -/* EOF */ diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h index efe2a9daa7..e3e32aa081 100644 --- a/include/configs/edb93xx.h +++ b/include/configs/edb93xx.h @@ -25,6 +25,8 @@ #error "no board defined" #endif +#define CONFIG_SYS_GENERIC_BOARD + /* Initial environment and monitor configuration options. */ #define CONFIG_BOOTDELAY 2 #define CONFIG_CMDLINE_TAG 1 diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 12744a6143..f55ba9f706 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -19,7 +19,7 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) @@ -33,6 +33,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h deleted file mode 100644 index 141489d179..0000000000 --- a/include/configs/enbw_cmc.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * (C) Copyright 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on davinci_dvevm.h. Original Copyrights follow: - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Board - */ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7 -#define CONFIG_USE_NAND - -/* - * SoC Configuration - */ -#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ -#define CONFIG_SOC_DA850 /* TI DA850 SoC */ -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH -#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_DA850_LOWLEVEL -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_SYS_DA850_PLL_INIT -#define CONFIG_SYS_DA850_DDR_INIT -#define CONFIG_DA8XX_GPIO -#define CONFIG_HOSTNAME enbw_cmc - -#define MACH_TYPE_ENBW_CMC 3585 -#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC - -/* - * Memory Info - */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ -#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ -#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ - -/* memtest start addr */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) - -/* memtest will be run on 16MB */ -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) - -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ - -/* - * Serial Driver info - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ -#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ - -/* - * I2C Configuration - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ -#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 -#define CONFIG_CMD_I2C - -#define CONFIG_CMD_DTT -#define CONFIG_DTT_LM75 -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - -/* - * SPI Configuration - */ -#define CONFIG_DAVINCI_SPI -#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) -#define CONFIG_CMD_SPI - -/* - * Flash & Environment - */ -#ifdef CONFIG_USE_NAND -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_NAND_CS 3 -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_SYS_NAND_MASK_CLE 0x10 -#define CONFIG_SYS_NAND_MASK_ALE 0x8 -#undef CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ - -#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=davinci_nand.1" -#define MTDPARTS_DEFAULT \ - "mtdparts=" \ - "physmap-flash.0:" \ - "512k(U-Boot)," \ - "64k(env1)," \ - "64k(env2)," \ - "-(rest);" \ - "davinci_nand.1:" \ - "128k(dtb)," \ - "3m(kernel)," \ - "4m(rootfs)," \ - "-(userfs)" - - -#define CONFIG_CMD_MTDPARTS - -#endif - -/* - * Network & Ethernet Configuration - */ -#ifdef CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#endif - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_FLASH_CFI_MTD -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_FLASH_16BIT /* Flash is 16-bit */ - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE (64 << 10) -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#undef CONFIG_ENV_IS_IN_NAND -#define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \ - CONFIG_ENV_SECT_SIZE) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "u-boot_addr_r=c0000000\0" \ - "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"\ - "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ - "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \ - " ${filesize};" \ - "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\ - "netdev=eth0\0" \ - "rootpath=/opt/eldk-arm/arm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "kernel_addr_r=c0700000\0" \ - "fdt_addr_r=c0600000\0" \ - "ramdisk_addr_r=c0b00000\0" \ - "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" \ - __stringify(CONFIG_HOSTNAME) ".dtb\0" \ - "kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \ - "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0" \ - "nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0" \ - "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0" \ - "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \ - "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \ - "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0" \ - "addcon=setenv bootargs ${bootargs} console=ttyS2," \ - "${baudrate}n8\0" \ - "net_nfs=run load_fdt load_kernel; " \ - "run nfsargs addip addcon addmtd addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\ - "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ - "bootcmd=run net_nfs\0" \ - "machid=e01\0" \ - "key_cmd_0=echo key: 0\0" \ - "key_cmd_1=echo key: 1\0" \ - "key_cmd_2=echo key: 2\0" \ - "key_cmd_3=echo key: 3\0" \ - "key_magic_0=0\0" \ - "key_magic_1=1\0" \ - "key_magic_2=2\0" \ - "key_magic_3=3\0" \ - "magic_keys=0123\0" \ - "hwconfig=switch:lan=on,pwl=off,config=0x60100000\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "logversion=2\0" \ - "\0" - -/* - * U-Boot general configuration - */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -#define CONFIG_BOOTDELAY 3 -#define CONFIG_HWCONFIG -#define CONFIG_SHOW_BOOT_PROGRESS -#define CONFIG_BOARD_LATE_INIT - -/* - * U-Boot commands - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_CACHE - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#ifndef CONFIG_DRIVER_TI_EMAC -#undef CONFIG_CMD_DHCP -#undef CONFIG_CMD_MII -#undef CONFIG_CMD_PING -#endif - -#ifdef CONFIG_USE_NAND -#define CONFIG_CMD_NAND - -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS -#define CONFIG_LZO -#define CONFIG_RBTREE -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#endif - -#if !defined(CONFIG_USE_NAND) && \ - !defined(CONFIG_USE_NOR) && \ - !defined(CONFIG_USE_SPIFLASH) -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_SIZE (16 << 10) -#undef CONFIG_CMD_ENV -#endif - -#define CONFIG_SYS_TEXT_BASE 0x60000000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 -#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00) - -#define CONFIG_VERSION_VARIABLE -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMC_RESET_PIN 0x04000000 -#define CONFIG_CMC_RESET_TIMEOUT 3 - -#define CONFIG_HW_WATCHDOG -#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE -#define CONFIG_SYS_WDT_PERIOD_LOW 0x0c000000 -#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0 - -#define CONFIG_CMD_DATE -#define CONFIG_RTC_DAVINCI - -/* SD/MMC */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_DAVINCI_MMC -#define CONFIG_MMC_MBLOCK -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_FAT -#define CONFIG_CMD_MMC - -/* GPIO */ -#define CONFIG_ENBW_CMC_BOARD_TYPE 57 -#define CONFIG_ENBW_CMC_HW_ID_BIT0 39 -#define CONFIG_ENBW_CMC_HW_ID_BIT1 38 -#define CONFIG_ENBW_CMC_HW_ID_BIT2 35 - -/* FDT support */ -#define CONFIG_OF_LIBFDT - -/* LowLevel Init */ -/* PLL */ -#define CONFIG_SYS_DV_CLKMODE 0 -#define CONFIG_SYS_DA850_PLL0_POSTDIV 0 -#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 -#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 -#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 /* 150MHz */ -#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 -#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 -#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 -#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 - -#define CONFIG_SYS_DA850_PLL1_POSTDIV 1 -#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 -#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 -#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 - -#define CONFIG_SYS_DA850_PLL0_PLLM 18 /* PLL0 -> 456 MHz */ -#define CONFIG_SYS_DA850_PLL1_PLLM 24 /* PLL1 -> 300 MHz */ - -/* DDR RAM */ -#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ - DV_DDR_PHY_EXT_STRBEN | \ - (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \ - (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \ - (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ - (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ - (0x1 << DV_DDR_SDCR_DDREN_SHIFT) | \ - (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ - (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) | \ - (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ - (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ - (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ - (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */ - -/* - * freq = 150MHz -> t = 7ns - */ -#define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \ - (0x0d << DV_DDR_SDTMR1_RFC_SHIFT) | \ - (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ - (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ - (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ - (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ - (7 << DV_DDR_SDTMR1_RC_SHIFT) | \ - (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ - (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) | /* Reserved */ \ - ((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT)) - -/* - * freq = 150MHz -> t=7ns - */ -#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \ - (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \ - (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ - (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ - (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ - (15 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ - (27 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ - (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ - (2 << DV_DDR_SDTMR2_CKE_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000407 -#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 -#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ - DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ - DAVINCI_SYSCFG_SUSPSRC_UART2 | \ - DAVINCI_SYSCFG_SUSPSRC_EMAC |\ - DAVINCI_SYSCFG_SUSPSRC_I2C) - -#define CONFIG_SYS_DA850_CS2CFG (DAVINCI_ABCR_WSETUP(2) | \ - DAVINCI_ABCR_WSTROBE(6) | \ - DAVINCI_ABCR_WHOLD(1) | \ - DAVINCI_ABCR_RSETUP(2) | \ - DAVINCI_ABCR_RSTROBE(6) | \ - DAVINCI_ABCR_RHOLD(1) | \ - DAVINCI_ABCR_ASIZE_16BIT) - -#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \ - DAVINCI_ABCR_WSTROBE(2) | \ - DAVINCI_ABCR_WHOLD(1) | \ - DAVINCI_ABCR_RSETUP(1) | \ - DAVINCI_ABCR_RSTROBE(6) | \ - DAVINCI_ABCR_RHOLD(1) | \ - DAVINCI_ABCR_ASIZE_8BIT) - -/* - * NOR Bootconfiguration word: - * Method: Direc boot - * EMIFA access mode: 16 Bit - */ -#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) - -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY) -#define CONFIG_POST_EXTERNAL_WORD_FUNCS -#define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE -#define CONFIG_LOGBUFFER -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -#define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE -#define CONFIG_SYS_BOOTCOUNT_BE - -#define CONFIG_SYS_NAND_U_BOOT_DST 0xc0080000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x60004000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x70000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#endif /* __CONFIG_H */ diff --git a/include/configs/flea3.h b/include/configs/flea3.h index 5b4b011957..f646feefa9 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -52,6 +52,8 @@ */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */ #define CONFIG_SYS_MXC_I2C3_SLAVE 0xfe diff --git a/include/configs/galileo.h b/include/configs/galileo.h index b7ec2792bb..ba6c8f172b 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -15,6 +15,7 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_ARCH_MISC_INIT /* ns16550 UART is memory-mapped in Quark SoC */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 8b9d922876..484d76305f 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -57,7 +57,7 @@ #define CONFIG_CMD_GPIO /* Thermal */ -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL /* Serial */ #define CONFIG_MXC_UART @@ -107,6 +107,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_GSC 0 diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 8ff9077c37..3af02132f8 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -12,6 +12,8 @@ #ifndef __HIKEY_H #define __HIKEY_H +#include <linux/sizes.h> + /* We use generic board for hikey */ #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_POWER @@ -29,6 +31,8 @@ /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT +#define CONFIG_BOARD_EARLY_INIT_F + /* Physical Memory Map */ /* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ @@ -38,7 +42,8 @@ #define PHYS_SDRAM_1 0x00000000 /* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/ -#define PHYS_SDRAM_1_SIZE 0x3f000000 +#define PHYS_SDRAM_1_SIZE 0x3EFFFFFF + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 @@ -55,15 +60,10 @@ #define GICC_BASE 0xf6802000 /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) - -/* PL011 Serial Configuration */ -#define CONFIG_PL011_SERIAL - -#define CONFIG_PL011_CLOCK 19200000 -#define CONFIG_PL01x_PORTS {(void *)0xF8015000} -#define CONFIG_CONS_INDEX 0 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) +/* Serial port PL010/PL011 through the device model */ +#define CONFIG_PL01X_SERIAL #define CONFIG_BAUDRATE 115200 #define CONFIG_CMD_USB @@ -81,9 +81,7 @@ #endif #define CONFIG_HIKEY_GPIO -#define CONFIG_DM_GPIO #define CONFIG_CMD_GPIO -#define CONFIG_DM /* SD/MMC configuration */ #define CONFIG_GENERIC_MMC diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h deleted file mode 100644 index 2fa6c3d91b..0000000000 --- a/include/configs/ima3-mx53.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * (C) Copyright 2012, Stefano Babic <sbabic@denx.de> - * - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * Configuration settings for the MX53-EVK Freescale board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* SOC type must be included before imx-regs.h */ -#define CONFIG_MX53 -#include <asm/arch/imx-regs.h> - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_OF_LIBFDT - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -#define CONFIG_BOARD_EARLY_INIT_F - -/* Enable GPIOs */ -#define CONFIG_MXC_GPIO - -/* UART */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR - -/* MMC */ -#define CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_DOS_PARTITION - -/* Ethernet on FEC */ -#define CONFIG_MII - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x01 -#define CONFIG_PHY_ADDR CONFIG_FEC_MXC_PHYADDR -#define CONFIG_RESET_PHY_R -#define CONFIG_FEC_MXC_NO_ANEG -#define CONFIG_ETHPRIME "FEC0" - -/* SPI */ -#define CONFIG_HARD_SPI -#define CONFIG_MXC_SPI -#define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 - -/* SPI FLASH - not used for environment */ -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SF_DEFAULT_SPEED 25000000 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* Command definition */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_GPIO - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ -#define CONFIG_SYS_TEXT_BASE 0xf0001400 /* uboot in nor flash */ - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_CMDLINE_EDITING - -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define MTDIDS_DEFAULT "nor0=f0000000.flash" - -/* FLASH and environment organization */ - -#define CONFIG_SYS_FLASH_BASE 0xF0000000 -#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */ -#define CONFIG_FLASH_CFI_MTD /* with MTD support */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* - * Default environment and default scripts - * to update uboot and load kernel - */ - -#define HOSTNAME ima3-mx53 - -#define CONFIG_HOSTNAME ima3-mx53 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram0 rw\0" \ - "addip_sta=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test -n ${ipdyn};then run addip_dyn;" \ - "else run addip_sta;fi\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=${console},${baudrate}\0" \ - "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ - "console=ttymxc3\0" \ - "loadaddr=70800000\0" \ - "kernel_addr_r=70800000\0" \ - "ramdisk_addr_r=71000000\0" \ - "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ - "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ - "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \ - "mmcargs=setenv bootargs root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "mmcroot=/dev/mmcblk0p3 rw\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs addip addtty addmtd addmisc mmcload;" \ - "bootm\0" \ - "mmcload=fatload mmc ${mmcdev}:${mmcpart} " \ - "${loadaddr} ${uimage}\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "net_self_load=tftp ${ramdisk_addr_r} ${ramdisk_file};" \ - "tftp ${kernel_addr_r} ${bootfile}\0" \ - "net_self=if run net_self_load;then " \ - "run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ - "else echo Images not loades;fi\0" \ - "satargs=setenv bootargs root=/dev/sda1\0" \ - "satafile=boot/uImage\0" \ - "ssdboot=echo Booting from ssd ...; " \ - "run satargs addip addtty addmtd addmisc;" \ - "sata init;ext2load sata 0:1 ${kernel_addr_r} " \ - "${satafile};bootm\0" \ - "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.imx\0" \ - "uimage=uImage\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "uboot_addr=0xf0001000\0" \ - "update=protect off 0xf0000000 +60000;" \ - "erase ${uboot_addr} +60000;" \ - "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ - "upd=if run load;then echo Updating u-boot;if run update;" \ - "then echo U-Boot updated;" \ - "else echo Error updating u-boot !;" \ - "echo Board without bootloader !!;" \ - "fi;" \ - "else echo U-Boot not downloaded..exiting;fi\0" \ - "bootcmd=run net_nfs\0" - - -#define CONFIG_CMD_SATA -#ifdef CONFIG_CMD_SATA - #define CONFIG_DWC_AHSATA - #define CONFIG_SYS_SATA_MAX_DEVICE 1 - #define CONFIG_DWC_AHSATA_PORT_ID 0 - #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR - #define CONFIG_LBA48 - #define CONFIG_LIBATA -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/imx27lite.h b/include/configs/imx27lite.h deleted file mode 100644 index c18c35ef53..0000000000 --- a/include/configs/imx27lite.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* include common defines/options for all imx27lite related boards */ -#include "imx27lite-common.h" -/* - * SoC Configuration - */ -#define CONFIG_IMX27LITE -#define CONFIG_HOSTNAME imx27 -#define CONFIG_BOARDNAME "LogicPD imx27lite\n" - -/* - * Flash & Environment - */ -#define CONFIG_SYS_FLASH_SECT_SZ 0x2000 /* 8KB sect size Intel Flash */ -#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x20000) -#define PHYS_FLASH_SIZE 0x200000 -#define CONFIG_ENV_SECT_SIZE 0x10000 /* Env sector Size */ - -/* - * SD/MMC - */ -#define CONFIG_MXC_MCI_REGS_BASE 0x10014000 - -/* - * MTD partitions - */ -#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0" -#define MTDPARTS_DEFAULT \ - "mtdparts=" \ - "physmap-flash.0:" \ - "256k(U-Boot)," \ - "1664k(user)," \ - "64k(env1)," \ - "64k(env2);" \ - "mxc_nand.0:" \ - "128k(IPL-SPL)," \ - "4m(kernel)," \ - "22m(rootfs)," \ - "-(userfs)" - -#endif /* __CONFIG_H */ diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h deleted file mode 100644 index 23e3a6c5fc..0000000000 --- a/include/configs/imx31_litekit.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments. - * Richard Woodruff <r-woodruff2@ti.com> - * Kshitij Gupta <kshitij@ti.com> - * - * Configuration settings for the LogicPD i.MX31 Litekit board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - - /* High Level Configuration Options */ -#define CONFIG_MX31 1 /* This is a mx31 */ -#define CONFIG_MX31_CLK32 32000 - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_SYS_TEXT_BASE 0xa0000000 - -#define CONFIG_MACH_TYPE MACH_TYPE_MX31LITE - -/* Temporarily disabled */ -#if 0 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_FIT 1 -#define CONFIG_FIT_VERBOSE 1 -#endif - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_MXC_GPIO - -#define CONFIG_HARD_SPI 1 -#define CONFIG_MXC_SPI 1 -#define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) - -/* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL -#define CONFIG_FSL_PMIC_BUS 1 -#define CONFIG_FSL_PMIC_CS 0 -#define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/*********************************************************** - * Command definition - ***********************************************************/ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SPI -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NAND - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.23.168 -#define CONFIG_SERVERIP 192.168.23.2 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \ - "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ - "bootcmd=run bootcmd_net\0" \ - "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \ - "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0" - - -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000) -#define CONFIG_SMC911X_32_BIT 1 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */ - -#define CONFIG_CMDLINE_EDITING 1 - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD0_BASE -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) -#define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x001f0000) -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_SIZE (64 * 1024) - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* - * JFFS2 partitions - */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" - -/* - * NAND flash - */ -#define CONFIG_NAND_MXC -#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR -#define CONFIG_MXC_NAND_HWECC - -#endif /* __CONFIG_H */ diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 86f327c827..3bea71b969 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -38,6 +38,8 @@ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET diff --git a/include/configs/jornada.h b/include/configs/jornada.h deleted file mode 100644 index 3090476340..0000000000 --- a/include/configs/jornada.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright 2010 (C) - * Kristoffer Ericson <kristoffer.ericson@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SA1110 1 /* This is an SA110 CPU */ -#define CONFIG_JORNADA700 1 /* on an HP Jornada 700 series */ -#define CONFIG_SYS_FLASH_PROTECTION 1 - -#define CONFIG_SYS_TEXT_BASE 0xC1F00000 - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* Console setting */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * select serial console configuration - */ -#define CONFIG_SA1100_SERIAL 1 -#define CONFIG_SERIAL3 1 /* we use serial 3 */ -#define CONFIG_BAUDRATE 19200 -#define CONFIG_LOADS_ECHO 1 - -/* - * Command line configuration. - */ -#define CONFIG_CMD_JFFS2 - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTARGS "root=/dev/hda1 console=ttySA0,19200n8 console=tty1" -#define CONFIG_BOOTCOMMAND "run boot_kernel" -#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ -#define CONFIG_SYS_LOAD_ADDR 0xc0000000 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* console buffsize */ -#define CONFIG_SYS_PBSIZE (256+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE 256 /* Boot Argument Buffer Size */ -#define CONFIG_SYS_MEMTEST_START 0xc0040000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xc2000000 /* 4..128 MB */ -#define CONFIG_SYS_CPUSPEED 0x0a /* core clock 206MHz */ -#define CONFIG_SYS_BAUDRATE_TABLE { 19200, 38400, 57600, 115200 } - -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_FLASH_CFI_WIDTH FLASH_CFI_32BIT -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_ERASE_TOUT (4096) -#define CONFIG_SYS_FLASH_WRITE_TOUT (4096) -#define CONFIG_SYS_FLASH_INCREMENT 0x02000000 -#define PHYS_FLASH_1 0x00000000 /* starts at 0x0 */ -#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256KB Sectors */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 260 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 -#define CONFIG_SYS_MONITOR_LEN 0x00040000 -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_FLASH_SHOW_PROGRESS 1 - -/* Environment */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x00040000 -#define CONFIG_ENV_OFFSET 0x00040000 -#define CONFIG_ENV_SIZE 0x00040000 -#define CONFIG_ENV_SECT_SIZE 0x00040000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - Monitor - 0x00000000 - 0x00040000 (256kb) - Environment - 0x00040000 - 0x00080000 (256kb) - Kernel - 0x00080000 - 0x00380000 (3mb) - Rootfs - 0x00380000 - 0x........ (rest) -*/ - -#define CONFIG_NR_DRAM_BANKS 2 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_INIT_SP_ADDR 0x0 -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_2 0xc4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=jornada7xx-0" -#define MTDPARTS_DEFAULT "mtdparts=jornada7xx-0:256k(u-boot),256k(env),"\ - "3m(kernel),-(user);" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "flash_kernel=protect off all; " \ - "erase 00080000 0037ffff;cp.b c0000000 00080000 00300000;\0" \ - "flash_uboot=protect off all; " \ - "erase 00000000 0003ffff;cp.b c0000000 00000000 00040000;\0" \ - "boot_kernel=cp.b 00080000 c0000000 00300000;bootm;\0" -#endif /* __CONFIG_H */ diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 30810d3752..7f878b713a 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -8,6 +8,11 @@ #define _CONFIG_LACIE_KW_H /* + * Generic board support + */ +#define CONFIG_SYS_GENERIC_BOARD + +/* * Machine number definition */ #if defined(CONFIG_INETSPACE_V2) @@ -96,8 +101,6 @@ #undef CONFIG_SYS_IDE_MAXDEVICE #undef CONFIG_SYS_PROMPT #define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */ -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 #if defined(CONFIG_D2NET_V2) #define CONFIG_SYS_PROMPT "d2v2> " #elif defined(CONFIG_NET2BIG_V2) @@ -127,6 +130,11 @@ #if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \ defined(CONFIG_NET2BIG_V2) #define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 2 +#else +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 #endif #endif /* CONFIG_MVSATA_IDE */ diff --git a/include/configs/lp8x4x.h b/include/configs/lp8x4x.h deleted file mode 100644 index 10a7b05daf..0000000000 --- a/include/configs/lp8x4x.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * ICP DAS LP-8x4x configuration file - * - * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X /* Marvell PXA270 CPU */ -#define MACH_TYPE_LP8X4X 4539 /* ICP DAS LP-8x4x */ -#define CONFIG_MACH_TYPE MACH_TYPE_LP8X4X -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_MALLOC_LEN (128*1024) -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_BOOTCOMMAND \ - "bootm 80000 - 240000;" - -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 mem=128M root=/dev/mmcblk0p1 rw" \ - "init=/sbin/init rootfstype=ext4 rootwait" - -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_LZMA /* LZMA compression support */ -#define CONFIG_OF_LIBFDT - -/* - * Serial Console Configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 -#define CONFIG_CONS_INDEX 3 -#define CONFIG_BAUDRATE 115200 - -/* - * Bootloader Components Configuration - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MMC -#define CONFIG_CMD_USB -#undef CONFIG_LCD -#undef CONFIG_CMD_IDE - -/* - * Networking Configuration - * chip on the ICPDAS LINPAC board - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x0C000000 -#define DM9000_IO 0x0C000000 -#define DM9000_DATA 0x0C004000 -#define DM9000_IO_2 0x0D000000 -#define DM9000_DATA_2 0x0D004000 -#define CONFIG_NET_RETRY_COUNT 10 - -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#endif - -/* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_DOS_PARTITION -#endif - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#endif - -/* - * HUSH Shell Configuration - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP -#undef CONFIG_SYS_PROMPT -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " -#else -#endif -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_DEVICE_NULLDEV 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_AUTO_COMPLETE 1 - -/* - * DRAM Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xa0008000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Use first 64kb bank of the internal SRAM */ -#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 - -/* - * NOR FLASH - */ -#define CONFIG_SYS_MONITOR_BASE 0x0 -#define CONFIG_SYS_MONITOR_LEN 0x40000 -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x40000 - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } - -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_FLASH_PROTECTION 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPSR0_VAL 0x0808c014 -#define CONFIG_SYS_GPSR1_VAL 0x00cf0002 -#define CONFIG_SYS_GPSR2_VAL 0x0221c000 -#define CONFIG_SYS_GPSR3_VAL 0x00020000 - -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x0000ab80 -#define CONFIG_SYS_GPCR2_VAL 0x00100000 -#define CONFIG_SYS_GPCR3_VAL 0x0 - -#define CONFIG_SYS_GPDR0_VAL 0xc0e9ddf4 -#define CONFIG_SYS_GPDR1_VAL 0xfcffab83 -#define CONFIG_SYS_GPDR2_VAL 0x02f1ffff -#define CONFIG_SYS_GPDR3_VAL 0x00021b81 - -#define CONFIG_SYS_GAFR0_L_VAL 0x80000000 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5e54018 -#define CONFIG_SYS_GAFR1_L_VAL 0x999a955a -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a -#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x55f9a402 -#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c -#define CONFIG_SYS_GAFR3_U_VAL 0x00001599 - -#define CONFIG_SYS_PSSR_VAL 0x32 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x005002c0 -#define CONFIG_SYS_CCCR 0x02000290 -#define CONFIG_SYS_CLKCFG 0x0000000b - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x2bd8aad2 -#define CONFIG_SYS_MSC1_VAL 0xb8c9b8dc -#define CONFIG_SYS_MSC2_VAL 0xfff9b8c9 -#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 -#define CONFIG_SYS_MDREFR_VAL 0x2093e018 -#define CONFIG_SYS_MDCNFG_VAL 0x890009d1 -#define CONFIG_SYS_MDMRS_VAL 0x00220022 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000001 -#define CONFIG_SYS_MCMEM0_VAL 0x0000c497 -#define CONFIG_SYS_MCMEM1_VAL 0x0000c497 -#define CONFIG_SYS_MCATT0_VAL 0x0000c497 -#define CONFIG_SYS_MCATT1_VAL 0x0000c497 -#define CONFIG_SYS_MCIO0_VAL 0x00008407 -#define CONFIG_SYS_MCIO1_VAL 0x00008407 - -/* - * LCD - */ -#ifdef CONFIG_LCD -#define CONFIG_VOIPAC_LCD -#endif - -/* - * USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lp8x4x" -#define CONFIG_USB_STORAGE -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index b44f3264e3..f73900fe30 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -389,6 +389,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 7dcb719b01..02cc09c82b 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -275,6 +275,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* EEPROM */ @@ -308,12 +310,16 @@ #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_SPI_FLASH_STMICRO +/* DSPI */ +#define CONFIG_FSL_DSPI +#define CONFIG_SPI_FLASH_ATMEL +#endif + /* DM SPI */ #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) #define CONFIG_CMD_SF #define CONFIG_DM_SPI_FLASH #endif -#endif /* * Video diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 2dbb5f70a9..55b909ceac 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -97,6 +97,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h new file mode 100644 index 0000000000..26136a52ce --- /dev/null +++ b/include/configs/lwmon5.h @@ -0,0 +1,633 @@ +/* + * (C) Copyright 2007-2013 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * lwmon5.h - configuration for lwmon5 board + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Liebherr extra version info + */ +#define CONFIG_IDENT_STRING " - v2.0" + +/* + * High Level Configuration Options + */ +#define CONFIG_LWMON5 1 /* Board is lwmon5 */ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_440 1 /* ... PPC440 family */ + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_SYS_TEXT_BASE 0xFFF80000 +#define CONFIG_HOSTNAME lwmon5 + +#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ + +#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */ + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ +#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */ +#define CONFIG_MISC_INIT_R /* Call misc_init_r */ +#define CONFIG_BOARD_RESET /* Call board_reset */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */ +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */ + +#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ +#define CONFIG_SYS_LIME_BASE_0 0xc0000000 +#define CONFIG_SYS_LIME_BASE_1 0xc1000000 +#define CONFIG_SYS_LIME_BASE_2 0xc2000000 +#define CONFIG_SYS_LIME_BASE_3 0xc3000000 +#define CONFIG_SYS_FPGA_BASE_0 0xc4000000 +#define CONFIG_SYS_FPGA_BASE_1 0xc4200000 +#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ +#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000) +#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000) +#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000) + +#define CONFIG_SYS_USB2D0_BASE 0xe0000100 +#define CONFIG_SYS_USB_DEVICE 0xe0000000 +#define CONFIG_SYS_USB_HOST 0xe0000400 + +/* + * Initial RAM & stack pointer + * + * On LWMON5 we use D-cache as init-ram and stack pointer. We also move + * the POST_WORD from OCM to a 440EPx register that preserves it's + * content during reset (GPT0_COMP6). This way we reserve the OCM (16k) + * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.) + */ +#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* unused GPT0 COMP reg */ +#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) +#define CONFIG_SYS_OCM_SIZE (16 << 10) +/* 440EPx errata CHIP 11: don't use last 4kbytes */ +#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) + +/* Additional registers for watchdog timer post test */ +#define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2) +#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1) +#define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR +#define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR +#define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000 +#define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000 +#define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001 +#define CONFIG_SYS_OCM_STATUS_OK 0x00009A00 +#define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300 +#define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00 + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CONFIG_SYS_FLASH0 0xFC000000 +#define CONFIG_SYS_FLASH1 0xF8000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } + +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ +#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */ + +#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +/* + * DDR SDRAM + */ +#define CONFIG_SYS_MBYTES_SDRAM 256 +#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ +#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ +#define CONFIG_DDR_ECC /* enable ECC */ + +/* POST support */ +#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ + CONFIG_SYS_POST_CPU | \ + CONFIG_SYS_POST_ECC | \ + CONFIG_SYS_POST_ETHER | \ + CONFIG_SYS_POST_FPU | \ + CONFIG_SYS_POST_I2C | \ + CONFIG_SYS_POST_MEMORY | \ + CONFIG_SYS_POST_OCM | \ + CONFIG_SYS_POST_RTC | \ + CONFIG_SYS_POST_SPR | \ + CONFIG_SYS_POST_UART | \ + CONFIG_SYS_POST_SYSMON | \ + CONFIG_SYS_POST_WATCHDOG | \ + CONFIG_SYS_POST_DSP | \ + CONFIG_SYS_POST_BSPEC1 | \ + CONFIG_SYS_POST_BSPEC2 | \ + CONFIG_SYS_POST_BSPEC3 | \ + CONFIG_SYS_POST_BSPEC4 | \ + CONFIG_SYS_POST_BSPEC5) + +/* Define here the base-addresses of the UARTs to test in POST */ +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ + CONFIG_SYS_NS16550_COM2 } + +#define CONFIG_POST_UART { \ + "UART test", \ + "uart", \ + "This test verifies the UART operation.", \ + POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \ + &uart_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_UART \ + } + +#define CONFIG_POST_WATCHDOG { \ + "Watchdog timer test", \ + "watchdog", \ + "This test checks the watchdog timer.", \ + POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \ + &lwmon5_watchdog_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_WATCHDOG \ + } + +#define CONFIG_POST_BSPEC1 { \ + "dsPIC init test", \ + "dspic_init", \ + "This test returns result of dsPIC READY test run earlier.", \ + POST_RAM | POST_ALWAYS, \ + &dspic_init_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_BSPEC1 \ + } + +#define CONFIG_POST_BSPEC2 { \ + "dsPIC test", \ + "dspic", \ + "This test gets result of dsPIC POST and dsPIC version.", \ + POST_RAM | POST_ALWAYS, \ + &dspic_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_BSPEC2 \ + } + +#define CONFIG_POST_BSPEC3 { \ + "FPGA test", \ + "fpga", \ + "This test checks FPGA registers and memory.", \ + POST_RAM | POST_ALWAYS | POST_MANUAL, \ + &fpga_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_BSPEC3 \ + } + +#define CONFIG_POST_BSPEC4 { \ + "GDC test", \ + "gdc", \ + "This test checks GDC registers and memory.", \ + POST_RAM | POST_ALWAYS | POST_MANUAL,\ + &gdc_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_BSPEC4 \ + } + +#define CONFIG_POST_BSPEC5 { \ + "SYSMON1 test", \ + "sysmon1", \ + "This test checks GPIO_62_EPX pin indicating power failure.", \ + POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \ + &sysmon1_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_BSPEC5 \ + } + +#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ +#define CONFIG_LOGBUFFER +/* Reserve GPT0_COMP1-COMP5 for logbuffer header */ +#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1) +#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE) +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_PPC4XX +#define CONFIG_SYS_I2C_PPC4XX_CH0 +#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 +#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F + +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */ +#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */ +#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */ +#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */ +#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */ +#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */ +#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */ + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */ + /* 64 byte page write mode using*/ + /* last 6 bits of the address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE + +#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ +#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ +#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */ + +#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \ + CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\ + CONFIG_SYS_I2C_EEPROM_MB_ADDR, \ + CONFIG_SYS_I2C_DSPIC_ADDR, \ + CONFIG_SYS_I2C_DSPIC_2_ADDR, \ + CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\ + CONFIG_SYS_I2C_DSPIC_IO_ADDR } + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +/* Update size in "reg" property of NOR FLASH device tree nodes */ +#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE + +#define CONFIG_FIT /* enable FIT image support */ + +#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ + +#define CONFIG_PREBOOT "setenv bootdelay 15" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=lwmon5\0" \ + "netdev=eth0\0" \ + "unlock=yes\0" \ + "logversion=2\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ + "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\ + "flash_nfs=run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};" \ + "run nfsargs addip addtty addmisc;bootm\0" \ + "rootpath=/opt/eldk/ppc_4xxFP\0" \ + "bootfile=/tftpboot/lwmon5/uImage\0" \ + "kernel_addr=FC000000\0" \ + "ramdisk_addr=FC180000\0" \ + "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ + "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \ + "cp.b 200000 FFF80000 80000\0" \ + "upd=run load update\0" \ + "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \ + "autoscr 200000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_PPC4xx_EMAC +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 300 + +#define CONFIG_HAS_ETH0 +#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 1 + +/* Video console */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_MB862xx +#define CONFIG_VIDEO_MB862xx_ACCEL +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_CONSOLE_EXTRA_INFO +#define VIDEO_FB_16BPP_PIXEL_SWAP +#define VIDEO_FB_16BPP_WORD_SWAP + +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN + +/* + * USB/EHCI + */ +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */ +#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300 +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */ +#define CONFIG_USB_STORAGE + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM + +#ifdef CONFIG_VIDEO +#define CONFIG_CMD_BMP +#endif + +#ifdef CONFIG_440EPX +#define CONFIG_CMD_USB +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SUPPORT_VFAT + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ + +#ifndef DEBUG +#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ +#endif +#define CONFIG_WD_PERIOD 40000 /* in usec */ +#define CONFIG_WD_MAX_RATE 66600 /* in ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the 40x Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ + +/* + * External Bus Controller (EBC) Setup + */ +#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CONFIG_SYS_EBC_PB0AP 0x03000280 +#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000) + +/* Memory Bank 1 (Lime) initialization */ +#define CONFIG_SYS_EBC_PB1AP 0x01004380 +#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000) + +/* Memory Bank 2 (FPGA) initialization */ +#define CONFIG_SYS_EBC_PB2AP 0x01004400 +#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000) + +/* Memory Bank 3 (FPGA2) initialization */ +#define CONFIG_SYS_EBC_PB3AP 0x01004400 +#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000) + +#define CONFIG_SYS_EBC_CFG 0xb8400000 + +/* + * Graphics (Fujitsu Lime) + */ +/* SDRAM Clock frequency adjustment register */ +#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038 +#if 1 /* 133MHz is not tested enough, use 100MHz for now */ +/* Lime Clock frequency is to set 100MHz */ +#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000 +#else +/* Lime Clock frequency for 133MHz */ +#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000 +#endif + +/* SDRAM Parameter register */ +#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC +/* + * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars + * and pixel flare on display when 133MHz was configured. According to + * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed + * Grade + */ +#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ +#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3 +#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ +#else +#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2 +#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ +#endif + +/* + * GPIO Setup + */ +#define CONFIG_SYS_GPIO_PHY1_RST 12 +#define CONFIG_SYS_GPIO_FLASH_WP 14 +#define CONFIG_SYS_GPIO_PHY0_RST 22 +#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49 +#define CONFIG_SYS_GPIO_DSPIC_READY 51 +#define CONFIG_SYS_GPIO_CAN_ENABLE 53 +#define CONFIG_SYS_GPIO_LSB_ENABLE 54 +#define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55 +#define CONFIG_SYS_GPIO_HIGHSIDE 56 +#define CONFIG_SYS_GPIO_EEPROM_INT_WP 57 +#define CONFIG_SYS_GPIO_BOARD_RESET 58 +#define CONFIG_SYS_GPIO_LIME_S 59 +#define CONFIG_SYS_GPIO_LIME_RST 60 +#define CONFIG_SYS_GPIO_SYSMON_STATUS 62 +#define CONFIG_SYS_GPIO_WATCHDOG 63 + +#define GPIO49_VAL 1 + +/* + * PPC440 GPIO Configuration + */ +#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +{ \ +/* GPIO Core 0 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ +}, \ +{ \ +/* GPIO Core 1 */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ +} \ +} + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index 35058e222a..8853d8fcc0 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -172,6 +172,8 @@ #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ #endif diff --git a/include/configs/magnesium.h b/include/configs/magnesium.h deleted file mode 100644 index 3364bde71f..0000000000 --- a/include/configs/magnesium.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (C) 2010 Heiko Schocher <hs@denx.de> - * - * based on: - * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* include common defines/options for all imx27lite related boards */ -#include "imx27lite-common.h" - -/* - * SoC Configuration - */ -#define CONFIG_MAGNESIUM -#define CONFIG_HOSTNAME magnesium -#define CONFIG_BOARDNAME "Projectiondesign magnesium\n" - -/* - * Flash & Environment - */ -#define CONFIG_SYS_FLASH_SECT_SZ 0x8000 /* 64KB sect size */ -#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x40000) -#define PHYS_FLASH_SIZE 0x800000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Env sector Size */ - -/* - * NAND - */ -#define CONFIG_SYS_NAND_LARGEPAGE - -/* - * SD/MMC - */ -#define CONFIG_MXC_MCI_REGS_BASE 0x10013000 - -/* - * MTD partitions - */ -#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0" -#define MTDPARTS_DEFAULT \ - "mtdparts=" \ - "physmap-flash.0:" \ - "256k(U-Boot)," \ - "7680k(user)," \ - "128k(env1)," \ - "128k(env2);" \ - "mxc_nand.0:" \ - "128k(IPL-SPL)," \ - "4m(kernel)," \ - "22m(rootfs)," \ - "-(userfs)" - -#endif /* __CONFIG_H */ diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h deleted file mode 100644 index 45a4a7541c..0000000000 --- a/include/configs/mv88f6281gtw_ge.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_MV88F6281GTW_GE_H -#define _CONFIG_MV88F6281GTW_GE_H - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nMarvell-MV88F6281GTW_GE" - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_MACH_MV88F6281GTW_GE /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FAT -#define CONFIG_CMD_PING -#define CONFIG_CMD_SF -#define CONFIG_CMD_USB - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* Unwanted stuffs from mv-common.h */ -#undef CONFIG_CMD_EXT2 -#undef CONFIG_CMD_JFFS2 -#undef CONFIG_CMD_FAT -#undef CONFIG_CMD_UBI -#undef CONFIG_CMD_UBIFS -#undef CONFIG_RBTREE - -/* - * Environment variables configurations - */ -#ifdef CONFIG_SPI_FLASH -#define CONFIG_ENV_IS_IN_SPI_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */ -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ -#endif -#define CONFIG_ENV_SIZE 0x1000 /* 4k */ -#define CONFIG_ENV_ADDR 0x30000 -#define CONFIG_ENV_OFFSET 0x30000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "${x_bootcmd_usb}; bootm 0x6400000;" - -#define CONFIG_MTDPARTS "spi0.0:512k(uboot)," \ - "512k@512k(psm),2m@1m(kernel),13m@3m(rootfs)\0" - -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \ - "x_bootcmd_kernel=cp.b 0xE8100000 0x6400000 0x200000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=/dev/mtdblock3 ro rootfstype=squashfs\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_MV88E61XX_SWITCH /* Enable mv88e61xx switch driver */ -#endif /* CONFIG_CMD_NET */ - -#endif /* _CONFIG_MV88F6281GTW_GE_H */ diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index bd7216e47b..04140865f4 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -115,6 +115,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ /* RTC */ #define CONFIG_RTC_IMXDI diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index c9983f3f58..6bfdaa6432 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -42,6 +42,8 @@ */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_MXC_SPI #define CONFIG_MXC_GPIO diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h deleted file mode 100644 index 373cfcbc79..0000000000 --- a/include/configs/mx51_efikamx.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * Configuration settings for the MX51EVK Board - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -/* An i.MX51 CPU */ -#define CONFIG_MX51 - -#define machine_is_efikamx() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKAMX) -#define machine_is_efikasb() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKASB) - -#include <asm/arch/imx-regs.h> - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_SYS_TEXT_BASE 0x97800000 - -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF - -/* - * Bootloader Components Configuration - */ -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IDE -#define CONFIG_CMD_DATE - -/* - * Environmental settings - */ - -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) -#define CONFIG_ENV_SIZE (4 * 1024) - -/* - * ATAG setup - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_OF_LIBFDT 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT - -/* - * Hardware drivers - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_MXC_GPIO - -/* - * SPI Interface - */ -#ifdef CONFIG_CMD_SPI - -#define CONFIG_HARD_SPI -#define CONFIG_MXC_SPI -#define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) - -/* SPI FLASH */ -#ifdef CONFIG_CMD_SF - -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SF_DEFAULT_CS 1 -#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) -#define CONFIG_SF_DEFAULT_SPEED 25000000 - -#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_MAX_HZ 25000000 -#define CONFIG_ENV_SPI_MODE (SPI_MODE_0) -#define CONFIG_FSL_ENV_IN_SF -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SYS_NO_FLASH - -#else -#define CONFIG_ENV_IS_NOWHERE -#endif - -/* SPI PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL -#define CONFIG_FSL_PMIC_BUS 0 -#define CONFIG_FSL_PMIC_CS (0 | 120 << 8) -#define CONFIG_FSL_PMIC_CLK 25000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX -#endif - -/* - * MMC Configs - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2 -#endif - -/* - * ATA/IDE - */ -#ifdef CONFIG_CMD_IDE -#define CONFIG_LBA48 -#undef CONFIG_IDE_LED -#undef CONFIG_IDE_RESET - -#define CONFIG_MX51_PATA - -#define __io - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 - -#define CONFIG_SYS_ATA_BASE_ADDR 0x83fe0000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0xa0 -#define CONFIG_SYS_ATA_REG_OFFSET 0xa0 -#define CONFIG_SYS_ATA_ALT_OFFSET 0xd8 - -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_IDE_PREINIT -#define CONFIG_MXC_ATA_PIO_MODE 4 -#endif - -/* - * USB - */ -#define CONFIG_CMD_USB -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_MX5 -#define CONFIG_USB_ULPI -#define CONFIG_USB_ULPI_VIEWPORT -#define CONFIG_MXC_USB_PORT 1 -#if (CONFIG_MXC_USB_PORT == 0) -#define CONFIG_MXC_USB_PORTSC (1 << 28) -#define CONFIG_MXC_USB_FLAGS MXC_EHCI_INTERNAL_PHY -#else -#define CONFIG_MXC_USB_PORTSC (2 << 30) -#define CONFIG_MXC_USB_FLAGS 0 -#endif -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_KEYBOARD -#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP -#define CONFIG_PREBOOT -/* USB NET */ -#ifdef CONFIG_CMD_NET -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#endif -#endif /* CONFIG_CMD_USB */ - -/* - * Filesystems - */ -#ifdef CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BOOTDELAY 3 -#define CONFIG_LOADADDR 0x90800000 - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x90000000 -#define CONFIG_SYS_MEMTEST_END 0x90010000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_CMDLINE_EDITING - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_SYS_DDR_CLKSEL 0 -#define CONFIG_SYS_CLKTL_CBCDR 0x59E35145 -#define CONFIG_SYS_MAIN_PWR_ON - -#endif diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 0479195d6d..b889c254cc 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -48,6 +48,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* MMC Configs */ diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 82c8af802f..4f304ed89f 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -41,6 +41,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* PMIC Configs */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index ad2629da72..3a65861e5e 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -76,6 +76,8 @@ /* I2C Configs */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* PMIC Controller */ diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index bcdb054360..e46f2eeecb 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -38,6 +38,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* MMC Configs */ diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 634a09f349..6e89dd1455 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -14,7 +14,7 @@ #define CONFIG_SPL_MMC_SUPPORT #include "imx6_spl.h" -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 11cf538b0a..1c998058a9 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -51,6 +51,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 6a57841f5f..9dcc64ea57 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -11,7 +11,7 @@ #include "mx6_common.h" -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) @@ -80,6 +80,10 @@ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "console=" CONFIG_CONSOLE_DEV "\0" \ + "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ + "dfu_alt_info_spl=spl raw 0x400\0" \ + "dfu_alt_info_img=u-boot raw 0x10000\0" \ + "dfu_alt_info=spl raw 0x400\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ @@ -238,6 +242,18 @@ #define CONFIG_G_DNL_VENDOR_NUM 0x0525 #define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 #define CONFIG_G_DNL_MANUFACTURER "FSL" + +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 + +/* USB Device Firmware Update support */ +#define CONFIG_CMD_DFU +#define CONFIG_USB_FUNCTION_DFU +#define CONFIG_DFU_MMC +#define CONFIG_DFU_SF #endif #endif /* __MX6QSABRE_COMMON_CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 5f635ca6c5..e9e3b27f36 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -44,6 +44,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 04d53a7f08..ae39503542 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -14,7 +14,6 @@ #ifdef CONFIG_SPL #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT #include "imx6_spl.h" #endif @@ -36,6 +35,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 @@ -197,6 +198,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/ #endif -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 74d04a088f..edf7d3f93a 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -15,7 +15,6 @@ #ifdef CONFIG_SPL #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT #include "imx6_spl.h" #endif @@ -128,6 +127,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 @@ -177,7 +178,7 @@ #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL #define CONFIG_CMD_TIME diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 4a2280bc18..d5faae6a7b 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -14,14 +14,15 @@ #include "mx6_common.h" #include <asm/imx-common/gpio.h> +#define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) + /* SPL options */ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT #include "imx6_spl.h" -#define CONFIG_ROM_UNIFIED_SECTIONS -#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -34,11 +35,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_CMD_FUSE -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif - /* MMC Configs */ #ifdef CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR @@ -53,24 +49,21 @@ #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #endif -#undef CONFIG_BOOTM_NETBSD -#undef CONFIG_BOOTM_PLAN9 -#undef CONFIG_BOOTM_RTEMS - -#undef CONFIG_CMD_EXPORTENV -#undef CONFIG_CMD_IMPORTENV - /* I2C configs */ #define CONFIG_CMD_I2C #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_SPEED 100000 -#endif - -#define PHYS_SDRAM_SIZE SZ_512M -#undef CONFIG_CMD_IMLS +/* PMIC only for 9X9 EVK */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#endif #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 @@ -80,7 +73,7 @@ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx6ul-14x14-evk.dtb\0" \ + "fdt_file=undefined\0" \ "fdt_addr=0x83000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ @@ -134,9 +127,19 @@ "fi; " \ "else " \ "bootz; " \ - "fi;\0" + "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "if test $board_name = EVK && test $board_rev = 9X9; then " \ + "setenv fdt_file imx6ul-9x9-evk.dtb; fi; " \ + "if test $board_name = EVK && test $board_rev = 14X14; then " \ + "setenv fdt_file imx6ul-14x14-evk.dtb; fi; " \ + "if test $fdt_file = undefined; then " \ + "echo WARNING: Could not determine dtb to use; fi; " \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ "mmc dev ${mmcdev};" \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -150,9 +153,6 @@ "else run netboot; fi" /* Miscellaneous configurable options */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) @@ -238,9 +238,8 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_MICREL -#define CONFIG_FEC_DMA_MINALIGN 64 #endif -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL #endif diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h new file mode 100644 index 0000000000..ea2be496e0 --- /dev/null +++ b/include/configs/mx7_common.h @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7_COMMON_H +#define __MX7_COMMON_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> + +#ifndef CONFIG_MX7 +#define CONFIG_MX7 +#endif + +/* Timer settings */ +#define CONFIG_MXC_GPT_HCLK +#define CONFIG_SYSCOUNTER_TIMER +#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ + +/* Enable iomux-lpsr support */ +#define CONFIG_IOMUX_LPSR +#define CONFIG_IMX_FIXED_IVT_OFFSET + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_ROM_UNIFIED_SECTIONS +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_LOADADDR 0x80800000 +#define CONFIG_SYS_TEXT_BASE 0x87800000 + +#ifndef CONFIG_BOOTDELAY +#define CONFIG_BOOTDELAY 3 +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Filesystems and image support */ +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT + +/* Miscellaneous configurable options */ +#undef CONFIG_CMD_IMLS +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +/* GPIO */ +#define CONFIG_MXC_GPIO +#define CONFIG_CMD_GPIO + +/* UART */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +/* MMC */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC + +/* Fuses */ +#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP + +#endif diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h new file mode 100644 index 0000000000..f16f9c1271 --- /dev/null +++ b/include/configs/mx7dsabresd.h @@ -0,0 +1,191 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D SABRESD board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_SABRESD_CONFIG_H +#define __MX7D_SABRESD_CONFIG_H + +#include "mx7_common.h" + +#define CONFIG_DBG_MONITOR +#define PHYS_SDRAM_SIZE SZ_1G + +/* Network */ +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_BROADCOM +/* ENET1 */ +#define IMX_FEC_BASE ENET_IPS_BASE_ADDR + +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV + +/* I2C configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx7d-sdb.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX7 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_IMX_THERMAL + +#endif /* __CONFIG_H */ diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h deleted file mode 100644 index dd70adccea..0000000000 --- a/include/configs/nhk8815.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * (C) Copyright 2005 - * STMicroelectronics. - * Configuration settings for the "Nomadik Hardware Kit" NHK-8815, - * the evaluation board for the Nomadik 8815 System on Chip. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <nomadik.h> - -#define CONFIG_NOMADIK_8815 /* cpu variant */ - -#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */ - -/* commands */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_SYS_NO_FLASH -/* There is NAND storage */ -#define CONFIG_NAND_NOMADIK -#define CONFIG_CMD_JFFS2 - -/* user interface */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_LOAD_ADDR 0x800000 /* default load address */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* boot config */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG -#define CONFIG_BOOTDELAY 1 -#define CONFIG_BOOTARGS "root=/dev/ram0 console=ttyAMA1,115200n8 init=linuxrc" -#define CONFIG_BOOTCOMMAND "fsload 0x100000 kernel.uimg;" \ - " fsload 0x800000 initrd.gz.uimg;" \ - " bootm 0x100000 0x800000" - -/* memory-related information */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0x08000000 /* SDR-SDRAM BANK #2*/ -#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) -/* The IPL loads us at 0, tell so to u-boot. Put stack pointer 1M into RAM */ -#define CONFIG_SYS_TEXT_BASE 0x00000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + (1<<20)) - -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024) - -#define CONFIG_BOARD_LATE_INIT /* call board_late_init during start up */ - -/* timing informazion */ -#define CONFIG_SYS_TIMERBASE 0x101E2000 - -/* serial port (PL011) configuration */ -#define CONFIG_PL011_SERIAL -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_SERIAL0 0x101FD000 -#define CFG_SERIAL1 0x101FB000 - -#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 } -#define CONFIG_PL011_CLOCK 48000000 - -/* i2c, for the port extenders (uses gpio.c in board directory) */ -#ifndef __ASSEMBLY__ -#include <asm/arch/gpio.h> -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT 1 /* I2C bit-banged */ -#define I2C_SOFT_DEFS -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -#define __SDA 63 -#define __SCL 62 -#define I2C_SDA(x) nmk_gpio_set(__SDA, x) -#define I2C_SCL(x) nmk_gpio_set(__SCL, x) -#define I2C_READ (nmk_gpio_get(__SDA)!=0) -#define I2C_ACTIVE nmk_gpio_dir(__SDA, 1) -#define I2C_TRISTATE nmk_gpio_dir(__SDA, 0) -#define I2C_DELAY (udelay(2)) -#endif /* __ASSEMBLY__ */ - -/* Ethernet */ -#define PCI_MEMORY_VADDR 0xe8000000 -#define PCI_IO_VADDR 0xee000000 -#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) -#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR) - -#define CONFIG_SMC91111 /* Using SMC91c111*/ -#define CONFIG_SMC91111_BASE 0x34000300 -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_IP_DEFRAG /* Allows faster download, TFTP and NFS */ -#define CONFIG_TFTP_BLOCKSIZE 4096 -#define CONFIG_NFS_READ_SIZE 4096 - -/* Storage information: onenand and nand */ -#define CONFIG_CMD_ONENAND -#define CONFIG_MTD_ONENAND_VERIFY_WRITE -#define CONFIG_SYS_ONENAND_BASE 0x30000000 - -#define CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 /* SMPS0n */ - -/* - * Filesystem information - * - * Since U-Boot has been loaded to RAM by vendor code, we could use - * either or both OneNand and Nand. However, we need to know where the - * filesystem lives. Comments below report vendor-selected partitions - */ -#ifdef CONFIG_BOOT_ONENAND - /* Partition Size Start - * XloaderTOC + X-Loader 256KB 0x00000000 - * Memory init function 256KB 0x00040000 - * U-Boot + env 2MB 0x00080000 - * Sysimage (kernel + ramdisk) 4MB 0x00280000 - * JFFS2 Root filesystem 22MB 0x00680000 - * JFFS2 User Data 227.5MB 0x01C80000 - */ -# define CONFIG_JFFS2_DEV "onenand0" -# define CONFIG_JFFS2_PART_SIZE 0x01600000 -# define CONFIG_JFFS2_PART_OFFSET 0x00680000 -# define CONFIG_ENV_IS_IN_ONENAND -# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */ -# define CONFIG_ENV_ADDR (0x00280000 - CONFIG_ENV_SIZE) - -#else /* BOOT_NAND */ - /* Partition Size Start - * XloaderTOC + X-Loader 256KB 0x00000000 - * Memory init function 256KB 0x00040000 - * U-Boot + env 2MB 0x00080000 - * Kernel Image 3MB 0x00280000 - * JFFS2 Root filesystem 22MB 0x00580000 - * JFFS2 User Data 100.5MB 0x01b80000 - */ -# define CONFIG_JFFS2_DEV "nand0" -# define CONFIG_JFFS2_NAND 1 /* For the jffs2 support*/ -# define CONFIG_JFFS2_PART_SIZE 0x01600000 -# define CONFIG_JFFS2_PART_OFFSET 0x00580000 -# define CONFIG_ENV_IS_IN_NAND -# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */ -# define CONFIG_ENV_OFFSET (0x00280000 - CONFIG_ENV_SIZE) - -#endif /* CONFIG_BOOT_ONENAND */ - -/* this is needed to make hello_world.c and other stuff happy */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index dd4cb0f893..b1137713e1 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -43,6 +43,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_EDID diff --git a/include/configs/novena.h b/include/configs/novena.h index 0970fd7548..cd426be18c 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -102,6 +102,8 @@ /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_MXC diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index f309b2e83b..bf986f86cb 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -121,7 +121,6 @@ /* * Board NAND Info. */ -#define CONFIG_SYS_NAND_QUIET_TEST 1 #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h index 713df3cf80..3f777b6aeb 100644 --- a/include/configs/omap3_cairo.h +++ b/include/configs/omap3_cairo.h @@ -70,7 +70,6 @@ /* * Board NAND Info. */ -#define CONFIG_SYS_NAND_QUIET_TEST 1 #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 7e7f6f2e9f..0ebe5c118b 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -15,6 +15,7 @@ #define CONFIG_OMAP /* This is TI OMAP core */ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 04433edcc5..4409103f49 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -19,6 +19,8 @@ #include <configs/ti_omap3_common.h> #include <asm/mach-types.h> +#undef CONFIG_BOOTDELAY + /* * Display CPU and Board information */ @@ -81,74 +83,33 @@ /*#undef CONFIG_ENV_IS_NOWHERE*/ +#ifndef CONFIG_SPL_BUILD + +#include <config_distro_defaults.h> + +/* Environment */ +#define ENV_DEVICE_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define MEM_LAYOUT_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "scriptaddr=0x87E00000\0" \ + "pxefile_addr_r=0x87F00000\0" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#include <config_distro_bootcmd.h> + + #define CONFIG_EXTRA_ENV_SETTINGS \ - "usbtty=cdc_acm\0" \ - "loadaddr=0x82000000\0" \ - "dtbaddr=0x81600000\0" \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "usbtty=cdc_acm\0" \ - "console=ttyO2,115200n8\0" \ - "mpurate=auto\0" \ - "vram=12M\0" \ - "dvimode=1024x768MR-16@60\0" \ - "defaultdisplay=dvi\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "nandroot=/dev/mtdblock4 rw\0" \ - "nandrootfstype=jffs2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootz ${loadaddr}\0" \ - "mmcbootfdt=echo Booting with DT from mmc ...; " \ - "bootz ${loadaddr} - ${dtbaddr}\0" \ - "nandboot=echo Booting from onenand ...; " \ - "run nandargs; " \ - "onenand read ${loadaddr} 280000 400000; " \ - "bootz ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loadzimage; then " \ - "if test -n $dtbfile; then " \ - "if run loadfdt; then " \ - "run mmcbootfdt;" \ - "fi;" \ - "fi;" \ - "run mmcboot;" \ - "fi;" \ - "fi;" \ - "run nandboot;" \ + ENV_DEVICE_SETTINGS \ + MEM_LAYOUT_SETTINGS \ + BOOTENV + +#endif /* * FLASH and environment organization diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 8bd36340e7..ecd5615859 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -105,7 +105,6 @@ * Board NAND Info. */ #define CONFIG_SYS_NAND_BASE NAND_BASE -#define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h deleted file mode 100644 index 9e2cf7333c..0000000000 --- a/include/configs/omap3_mvblx.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * MATRIX VISION GmbH mvBlueLYNX-X - * - * Derived from omap3_beagle.h: - * (C) Copyright 2006-2008 - * Texas Instruments. - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * - * Configuration settings for the TI OMAP3530 Beagle board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */ -#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 - -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap.h> - -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_MISC_INIT_R - -#define CONFIG_OF_LIBFDT 1 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 -#define CONFIG_SERIAL_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 -#define CONFIG_SERIAL1 1 /* UART1 */ - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - -/* silent console by default */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 -#define CONFIG_SILENT_CONSOLE 1 - -/* USB */ -#define CONFIG_USB_MUSB_UDC 1 -#define CONFIG_USB_OMAP3 1 -#define CONFIG_TWL4030_USB 1 - -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 -#define CONFIG_USBD_VENDORID 0x164c -#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201 -#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201 -#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH" -#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X" - -/* no FLASH available */ -#define CONFIG_SYS_NO_FLASH - -/* commands to include */ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_FPGA_LOADMK - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_OMAP34XX - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER 1 - -/* Environment information */ -#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */ -#define CONFIG_BOOTDELAY 0 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "silent=true\0" \ - "loadaddr=0x82000000\0" \ - "usbtty=cdc_acm\0" \ - "console=ttyO0,115200n8\0" \ - "mpurate=600\0" \ - "vram=12M\0" \ - "dvimode=1024x768-24@60\0" \ - "defaultdisplay=dvi\0" \ - "loadfpga=if ext2load mmc ${mmcdev}:2 ${loadaddr} "\ - "/lib/firmware/mvblx/${fpgafilename}; then " \ - "fpga load 0 ${loadaddr} ${filesize}; " \ - "fi;\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype} " \ - "mvfw.fpgavers=${fpgavers} " \ - "${cmdline_suffix}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "mmcbootcmd= " \ - "echo Trying mmc${mmcdev}; " \ - "mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loading boot environment from mmc${mmcdev}; " \ - "run importbootenv; " \ - "fi;" \ - "run loadfpga; " \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "fi;" \ - "fi\0" - -#define CONFIG_BOOTCOMMAND \ - "setenv mmcdev 1;" \ - "run mmcbootcmd || " \ - "setenv mmcdev 0;" \ - "run mmcbootcmd" - - -#define CONFIG_AUTO_COMPLETE 1 -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */ -#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */ -#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -#define CONFIG_ENV_IS_NOWHERE 1 - -/*---------------------------------------------------------------------------- - * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family) - *---------------------------------------------------------------------------- - */ -#if defined(CONFIG_CMD_NET) - #define CONFIG_SMC911X 1 - #define CONFIG_SMC911X_32_BIT - #define CONFIG_SMC911X_BASE 0x2C000000 -#endif /* (CONFIG_CMD_NET) */ - -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA -#define CONFIG_FPGA_CYCLON2 -#define CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_EEPROM_BUS_NUM 2 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_OMAP3_SPI - -#define CONFIG_SYS_CACHELINE_SIZE 64 - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 53ff61d10c..3b1e5d7ff8 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -88,7 +88,6 @@ #endif /* CONFIG_NAND */ /* Board NAND Info. */ -#define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ /* Environment information */ diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h deleted file mode 100644 index f43e477ad2..0000000000 --- a/include/configs/omap3_sdp3430.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments Incorporated. - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * Nishanth Menon <nm@ti.com> - * - * Configuration settings for the 3430 TI SDP3430 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* TODO: REMOVE THE FOLLOWING - * Retained the following till size.h is removed in u-boot - */ -#include <linux/sizes.h> -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */ -#define CONFIG_OMAP_COMMON -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 - -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap.h> - -/* - * NOTE: these #defines presume standard SDP jumper settings. - * In particular: - * - 26 MHz clock (not 19.2 or 38.4 MHz) - * - Boot from 128MB NOR, not NAND or OneNAND - * - * At this writing, OMAP3 U-Boot support doesn't permit concurrent - * support for all the flash types the board supports. - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#define CONFIG_OF_LIBFDT 1 - -/* - * Size of malloc() pool - * Total Size Environment - 256k - * Malloc - add 256k - */ -#define CONFIG_ENV_SIZE (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10)) - -/*--------------------------------------------------------------------------*/ - -/* - * Hardware drivers - */ - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER 1 - -/* - * serial port - NS16550 compatible - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be - * swapped with UART2 via jumpering. Downsides of using J8: it doesn't - * support UART boot (that's only for UART3); it prevents sharing a Linux - * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards. - * - * UART boot uses UART3 on J9, and the SDP user's guide says to use - * that for console. Downsides of using J9: you can't use IRDA too; - * since UART3 isn't in the CORE power domain, it may be a bit less - * usable in certain PM-sensitive debug scenarios. - */ -#undef CONSOLE_J9 /* else J8/UART1 (innermost) */ - -#ifdef CONSOLE_J9 -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 /* UART3 */ -#else -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 -#define CONFIG_SERIAL1 1 /* UART1 */ -#endif - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* - * I2C for power management setup - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_OMAP34XX - -/* OMITTED: single 1 Gbit MT29F1G NAND flash */ - -/* - * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash - */ -#define CONFIG_SYS_FLASH_BASE 0x10000000 -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */ -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ - -#define CONFIG_SYS_FLASH_CFI_WIDTH 2 -#define PHYS_FLASH_SIZE (128 << 20) -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */ - -/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10) -#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE) -/*--------------------------------------------------------------------------*/ - -/* Enabled commands */ -#define CONFIG_CMD_DHCP /* DHCP Support */ -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ -#define CONFIG_CMD_MMC /* MMC support */ - -/*--------------------------------------------------------------------------*/ -/* - * MMC boot support - */ - -#if defined(CONFIG_CMD_MMC) -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 -#endif - -/*---------------------------------------------------------------------------- - * SMSC9115 Ethernet from SMSC9118 family - *---------------------------------------------------------------------------- - */ -#if defined(CONFIG_CMD_NET) - -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE DEBUG_BASE -#define CONFIG_LAN91C96_EXT_PHY - -#define CONFIG_BOOTP_SEND_HOSTNAME -/* - * BOOTP fields - */ -#define CONFIG_BOOTP_SUBNETMASK 0x00000001 -#define CONFIG_BOOTP_GATEWAY 0x00000002 -#define CONFIG_BOOTP_HOSTNAME 0x00000004 -#define CONFIG_BOOTP_BOOTPATH 0x00000010 -#endif /* (CONFIG_CMD_NET) */ - -/* - * Environment setup - * - * Default boot order: mmc bootscript, MMC uImage, NOR image. - * Network booting environment must be configured at site. - */ - -/* allow overwriting serial config and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyS0,115200n8\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ - "norargs=setenv bootargs console=${console} " \ - "root=/dev/mtdblock3 rw " \ - "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from MMC/SD ...; " \ - "autoscr ${loadaddr}\0" \ - "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from MMC/SD ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "norboot=echo Booting from NOR ...; " \ - "run norargs; " \ - "bootm 0x80000\0" \ - -#define CONFIG_BOOTCOMMAND \ - "if mmcinit; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run norboot; " \ - "fi; " \ - "fi; " \ - "else run norboot; fi" - -#define CONFIG_AUTO_COMPLETE 1 - -/*--------------------------------------------------------------------------*/ - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg - - * a basic sanity check ONLY - * IF you would like to increase coverage, increase the end address - * or run the test with custom options - */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20)) - -/* Default load address */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) - -/*--------------------------------------------------------------------------*/ - -/* - * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by - * 32KHz clk, or from external sig. This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -/* - * SDRAM Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/*--------------------------------------------------------------------------*/ - -/* - * NOR FLASH usage ... default nCS0: - * - one 256KB sector for U-Boot - * - one 256KB sector for its parameters (not all used) - * - eight sectors (2 MB) for kernel - * - rest for JFFS2 - */ - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) - -/* - * NAND FLASH usage ... default nCS1: - * - four 128KB sectors for X-Loader - * - four 128KB sectors for U-Boot - * - two 128KB sector for its parameters - * - 32 sectors (4 MB) for kernel - * - rest for filesystem - */ - -/* - * OneNAND FLASH usage ... default nCS2: - * - four 128KB sectors for X-Loader - * - two 128KB sectors for U-Boot - * - one 128KB sector for its parameters - * - sixteen sectors (2 MB) for kernel - * - rest for filesystem - */ - -#define CONFIG_SYS_CACHELINE_SIZE 64 - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 86479213fc..18a2924fd4 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -19,6 +19,47 @@ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" #endif +#define DFU_ALT_INFO_MMC \ + "dfu_alt_info_mmc=" \ + "boot part 0 1;" \ + "rootfs part 0 2;" \ + "MLO fat 0 1;" \ + "MLO.raw raw 0x100 0x100;" \ + "u-boot.img.raw raw 0x300 0x400;" \ + "spl-os-args.raw raw 0x80 0x80;" \ + "spl-os-image.raw raw 0x900 0x2000;" \ + "spl-os-args fat 0 1;" \ + "spl-os-image fat 0 1;" \ + "u-boot.img fat 0 1;" \ + "uEnv.txt fat 0 1\0" + +#define DFU_ALT_INFO_EMMC \ + "dfu_alt_info_emmc=" \ + "rawemmc raw 0 3751936;" \ + "boot part 1 1;" \ + "rootfs part 1 2;" \ + "MLO fat 1 1;" \ + "MLO.raw raw 0x100 0x100;" \ + "u-boot.img.raw raw 0x300 0x400;" \ + "spl-os-args.raw raw 0x80 0x80;" \ + "spl-os-image.raw raw 0x900 0x2000;" \ + "spl-os-args fat 1 1;" \ + "spl-os-image fat 1 1;" \ + "u-boot.img fat 1 1;" \ + "uEnv.txt fat 1 1\0" + +#define DFU_ALT_INFO_RAM \ + "dfu_alt_info_ram=" \ + "kernel ram 0x80200000 0x4000000;" \ + "fdt ram 0x80f80000 0x80000;" \ + "ramdisk ram 0x81000000 0x4000000\0" + +#define DFUARGS \ + "dfu_bufsiz=0x10000\0" \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_EMMC \ + DFU_ALT_INFO_RAM + #include <configs/ti_omap5_common.h> #define CONFIG_CONS_INDEX 3 @@ -58,6 +99,27 @@ #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80 #define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79 +/* USB GADGET */ +#define CONFIG_USB_DWC3_PHY_OMAP +#define CONFIG_USB_DWC3_OMAP +#define CONFIG_USB_DWC3 +#define CONFIG_USB_DWC3_GADGET + +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" +#define CONFIG_G_DNL_VENDOR_NUM 0x0403 +#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 +#define CONFIG_USB_GADGET_DUALSPEED + +/* USB Device Firmware Update support */ +#define CONFIG_USB_FUNCTION_DFU +#define CONFIG_DFU_RAM +#define CONFIG_CMD_DFU + +#define CONFIG_DFU_MMC + /* Enabled commands */ #define CONFIG_CMD_DHCP /* DHCP Support */ diff --git a/include/configs/openrd.h b/include/configs/openrd.h deleted file mode 100644 index 72113144b3..0000000000 --- a/include/configs/openrd.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2009 - * Net Insight <www.netinsight.net> - * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> - * - * Based on sheevaplug.h: - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_OPENRD_H -#define _CONFIG_OPENRD_H - -/* - * Version number information - */ -#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE -# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate" -#else -# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT -# define CONFIG_IDENT_STRING "\nOpenRD-Client" -# else -# ifdef CONFIG_BOARD_IS_OPENRD_BASE -# define CONFIG_IDENT_STRING "\nOpenRD-Base" -# else -# error Unknown OpenRD board specified -# endif -# endif -#endif - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_MACH_OPENRD_BASE /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#define CONFIG_SYS_MVFS -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MII -#define CONFIG_CMD_MMC -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB -#define CONFIG_CMD_IDE - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ -#endif -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -#define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x60000 -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ -/* - * Environment is right behind U-Boot in flash. Make sure U-Boot - * doesn't grow into the environment area. - */ -#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "${x_bootcmd_usb}; bootm 0x6400000;" - -#define MTDIDS_DEFAULT "nand0=nand_mtd" -#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\ - "0x400000@0x100000(uImage),"\ - "0x1fb00000@0x500000(rootfs)" - -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \ - "mtdids="MTDIDS_DEFAULT"\0" \ - "mtdparts="MTDPARTS_DEFAULT"\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -# ifdef CONFIG_BOARD_IS_OPENRD_BASE -# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -# else -# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ -# endif -# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE -# define CONFIG_PHY_BASE_ADR 0x0 -# define PHY_NO "88E1121" -# else -# define CONFIG_PHY_BASE_ADR 0x8 -# define PHY_NO "88E1116" -# endif -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_MVEBU_MMC -#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE -#endif /* CONFIG_CMD_MMC */ - -#endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 0d06fce1eb..426ec7246f 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -44,6 +44,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/otc570.h b/include/configs/otc570.h deleted file mode 100644 index 0cada63ef7..0000000000 --- a/include/configs/otc570.h +++ /dev/null @@ -1,252 +0,0 @@ -/* - * (C) Copyright 2010-2011 - * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> - * esd electronic system design gmbh <www.esd.eu> - * - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - * - * Configuation settings for the esd OTC570 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * SoC must be defined first, before hardware.h is included. - * In this case SoC is defined in boards.cfg. - */ -#include <asm/hardware.h> - -/* - * Warning: changing CONFIG_SYS_TEXT_BASE requires - * adapting the initial boot program. - * Since the linker has to swallow that define, we must use a pure - * hex number here! - */ -#define CONFIG_SYS_TEXT_BASE 0x20002000 - -/* - * since a number of boards are not being listed in linux - * arch/arm/tools/mach-types any more, the mach-types have to be - * defined here - */ -#define MACH_TYPE_OTC570 2166 - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ - -/* Misc CPU related */ -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SERIAL_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_MISC_INIT_R /* Call misc_init_r */ - -#define CONFIG_DISPLAY_BOARDINFO /* call checkboard() */ -#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */ -#define CONFIG_PREBOOT /* enable preboot variable */ - -/* - * Hardware drivers - */ - -/* required until arch/arm/include/asm/arch-at91/at91sam9263.h is reworked */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP - -/* general purpose I/O */ -#define CONFIG_AT91_GPIO - -/* Console output */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -/* LCD */ -#define CONFIG_LCD -#undef CONFIG_SPLASH_SCREEN - -#ifdef CONFIG_LCD -# define LCD_BPP LCD_COLOR8 - -# ifndef CONFIG_SPLASH_SCREEN -# define CONFIG_LCD_LOGO -# define CONFIG_LCD_INFO -# undef CONFIG_LCD_INFO_BELOW_LOGO -# endif /* CONFIG_SPLASH_SCREEN */ - -# undef LCD_TEST_PATTERN -# define CONFIG_SYS_WHITE_ON_BLACK -# define CONFIG_ATMEL_LCD -# define CONFIG_SYS_CONSOLE_IS_IN_ENV -# define CONFIG_OTC570_LCD_BASE (CONFIG_SYS_SDRAM_BASE + 0x03fa5000) -# define CONFIG_CMD_BMP -#endif /* CONFIG_LCD */ - -/* RTC and I2C stuff */ -#define CONFIG_RTC_DS1338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_SOFT_SPEED 100000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F - -/* Configure data and clock pins for pio */ -# define I2C_INIT { \ - at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \ - at91_set_pio_output(AT91_PIO_PORTB, 5, 0); \ -} -# define I2C_SOFT_DECLARATIONS -/* Configure data pin as output */ -# define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTB, 4, 0) -/* Configure data pin as input */ -# define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTB, 4, 0) -/* Read data pin */ -# define I2C_READ at91_get_pio_value(AT91_PIO_PORTB, 4) -/* Set data pin */ -# define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTB, 4, bit) -/* Set clock pin */ -# define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTB, 5, bit) -# define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SYS_I2C_SOFT */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NAND -#define CONFIG_CMD_USB -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DATE - -/* LED */ -#define CONFIG_AT91_LED - -/* - * SDRAM: 1 bank, min 32, max 128 MB - * Initialized before u-boot gets started. - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0x20000000 /* ATMEL_BASE_CS1 */ -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 - -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000) - -/* - * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above - * that address while providing maximum stack area below. - */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM0 + 0x1000 - GENERATED_GBL_DATA_SIZE) - -/* DataFlash */ -#ifdef CONFIG_SYS_USE_DATAFLASH -# define CONFIG_ATMEL_DATAFLASH_SPI -# define CONFIG_HAS_DATAFLASH -# define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 -# define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ -# define AT91_SPI_CLK 15000000 -# define DATAFLASH_TCSS (0x1a << 16) -# define DATAFLASH_TCHS (0x1 << 24) -#endif - -/* NOR flash is not populated, disable it */ -#define CONFIG_SYS_NO_FLASH - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -# define CONFIG_NAND_ATMEL -# define CONFIG_SYS_MAX_NAND_DEVICE 1 -# define CONFIG_SYS_NAND_BASE 0x40000000 /* ATMEL_BASE_CS3 */ -# define CONFIG_SYS_NAND_DBW_8 -# define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -# define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) -# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) -#endif - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_FIT -#define CONFIG_NET_RETRY_COUNT 20 -#undef CONFIG_RESET_PHY_R - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE -#define CONFIG_CMD_FAT - -/* CAN */ -#define CONFIG_AT91_CAN - -/* hw-controller addresses */ -#define CONFIG_ET1100_BASE 0x70000000 /* ATMEL_BASE_CS6 */ - -#ifdef CONFIG_SYS_USE_DATAFLASH - -/* bootstrap + u-boot + env in dataflash on CS0 */ -# define CONFIG_ENV_IS_IN_DATAFLASH -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ - 0x8400) -# define CONFIG_ENV_OFFSET 0x4200 -# define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ - CONFIG_ENV_OFFSET) -# define CONFIG_ENV_SIZE 0x4200 - -#elif CONFIG_SYS_USE_NANDFLASH - -/* bootstrap + u-boot + env + linux in nandflash */ -# define CONFIG_ENV_IS_IN_NAND 1 -# define CONFIG_ENV_OFFSET 0xC0000 -# define CONFIG_ENV_SIZE 0x20000 - -#endif - -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ - 128*1024, 0x1000) - -#endif diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index 9d7b650d98..f2a713d0be 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -13,7 +13,6 @@ #include "tegra210-common.h" /* High-level configuration options */ -#define V_PROMPT "Tegra210 (P2371-0000) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-0000" /* Board-specific serial config */ @@ -60,6 +59,4 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define COUNTER_FREQUENCY 38400000 - #endif /* _P2371_0000_H */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h new file mode 100644 index 0000000000..3bdf1961a3 --- /dev/null +++ b/include/configs/p2371-2180.h @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _P2371_2180_H +#define _P2371_2180_H + +#include <linux/sizes.h> + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-2180" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB2.0 Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_DHCP + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +/* Crystal is 38.4MHz. clk_m runs at half that rate */ +#define COUNTER_FREQUENCY 19200000 + +#endif /* _P2371_2180_H */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 356c941a77..c65d3e5fcb 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -13,7 +13,6 @@ #include "tegra210-common.h" /* High-level configuration options */ -#define V_PROMPT "Tegra210 (P2571) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571" /* Board-specific serial config */ @@ -61,7 +60,6 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define COUNTER_FREQUENCY 38400000 #define CONFIG_OF_BOARD_SETUP #endif /* _P2571_H */ diff --git a/include/configs/palmld.h b/include/configs/palmld.h deleted file mode 100644 index ec48c14aca..0000000000 --- a/include/configs/palmld.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Palm LifeDrive configuration file - * - * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ -#define CONFIG_PALMLD 1 /* Palm LifeDrive board */ - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_MALLOC_LEN (128*1024) -#define CONFIG_SYS_TEXT_BASE 0x0 - -#define CONFIG_BOOTCOMMAND \ - "if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then " \ - "source 0xa0000000; " \ - "else " \ - "bootm 0x0x60000; " \ - "fi; " -#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,9600" -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -#define CONFIG_LZMA /* LZMA compression support */ - -/* - * Serial Console Configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 -#define CONFIG_CONS_INDEX 3 -#define CONFIG_BAUDRATE 9600 - -/* - * Bootloader Components Configuration - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MMC -#define CONFIG_CMD_IDE -#define CONFIG_LCD -#define CONFIG_PXA_LCD - -/* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_DOS_PARTITION -#endif - -/* - * LCD - */ -#ifdef CONFIG_LCD -#define CONFIG_LQ038J7DH53 -#define CONFIG_VIDEO_LOGO -#define CONFIG_CMD_BMP -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) -#endif - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#endif - -/* - * HUSH Shell Configuration - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ - -/* - * DRAM Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) - -/* - * NOR FLASH - */ -#ifdef CONFIG_CMD_FLASH -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00080000 /* 512 KB */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_LEGACY_512Kx16 - -#define CONFIG_SYS_MONITOR_BASE 0 -#define CONFIG_SYS_MONITOR_LEN 0x40000 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 -#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_PROTECTION - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#else -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_NOWHERE -#endif - -#define CONFIG_ENV_ADDR 0x40000 -#define CONFIG_ENV_SIZE 0x4000 - -/* - * IDE - */ -#ifdef CONFIG_CMD_IDE -#define CONFIG_LBA48 -#undef CONFIG_IDE_LED -#undef CONFIG_IDE_RESET - -#define __io - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 - -#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x10 -#define CONFIG_SYS_ATA_REG_OFFSET 0x10 -#define CONFIG_SYS_ATA_ALT_OFFSET 0x10 - -#define CONFIG_SYS_ATA_STRIDE 1 -#endif - -/* - * GPIO settings - */ -#define CONFIG_SYS_GAFR0_L_VAL 0x00000000 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5180012 -#define CONFIG_SYS_GAFR1_L_VAL 0x69988056 -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa580aa -#define CONFIG_SYS_GAFR2_L_VAL 0x6aaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x01040001 -#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c -#define CONFIG_SYS_GAFR3_U_VAL 0x00000009 -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -#define CONFIG_SYS_GPCR3_VAL 0x00000000 -#define CONFIG_SYS_GPDR0_VAL 0xc26b0000 -#define CONFIG_SYS_GPDR1_VAL 0xfcdfaa93 -#define CONFIG_SYS_GPDR2_VAL 0x7bbaffff -#define CONFIG_SYS_GPDR3_VAL 0x006ff38d -#define CONFIG_SYS_GPSR0_VAL 0x0d9e45ee -#define CONFIG_SYS_GPSR1_VAL 0x03affdae -#define CONFIG_SYS_GPSR2_VAL 0x07554000 -#define CONFIG_SYS_GPSR3_VAL 0x01bc0785 - -#define CONFIG_SYS_PSSR_VAL 0x30 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x01ffffff -#define CONFIG_SYS_CCCR 0x02000210 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x7ff844c8 -#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4 -#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8 -#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd -#define CONFIG_SYS_MDREFR_VAL 0x201fa031 -#define CONFIG_SYS_MDMRS_VAL 0x00320032 -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000003 -#define CONFIG_SYS_MCMEM0_VAL 0x0001c391 -#define CONFIG_SYS_MCMEM1_VAL 0x0001c391 -#define CONFIG_SYS_MCATT0_VAL 0x0001c391 -#define CONFIG_SYS_MCATT1_VAL 0x0001c391 -#define CONFIG_SYS_MCIO0_VAL 0x00014611 -#define CONFIG_SYS_MCIO1_VAL 0x0001c391 - -#endif /* __CONFIG_H */ diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h deleted file mode 100644 index 81c3f028ff..0000000000 --- a/include/configs/palmtc.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Palm Tungsten|C configuration file - * - * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/pxa-regs.h> - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA25X 1 /* Intel PXA255 CPU */ -#define CONFIG_PALMTC 1 /* Palm Tungsten|C board */ - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_MALLOC_LEN (128*1024) -#define CONFIG_SYS_TEXT_BASE 0x0 - -#define CONFIG_BOOTCOMMAND \ - "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \ - "source 0xa0000000; " \ - "else " \ - "bootm 0x80000; " \ - "fi; " -#define CONFIG_BOOTARGS \ - "console=tty0 console=ttyS0,115200" -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -#define CONFIG_LZMA /* LZMA compression support */ - -/* - * Serial Console Configuration - * STUART - the lower serial port on Colibri board - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 -#define CONFIG_CONS_INDEX 3 -#define CONFIG_BAUDRATE 115200 - -/* - * Bootloader Components Configuration - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MMC -#define CONFIG_LCD -#define CONFIG_PXA_LCD - -/* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_DOS_PARTITION -#endif - -/* - * LCD - */ -#ifdef CONFIG_LCD -#define CONFIG_ACX517AKN -#define CONFIG_VIDEO_LOGO -#define CONFIG_CMD_BMP -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) -#endif - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#endif - -/* - * HUSH Shell Configuration - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */ - -/* - * DRAM Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 - -/* - * NOR FLASH - */ -#ifdef CONFIG_CMD_FLASH -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 64 - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 -#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_PROTECTION - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#else -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_NOWHERE -#endif - -#define CONFIG_SYS_MONITOR_BASE 0x0 -#define CONFIG_SYS_MONITOR_LEN 0x40000 - -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_ADDR 0x40000 - -/* - * GPIO settings - */ -#define CONFIG_SYS_GAFR0_L_VAL 0x00011004 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5000008 -#define CONFIG_SYS_GAFR1_L_VAL 0x60888050 -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50aaa -#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x00000000 -#define CONFIG_SYS_GPCR0_VAL 0x0 -#define CONFIG_SYS_GPCR1_VAL 0x0 -#define CONFIG_SYS_GPCR2_VAL 0x0 -#define CONFIG_SYS_GPDR0_VAL 0xcfff8140 -#define CONFIG_SYS_GPDR1_VAL 0xfcbfbef3 -#define CONFIG_SYS_GPDR2_VAL 0x0001ffff -#define CONFIG_SYS_GPSR0_VAL 0x00010f8f -#define CONFIG_SYS_GPSR1_VAL 0x00bf5de5 -#define CONFIG_SYS_GPSR2_VAL 0x03fe0800 - -#define CONFIG_SYS_PSSR_VAL PSSR_RDH - -/* Clock setup: - * CKEN[1] - PWM1 ; CKEN[6] - FFUART - * CKEN[12] - MMC ; CKEN[16] - LCD - */ -#define CONFIG_SYS_CKEN 0x00011042 -#define CONFIG_SYS_CCCR 0x00000161 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x800092c2 -#define CONFIG_SYS_MSC1_VAL 0x80008000 -#define CONFIG_SYS_MSC2_VAL 0x80008000 -#define CONFIG_SYS_MDCNFG_VAL 0x00001ac9 -#define CONFIG_SYS_MDREFR_VAL 0x00118018 -#define CONFIG_SYS_MDMRS_VAL 0x00220032 -#define CONFIG_SYS_FLYCNFG_VAL 0x01fe01fe -#define CONFIG_SYS_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00010504 -#define CONFIG_SYS_MCMEM1_VAL 0x00010504 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00010504 -#define CONFIG_SYS_MCIO0_VAL 0x00010e04 -#define CONFIG_SYS_MCIO1_VAL 0x00010e04 - -#endif /* __CONFIG_H */ diff --git a/include/configs/palmtreo680.h b/include/configs/palmtreo680.h deleted file mode 100644 index 5ffed82955..0000000000 --- a/include/configs/palmtreo680.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Palm Treo 680 configuration file - * - * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com> - * - * This file is released under the terms of GPL v2 and any later version. - * See the file COPYING in the root directory of the source tree for details. - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X -#define CONFIG_PALMTREO680 -#define CONFIG_MACH_TYPE MACH_TYPE_TREO680 - -#define CONFIG_SYS_MALLOC_LEN (4096*1024) - -#define CONFIG_LZMA - -/* - * Serial Console Configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_CONS_INDEX 3 - -/* we have nand (although technically nand *is* flash...) */ -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_LCD -/* #define CONFIG_KEYBOARD */ /* TODO */ - -/* - * Bootloader Components Configuration - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MMC -#define CONFIG_CMD_NAND - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -/* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC - -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_DOS_PARTITION -#endif - -/* - * LCD - */ -#ifdef CONFIG_LCD -#define CONFIG_PXA_LCD -#define CONFIG_ACX544AKN -#define CONFIG_LCD_LOGO -#define LCD_BPP LCD_COLOR16 -#define CONFIG_FB_ADDR 0x5c000000 /* internal SRAM */ -#define CONFIG_CMD_BMP -#define CONFIG_SPLASH_SCREEN /* requires "splashimage" env var */ -#define CONFIG_SPLASH_SCREEN_ALIGN /* requires "splashpos" env var */ -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) - -#endif - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#endif - -/* - * HUSH Shell Configuration - */ -#define CONFIG_SYS_HUSH_PARSER 1 -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#define CONFIG_SYS_LONGHELP -#undef CONFIG_SYS_PROMPT -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " -#else -#endif -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ - -/* - * Stack sizes - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * DRAM Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* - * GPIO settings - */ -#define CONFIG_SYS_GAFR0_L_VAL 0x0E000000 -#define CONFIG_SYS_GAFR0_U_VAL 0xA500001A -#define CONFIG_SYS_GAFR1_L_VAL 0x60000002 -#define CONFIG_SYS_GAFR1_U_VAL 0xAAA07959 -#define CONFIG_SYS_GAFR2_L_VAL 0x02AAAAAA -#define CONFIG_SYS_GAFR2_U_VAL 0x41440F08 -#define CONFIG_SYS_GAFR3_L_VAL 0x56AA95FF -#define CONFIG_SYS_GAFR3_U_VAL 0x00001401 -#define CONFIG_SYS_GPCR0_VAL 0x1FF80400 -#define CONFIG_SYS_GPCR1_VAL 0x03003FC1 -#define CONFIG_SYS_GPCR2_VAL 0x01C1E000 -#define CONFIG_SYS_GPCR3_VAL 0x01C1E000 -#define CONFIG_SYS_GPDR0_VAL 0xCFF90400 -#define CONFIG_SYS_GPDR1_VAL 0xFB22BFC1 -#define CONFIG_SYS_GPDR2_VAL 0x93CDFFDF -#define CONFIG_SYS_GPDR3_VAL 0x0069FF81 -#define CONFIG_SYS_GPSR0_VAL 0x02000018 -#define CONFIG_SYS_GPSR1_VAL 0x00000000 -#define CONFIG_SYS_GPSR2_VAL 0x000C0000 -#define CONFIG_SYS_GPSR3_VAL 0x00080000 - -#define CONFIG_SYS_PSSR_VAL 0x30 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x01ffffff -#define CONFIG_SYS_CCCR 0x02000210 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x7ff844c8 -#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4 -#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8 -#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd -#define CONFIG_SYS_MDREFR_VAL 0x201fa031 -#define CONFIG_SYS_MDMRS_VAL 0x00320032 -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 -#define CONFIG_SYS_MECR_VAL 0x00000003 -#define CONFIG_SYS_MCMEM0_VAL 0x0001c391 -#define CONFIG_SYS_MCMEM1_VAL 0x0001c391 -#define CONFIG_SYS_MCATT0_VAL 0x0001c391 -#define CONFIG_SYS_MCATT1_VAL 0x0001c391 -#define CONFIG_SYS_MCIO0_VAL 0x00014611 -#define CONFIG_SYS_MCIO1_VAL 0x0001c391 - -/* - * USB - */ -#define CONFIG_USB_DEVICE -#define CONFIG_USB_TTY -#define CONFIG_USB_DEV_PULLUP_GPIO 114 - -/* - * SPL - */ -#define CONFIG_SPL_TEXT_BASE 0xa1700000 /* IPL loads SPL here */ -#define CONFIG_SPL_STACK 0x5c040000 /* end of internal SRAM */ -#define CONFIG_SPL_NAND_SUPPORT /* build libnand for spl */ -#define CONFIG_SPL_NAND_DOCG4 /* use lean docg4 nand spl driver */ -#define CONFIG_SPL_LIBGENERIC_SUPPORT /* spl uses memcpy */ - -/* - * NAND - */ -#define CONFIG_NAND_DOCG4 -#define CONFIG_SYS_NAND_SELF_INIT -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* only one device */ -#define CONFIG_SYS_NAND_BASE 0x00000000 /* mapped to reset vector */ -#define CONFIG_SYS_NAND_PAGE_SIZE 0x200 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 -#define CONFIG_BITREVERSE /* needed by docg4 driver */ -#define CONFIG_BCH /* needed by docg4 driver */ - -/* - * IMPORTANT NOTE: this is the size of the concatenated spl + u-boot image. It - * will be rounded up to the next 64k boundary (the spl flash block size), so it - * does not have to be exact, but you must ensure that it is not less than the - * actual image size, or it may fail to boot (bricked phone)! - * (Tip: reduces to three blocks with lcd and mmc support removed from u-boot.) -*/ -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 /* four 64k flash blocks */ - -/* - * This is the byte offset into the flash at which the concatenated spl + u-boot - * image is placed. It must be at the start of a block (256k boundary). Blocks - * 0 - 5 are write-protected, so we start at block 6. - */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x180000 /* block 6 */ - -/* DRAM address to which u-boot proper is loaded (before it relocates itself) */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0xa0000000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST - -/* passed to linker by Makefile as arg to -Ttext option */ -#define CONFIG_SYS_TEXT_BASE 0xa0000000 - -#define CONFIG_SYS_INIT_SP_ADDR 0x5c040000 /* end of internal SRAM */ - -/* - * environment - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_BUILD_ENVCRC -#define CONFIG_ENV_SIZE 0x200 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_EXTRA_ENV_SETTINGS \ - "stdin=usbtty\0" \ - "stdout=usbtty\0" \ - "stderr=usbtty" -#define CONFIG_BOOTARGS "mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part) \ -ip=192.168.11.102:::255.255.255.0:treo:usb0" -#define CONFIG_BOOTDELAY 3 - -#if 0 /* example: try 2nd mmc partition, then nand */ -#define CONFIG_BOOTCOMMAND \ - "mmc rescan; " \ - "if mmcinfo && ext2load mmc 0:2 0xa1000000 uImage; then " \ - "bootm 0xa1000000; " \ - "elif nand read 0xa1000000 0x280000 0x240000; then " \ - "bootm 0xa1000000; " \ - "fi; " -#endif - -/* u-boot lives at end of SDRAM, so use start of SDRAM for stand alone apps */ -#define CONFIG_STANDALONE_LOAD_ADDR 0xa0000000 - -#define CONFIG_SYS_DCACHE_OFF -#define CONFIG_SYS_ICACHE_OFF - -#endif /* __CONFIG_H */ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h new file mode 100644 index 0000000000..150698ecaa --- /dev/null +++ b/include/configs/pcm052.h @@ -0,0 +1,281 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for the phytec PCM-052 SoM. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> + +#define CONFIG_VF610 + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_THUMB_BUILD + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* Enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_FSL_LPUART +#define LPUART_BASE UART1_BASE + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_UART_PORT (1) +#define CONFIG_BAUDRATE 115200 + +#undef CONFIG_CMD_IMLS + +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#ifdef CONFIG_CMD_NAND +#define CONFIG_USE_ARCH_MEMCPY +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR + +#define CONFIG_JFFS2_NAND + +/* UBI */ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* Dynamic MTD partition support */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define MTDIDS_DEFAULT "nand0=NAND" +#define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\ + ",384k(bootloader)"\ + ",128k(env1)"\ + ",128k(env2)"\ + ",128k(dtb)"\ + ",6144k(kernel)"\ + ",65536k(ramdisk)"\ + ",450944k(root)" +#endif + +#define CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + +/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/ +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL + +/* QSPI Configs*/ +#define CONFIG_FSL_QSPI + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SYS_FSL_QSPI_LE +#endif + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C3 +#define CONFIG_SYS_I2C_MXC + +/* RTC (actually an RV-4162 but M41T62-compatible) */ +#define CONFIG_CMD_DATE +#define CONFIG_RTC_M41T62 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_RTC_BUS_NUM 2 + +/* EEPROM (24FC256) */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_BUS 2 + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x82000000 + +/* We boot from the gfxRAM area of the OCRAM. */ +#define CONFIG_SYS_TEXT_BASE 0x3f408000 +#define CONFIG_BOARD_SIZE_LIMIT 524288 + +#define CONFIG_BOOTCOMMAND "run bootcmd_sd" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "blimg_file=u-boot.imx\0" \ + "blsec_addr=0x81000000\0" \ + "blimg_addr=0x81000400\0" \ + "kernel_file=zImage\0" \ + "kernel_addr=0x82000000\0" \ + "fdt_file=vf610-pcm052.dtb\0" \ + "fdt_addr=0x81000000\0" \ + "ram_file=uRamdisk\0" \ + "ram_addr=0x83000000\0" \ + "filesys=rootfs.ubifs\0" \ + "sys_addr=0x81000000\0" \ + "tftploc=/path/to/tftp/directory/\0" \ + "nfs_root=/path/to/nfs/root\0" \ + "tftptimeout=1000\0" \ + "tftptimeoutcountmax=1000000\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "bootargs_base=setenv bootargs rw mem=256M " \ + "console=ttyLP1,115200n8\0" \ + "bootargs_sd=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \ + "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \ + "bootargs_nand=setenv bootargs ${bootargs} " \ + "ubi.mtd=6 rootfstype=ubifs root=ubi0:rootfs\0" \ + "bootargs_ram=setenv bootargs ${bootargs} " \ + "root=/dev/ram rw initrd=${ram_addr}\0" \ + "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \ + "fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \ + "fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \ + "bootz ${kernel_addr} - ${fdt_addr}\0" \ + "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \ + "tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \ + "tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \ + "bootz ${kernel_addr} - ${fdt_addr}\0" \ + "bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \ + "nand read ${fdt_addr} dtb; " \ + "nand read ${kernel_addr} kernel; " \ + "bootz ${kernel_addr} - ${fdt_addr}\0" \ + "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \ + "nand read ${fdt_addr} dtb; " \ + "nand read ${kernel_addr} kernel; " \ + "nand read ${ram_addr} ramdisk; " \ + "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ + "update_bootloader_from_tftp=mtdparts default; " \ + "nand read ${blsec_addr} bootloader; " \ + "mw.b ${blimg_addr} 0xff 0x5FC00; " \ + "if tftp ${blimg_addr} ${tftpdir}${blimg_file}; then " \ + "nand erase.part bootloader; " \ + "nand write ${blsec_addr} bootloader ${filesize}; fi\0" \ + "update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \ + "${kernel_file}; " \ + "then mtdparts default; " \ + "nand erase.part kernel; " \ + "nand write ${kernel_addr} kernel ${filesize}; " \ + "if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \ + "nand erase.part dtb; " \ + "nand write ${fdt_addr} dtb ${filesize}; fi\0" \ + "update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \ + "then setenv fdtsize ${filesize}; " \ + "if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \ + "mtdparts default; " \ + "nand erase.part dtb; " \ + "nand write ${fdt_addr} dtb ${fdtsize}; " \ + "nand erase.part kernel; " \ + "nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \ + "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \ + "then mtdparts default; " \ + "nand erase.part root; " \ + "ubi part root; " \ + "ubi create rootfs; " \ + "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \ + "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ + "then mtdparts default; " \ + "nand erase.part ramdisk; " \ + "nand write ${ram_addr} ramdisk ${filesize}; fi\0" + +/* miscellaneous commands */ +#define CONFIG_CMD_ELF + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80010000 +#define CONFIG_SYS_MEMTEST_END 0x87C00000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* Physical memory map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM (0x80000000) +#define PHYS_SDRAM_SIZE (256 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_OFFSET (12 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET 0xA0000 +#define CONFIG_ENV_SIZE_REDUND (8 * 1024) +#define CONFIG_ENV_OFFSET_REDUND 0xC0000 +#endif + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#endif diff --git a/include/configs/platinum.h b/include/configs/platinum.h index d65143240b..bb7e845183 100644 --- a/include/configs/platinum.h +++ b/include/configs/platinum.h @@ -45,6 +45,8 @@ /* I2C config */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h deleted file mode 100644 index 332d79f89f..0000000000 --- a/include/configs/pxa255_idp.h +++ /dev/null @@ -1,335 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * Copied from lubbock.h - * - * (C) Copyright 2004 - * BEC Systems <http://bec-systems.com> - * Cliff Brake <cliff.brake@gmail.com> - * Configuation settings for the Accelent/Vibren PXA255 IDP - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/pxa-regs.h> - -/* - * If we are developing, we might want to start U-Boot from RAM - * so we MUST NOT initialize critical regs like mem-timing ... - */ -#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */ -#define CONFIG_SYS_TEXT_BASE 0x0 - -/* - * define the following to enable debug blinks. A debug blink function - * must be defined in memsetup.S - */ -#undef DEBUG_BLINK_ENABLE -#undef DEBUG_BLINKC_ENABLE - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */ - -#undef CONFIG_LCD -#ifdef CONFIG_LCD -#define CONFIG_PXA_LCD -#define CONFIG_SHARP_LM8V31 -#endif - -#define CONFIG_MMC 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_BOARD_LATE_INIT - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * PXA250 IDP memory map information - */ - -#define IDP_CS5_ETH_OFFSET 0x03400000 - - -/* - * Hardware drivers - */ -#define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300) -#define CONFIG_SMC_USE_32_BIT 1 -/* #define CONFIG_SMC_USE_IOFUNCS */ - -/* the following has to be set high -- suspect something is wrong with - * with the tftp timeout routines. FIXME!!! - */ -#define CONFIG_NET_RETRY_COUNT 100 - -/* - * select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ -#define CONFIG_CONS_INDEX 3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_FAT -#define CONFIG_CMD_DHCP - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTCOMMAND "bootm 40000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -/* #define CONFIG_INITRD_TAG 1 */ - -/* - * Current memory map for Vibren supplied Linux images: - * - * Flash: - * 0 - 0x3ffff (size = 0x40000): bootloader - * 0x40000 - 0x13ffff (size = 0x100000): kernel - * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs - * - * RAM: - * 0xa0008000 - kernel is loaded - * 0xa3000000 - Uboot runs (48MB into RAM) - * - */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "prog_boot_mmc=" \ - "mw.b 0xa0000000 0xff 0x40000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0000000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x3ffff; " \ - "erase 0x0 0x3ffff; " \ - "cp.b 0xa0000000 0x0 0x40000; " \ - "reset;" \ - "fi\0" \ - "prog_uzImage_mmc=" \ - "mw.b 0xa0000000 0xff 0x100000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0000000 uzImage; " \ - "then " \ - "protect off 0x40000 0xfffff; " \ - "erase 0x40000 0xfffff; " \ - "cp.b 0xa0000000 0x40000 0x100000; " \ - "fi\0" \ - "prog_jffs_mmc=" \ - "mw.b 0xa0000000 0xff 0x1e00000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0000000 root.jffs; " \ - "then " \ - "protect off 0x140000 0x1f3ffff; " \ - "erase 0x140000 0x1f3ffff; " \ - "cp.b 0xa0000000 0x140000 0x1e00000; " \ - "fi\0" \ - "boot_mmc=" \ - "if mmcinit && " \ - "fatload mmc 0 0xa1000000 uzImage && " \ - "then " \ - "bootm 0xa1000000; " \ - "fi\0" \ - "prog_boot_net=" \ - "mw.b 0xa0000000 0xff 0x100000; " \ - "if bootp 0xa0000000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x3ffff; " \ - "erase 0x0 0x3ffff; " \ - "cp.b 0xa0000000 0x0 0x40000; " \ - "reset; " \ - "fi\0" \ - "prog_uzImage_net=" \ - "mw.b 0xa0000000 0xff 0x100000; " \ - "if bootp 0xa0000000 uzImage; " \ - "then " \ - "protect off 0x40000 0xfffff; " \ - "erase 0x40000 0xfffff; " \ - "cp.b 0xa0000000 0x40000 0x100000; " \ - "fi\0" \ - "prog_jffs_net=" \ - "mw.b 0xa0000000 0xff 0x1e00000; " \ - "if bootp 0xa0000000 root.jffs; " \ - "then " \ - "protect off 0x140000 0x1f3ffff; " \ - "erase 0x140000 0x1f3ffff; " \ - "cp.b 0xa0000000 0x140000 0x1e00000; " \ - "fi\0" - - -/* "erase_env=" */ -/* "protect off" */ - - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#undef CONFIG_SYS_PROMPT -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ -#else -#endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */ - -#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ - -#define RTC 1 /* enable 32KHz osc */ - -#ifdef CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x04000000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 - -/* - * GPIO settings - */ - -#define CONFIG_SYS_GAFR0_L_VAL 0x80001005 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012 -#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558 -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a -#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x2 -#define CONFIG_SYS_GPCR0_VAL 0x1800400 -#define CONFIG_SYS_GPCR1_VAL 0x0 -#define CONFIG_SYS_GPCR2_VAL 0x0 -#define CONFIG_SYS_GPDR0_VAL 0xc1818440 -#define CONFIG_SYS_GPDR1_VAL 0xfcffab82 -#define CONFIG_SYS_GPDR2_VAL 0x1ffff -#define CONFIG_SYS_GPSR0_VAL 0x8000 -#define CONFIG_SYS_GPSR1_VAL 0x3f0002 -#define CONFIG_SYS_GPSR2_VAL 0x1c000 - -#define CONFIG_SYS_PSSR_VAL 0x20 - -#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 -#define CONFIG_SYS_CKEN 0x0 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x29DCA4D2 -#define CONFIG_SYS_MSC1_VAL 0x43AC494C -#define CONFIG_SYS_MSC2_VAL 0x39D449D4 -#define CONFIG_SYS_MDCNFG_VAL 0x090009C9 -#define CONFIG_SYS_MDREFR_VAL 0x0085C017 -#define CONFIG_SYS_MDMRS_VAL 0x00220022 -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000003 -#define CONFIG_SYS_MCMEM0_VAL 0x00014405 -#define CONFIG_SYS_MCMEM1_VAL 0x00014405 -#define CONFIG_SYS_MCATT0_VAL 0x00014405 -#define CONFIG_SYS_MCATT1_VAL 0x00014405 -#define CONFIG_SYS_MCIO0_VAL 0x00014405 -#define CONFIG_SYS_MCIO1_VAL 0x00014405 - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define CONFIG_SYS_MONITOR_BASE 0 -#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* put cfg at end of flash for now */ -#define CONFIG_ENV_IS_IN_FLASH 1 - /* Addr of Environment Sector */ -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000) -#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16) - -#endif /* __CONFIG_H */ diff --git a/include/configs/qong.h b/include/configs/qong.h deleted file mode 100644 index f34a54f754..0000000000 --- a/include/configs/qong.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com> - * - * Configuration settings for the Dave/DENX QongEVB-LITE board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - -/* High Level Configuration Options */ -#define CONFIG_MX31 /* This is a mx31 */ -#define CONFIG_QONG - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_SYS_TEXT_BASE 0xa0000000 - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1536 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -#define CONFIG_MXC_GPIO -#define CONFIG_HW_WATCHDOG -#define CONFIG_IMX_WATCHDOG - -#define CONFIG_MXC_SPI -#define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_RTC_MC13XXX - -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL -#define CONFIG_FSL_PMIC_BUS 1 -#define CONFIG_FSL_PMIC_CS 0 -#define CONFIG_FSL_PMIC_CLK 100000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 - -/* FPGA */ -#define CONFIG_FPGA -#define CONFIG_QONG_FPGA -#define CONFIG_FPGA_BASE (CS1_BASE) -#define CONFIG_FPGA_LATTICE -#define CONFIG_FPGA_COUNT 1 - -#ifdef CONFIG_QONG_FPGA -/* Ethernet */ -#define CONFIG_DNET -#define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE) - -/* Framebuffer and LCD */ -#define CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_MX3 -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SPLASH_SCREEN -#define CONFIG_CMD_BMP -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) - -/* USB */ -#define CONFIG_CMD_USB -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_MXC -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORT 2 -#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT) -#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_SUPPORT_VFAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#endif /* CONFIG_CMD_USB */ - -/* - * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the - * initial TFTP transfer, should the user wish one, significantly. - */ -#define CONFIG_ARP_TIMEOUT 200UL - -#endif /* CONFIG_QONG_FPGA */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/*********************************************************** - * Command definition - ***********************************************************/ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING -#define CONFIG_CMD_SPI -#define CONFIG_CMD_UNZIP - -#define CONFIG_BOARD_LATE_INIT - -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "uboot_addr=A0000000\0" \ - "kernel_addr=A00C0000\0" \ - "ramdisk_addr=A0300000\0" \ - "u-boot=qong/u-boot.bin\0" \ - "kernel_addr_r=80800000\0" \ - "hostname=qong\0" \ - "bootfile=qong/uImage\0" \ - "rootpath=/opt/eldk-4.2-arm/armVFP\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm\0" \ - "bootcmd=run flash_self\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \ - "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \ - "vmode:0\0" \ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* memtest works on first 255MB of RAM */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ - -#define CONFIG_MISC_INIT_R - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD0_BASE -#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ - -/* - * NAND driver - */ - -#ifndef __ASSEMBLY__ -extern void qong_nand_plat_init(void *chip); -extern int qong_nand_rdy(void *chip); -#endif -#define CONFIG_NAND_PLAT -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CS3_BASE -#define NAND_PLAT_INIT() qong_nand_plat_init(nand) - -#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24)) -#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23)) -#define QONG_NAND_WRITE(addr, cmd) \ - do { \ - __REG8(addr) = cmd; \ - } while (0) - -#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd) -#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip)) - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 -/* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000) - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -/* Flash memory is CFI compliant */ -#define CONFIG_SYS_FLASH_CFI -/* Use drivers/cfi_flash.c */ -#define CONFIG_FLASH_CFI_DRIVER -/* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -/* Use hardware sector protection */ -#define CONFIG_SYS_FLASH_PROTECTION - -/* - * Filesystem - */ -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#define CONFIG_RBTREE -#define CONFIG_MTD_PARTITIONS -#define CONFIG_CMD_MTDPARTS -#define CONFIG_LZO -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \ - "nand0=gen_nand" -#define MTDPARTS_DEFAULT \ - "mtdparts=physmap-flash.0:" \ - "512k(U-Boot),128k(env1),128k(env2)," \ - "2304k(kernel),13m(ramdisk),-(user);" \ - "gen_nand:" \ - "128m(nand)" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) - -#define CONFIG_BOARD_EARLY_INIT_F - -#endif /* __CONFIG_H */ diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h deleted file mode 100644 index a0120b06fd..0000000000 --- a/include/configs/rd6281a.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_RD6281A_H -#define _CONFIG_RD6281A_H - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nMarvell-RD6281A" - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_MACH_RD6281A /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FAT -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB -#define CONFIG_CMD_IDE - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ -#endif -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -#define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x40000 -#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "${x_bootcmd_usb}; bootm 0x6400000;" - -#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \ - "3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0" - -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ -#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE -#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */ -#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */ -#define CONFIG_PHY_BASE_ADR 0x0A -#define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */ -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - -#endif /* _CONFIG_RD6281A_H */ diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h deleted file mode 100644 index d4ffb467bd..0000000000 --- a/include/configs/scb9328.h +++ /dev/null @@ -1,312 +0,0 @@ -/* - * Copyright (C) 2003 ETC s.r.o. - * - * SPDX-License-Identifier: GPL-2.0+ - * Written by Peter Figuli <peposh@etc.sk>, 2003. - * - * 2003/13/06 Initial MP10 Support copied from wepep250 - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IMX 1 /* This is a Motorola MC9328MXL Chip */ -#define CONFIG_SCB9328 1 /* on a scb9328tronix board */ - -#define CONFIG_IMX_SERIAL -#define CONFIG_IMX_SERIAL1 -/* - * Select serial console configuration - */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - -/* - * Boot options. Setting delay to -1 stops autostart count down. - * NOTE: Sending parameters to kernel depends on kernel version and - * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept - * parameters at all! Do not get confused by them so. - */ -#define CONFIG_BOOTDELAY -1 -#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328" -#define CONFIG_BOOTCOMMAND "bootm 10040000" -#define CONFIG_SHOW_BOOT_PROGRESS -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.10.10.9 -#define CONFIG_SERVERIP 10.10.10.10 - -/* - * General options for u-boot. Modify to save memory foot print - */ -#define CONFIG_SYS_LONGHELP /* undef saves memory */ -#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */ -#define CONFIG_SYS_MAXARGS 16 /* max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */ - -#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ -#define CONFIG_SYS_MEMTEST_END 0x08F00000 - -#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ - -#define CONFIG_BAUDRATE 115200 -/* - * Definitions related to passing arguments to kernel. - */ -#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ -#define CONFIG_INITRD_TAG 1 /* send initrd params */ - -/* - * Malloc pool need to host env + 128 Kb reserve for other allocations. - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) ) - -/* SDRAM Setup Values -0x910a8300 Precharge Command CAS 3 -0x910a8200 Precharge Command CAS 2 - -0xa10a8300 AutoRefresh Command CAS 3 -0xa10a8200 Set AutoRefresh Command CAS 2 */ - -#define PRECHARGE_CMD 0x910a8200 -#define AUTOREFRESH_CMD 0xa10a8200 - -/* - * SDRAM Memory Map - */ -/* SH FIXME */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ -#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */ -#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */ - -#define CONFIG_SYS_TEXT_BASE 0x10000000 - -#define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000) - -/* - * Configuration for FLASH memory for the Synertronixx board - */ - -/* #define SCB9328_FLASH_32M */ - -/* 32MB */ -#ifdef SCB9328_FLASH_32M -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ -#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ -#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ -#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */ -#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ -#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ -#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ -#else - -/* 16MB */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ -#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ -#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ -#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */ -#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ -#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ -#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ -#endif /* SCB9328_FLASH_32M */ - -/* This should be defined if CFI FLASH device is present. Actually benefit - is not so clear to me. In other words we can provide more informations - to user, but this expects more complex flash handling we do not provide - now.*/ -#undef CONFIG_SYS_FLASH_CFI - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* timeout for Erase operation */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 /* timeout for Write operation */ - -#define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE - -/* - * This is setting for JFFS2 support in u-boot. - * Right now there is no gain for user, but later on booting kernel might be - * possible. Consider using XIP kernel running from flash to save RAM - * footprint. - * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. - */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 5 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -/* - * Environment setup. Definitions of monitor location and size with - * definition of environment setup ends up in 2 possibilities. - * 1. Embeded environment - in u-boot code is space for environment - * 2. Environment is read from predefined sector of flash - * Right now we support 2. possiblity, but expecting no env placed - * on mentioned address right now. This also needs to provide whole - * sector for it - for us 256Kb is really waste of memory. U-boot uses - * default env. and until kernel parameters could be sent to kernel - * env. has no sense to us. - */ - -/* Setup for PA23 which is Reset Default PA23 but has to become - CS5 */ - -#define CONFIG_SYS_GPR_A_VAL 0x00800000 -#define CONFIG_SYS_GIUS_A_VAL 0x0043fffe - -#define CONFIG_SYS_MONITOR_BASE 0x10000000 -#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */ -#define CONFIG_ENV_SIZE 0x20000 - -#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ - -/* - * CSxU_VAL: - * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 - * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | - * - * CSxL_VAL: - * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 - * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| - */ - -#define CONFIG_SYS_CS0U_VAL 0x000F2000 -#define CONFIG_SYS_CS0L_VAL 0x11110d01 -#define CONFIG_SYS_CS1U_VAL 0x000F0a00 -#define CONFIG_SYS_CS1L_VAL 0x11110601 -#define CONFIG_SYS_CS2U_VAL 0x0 -#define CONFIG_SYS_CS2L_VAL 0x0 - -#define CONFIG_SYS_CS3U_VAL 0x000FFFFF -#define CONFIG_SYS_CS3L_VAL 0x00000303 - -#define CONFIG_SYS_CS4U_VAL 0x000F0a00 -#define CONFIG_SYS_CS4L_VAL 0x11110301 - -/* CNC == 3 too long - #define CONFIG_SYS_CS5U_VAL 0x0000C210 */ - -/* #define CONFIG_SYS_CS5U_VAL 0x00008400 - mal laenger mahcen, ob der bei 150MHz laenger haelt dann und - kaum langsamer ist */ -/* #define CONFIG_SYS_CS5U_VAL 0x00009400 - #define CONFIG_SYS_CS5L_VAL 0x11010D03 */ - -#define CONFIG_SYS_CS5U_VAL 0x00008400 -#define CONFIG_SYS_CS5L_VAL 0x00000D03 - -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x16000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE+4) - -/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) - f_ref=16,777MHz - - 0x002a141f: 191,9944MHz - 0x040b2007: 144MHz - 0x042a141f: 96MHz - 0x0811140d: 64MHz - 0x040e200e: 150MHz - 0x00321431: 200MHz - - 0x08001800: 64MHz mit 16er Quarz - 0x04001800: 96MHz mit 16er Quarz - 0x04002400: 144MHz mit 16er Quarz - - 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 - |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ - -#define CPU200 - -#ifdef CPU200 -#define CONFIG_SYS_MPCTL0_VAL 0x00321431 -#else -#define CONFIG_SYS_MPCTL0_VAL 0x040e200e -#endif - -/* #define BUS64 */ -#define BUS72 - -#ifdef BUS72 -#define CONFIG_SYS_SPCTL0_VAL 0x04002400 -#endif - -#ifdef BUS96 -#define CONFIG_SYS_SPCTL0_VAL 0x04001800 -#endif - -#ifdef BUS64 -#define CONFIG_SYS_SPCTL0_VAL 0x08001800 -#endif - -/* Das ist der BCLK Divider, der aus der System PLL - BCLK und HCLK erzeugt: - 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0 - 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2 - 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2 - 0x2f001003 : 192MHz/5=38,4MHz - 0x2f000003 : 64MHz/1 - Bit 22: SPLL Restart - Bit 21: MPLL Restart */ - -#ifdef BUS64 -#define CONFIG_SYS_CSCR_VAL 0x2f030003 -#endif - -#ifdef BUS72 -#define CONFIG_SYS_CSCR_VAL 0x2f030403 -#endif - -/* - * Well this has to be defined, but on the other hand it is used differently - * one may expect. For instance loadb command do not cares :-) - * So advice is - do not relay on this... - */ -#define CONFIG_SYS_LOAD_ADDR 0x08400000 - -#define MHZ16QUARZINUSE - -#ifdef MHZ16QUARZINUSE -#define CONFIG_SYSPLL_CLK_FREQ 16000000 -#else -#define CONFIG_SYSPLL_CLK_FREQ 16780000 -#endif - -#define CONFIG_SYS_CLK_FREQ 16780000 - -/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */ -#define CONFIG_SYS_FMCR_VAL 0x00000001 - -/* Bit[0:3] contain PERCLK1DIV for UART 1 - 0x000b00b ->b<- -> 192MHz/12=16MHz - 0x000b00b ->8<- -> 144MHz/09=16MHz - 0x000b00b ->3<- -> 64MHz/4=16MHz */ - -#ifdef BUS96 -#define CONFIG_SYS_PCDR_VAL 0x000b00b5 -#endif - -#ifdef BUS64 -#define CONFIG_SYS_PCDR_VAL 0x000b00b3 -#endif - -#ifdef BUS72 -#define CONFIG_SYS_PCDR_VAL 0x000b00b8 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index d189c3fde9..e11c016aed 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -117,6 +117,9 @@ * */ #define CONFIG_MACB +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 #define CONFIG_RMII /* use reduced MII inteface */ #define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */ #define CONFIG_AT91_WANTS_COMMON_PHY @@ -182,6 +185,7 @@ /* General Boot Parameter */ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND "run flashboot" +#define CONFIG_BOOT_RETRY_TIME 30 #define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE \ diff --git a/include/configs/snowball.h b/include/configs/snowball.h deleted file mode 100644 index de03e76ba1..0000000000 --- a/include/configs/snowball.h +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * #define DEBUG 1 - */ - -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SNOWBALL -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_BOARD_LATE_INIT - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_U8500 - -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF - -/*----------------------------------------------------------------------- - * Size of environment and malloc() pool - */ -/* - * If you use U-Boot as crash kernel, make sure that it does not overwrite - * information saved by kexec during panic. Kexec expects the start - * address of the executable 32K above "crashkernel" address. - */ -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (8*1024) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) - -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_CMD_ENV -#define CONFIG_ENV_OFFSET 0x0118000 -#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */ - -/* - * PL011 Configuration - */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_SERIAL_RLCR -#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT - -/* - * U8500 UART registers base for 3 serial devices - */ -#define CFG_UART0_BASE 0x80120000 -#define CFG_UART1_BASE 0x80121000 -#define CFG_UART2_BASE 0x80007000 -#define CFG_SERIAL0 CFG_UART0_BASE -#define CFG_SERIAL1 CFG_UART1_BASE -#define CFG_SERIAL2 CFG_UART2_BASE -#define CONFIG_PL011_CLOCK 38400000 -#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \ - (void *)CFG_SERIAL2 } -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* - * Devices and file systems - */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_DOS_PARTITION - -/* - * Commands - */ -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 - -#ifndef CONFIG_BOOTDELAY -#define CONFIG_BOOTDELAY 1 -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ -"mmc dev 1; " \ - "if run loadbootscript; " \ - "then run bootscript; " \ - "else " \ - "if run mmcload; " \ - "then run mmcboot; " \ - "else " \ - "mmc dev 0; " \ - "if run emmcloadbootscript; " \ - "then run bootscript; " \ - "else " \ - "if run emmcload; " \ - "then run emmcboot; " \ - "else " \ - "echo No media to boot from; " \ - "fi; " \ - "fi; " \ - "fi; " \ - "fi; " - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr=0x00100000\0" \ - "console=ttyAMA2,115200n8\0" \ - "loadbootscript=fatload mmc 1:1 ${loadaddr} boot.scr\0" \ - "emmcloadbootscript=fatload mmc 0:2 ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript " \ - "from mmc ...; source ${loadaddr}\0" \ - "memargs256=mem=96M@0 mem_modem=32M@96M mem=32M@128M " \ - "hwmem=22M@160M pmem_hwb=42M@182M mem_mali=32@224M\0" \ - "memargs512=mem=96M@0 mem_modem=32M@96M hwmem=32M@128M " \ - "mem=64M@160M mem_mali=32M@224M " \ - "pmem_hwb=128M@256M mem=128M@384M\0" \ - "memargs1024=mem=128M@0 mali.mali_mem=32M@128M " \ - "hwmem=168M@M160M mem=48M@328M " \ - "mem_issw=1M@383M mem=640M@384M\0" \ - "memargs=setenv bootargs ${bootargs} ${memargs1024}\0" \ - "emmcload=fatload mmc 0:2 ${loadaddr} uImage\0" \ - "mmcload=fatload mmc 1:1 ${loadaddr} uImage\0" \ - "commonargs=setenv bootargs console=${console} " \ - "vmalloc=300M\0" \ - "emmcargs=setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk0p3 " \ - "rootwait\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console}\0" \ - "emmcboot=echo Booting from eMMC ...; " \ - "run commonargs emmcargs memargs; " \ - "bootm ${loadaddr}\0" \ - "mmcargs=setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk1p2 " \ - "rootwait earlyprintk\0" \ - "mmcboot=echo Booting from external MMC ...; " \ - "run commonargs mmcargs memargs; " \ - "bootm ${loadaddr}\0" \ - "fdt_high=0x2BC00000\0" \ - "stdout=serial,usbtty\0" \ - "stdin=serial,usbtty\0" \ - "stderr=serial,usbtty\0" - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 - -#define CONFIG_SYS_HUSH_PARSER 1 -#define CONFIG_CMDLINE_EDITING - -#define CONFIG_SETUP_MEMORY_TAGS 2 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ - -/* - * additions for new relocation code - */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_MAX_RAM_SIZE 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET - -/* landing address before relocation */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x0 -#endif - -/* - * MMC related configs - */ -#define CONFIG_ARM_PL180_MMCI -#define MMC_BLOCK_SIZE 512 -#define CFG_EMMC_BASE 0x80114000 -#define CFG_MMC_BASE 0x80126000 - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_NO_FLASH - -/* - * base register values for U8500 - */ -#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock */ - - -/* - * U8500 GPIO register base for 9 banks - */ -#define CONFIG_DB8500_GPIO -#define CFG_GPIO_0_BASE 0x8012E000 -#define CFG_GPIO_1_BASE 0x8012E080 -#define CFG_GPIO_2_BASE 0x8000E000 -#define CFG_GPIO_3_BASE 0x8000E080 -#define CFG_GPIO_4_BASE 0x8000E100 -#define CFG_GPIO_5_BASE 0x8000E180 -#define CFG_GPIO_6_BASE 0x8011E000 -#define CFG_GPIO_7_BASE 0x8011E080 -#define CFG_GPIO_8_BASE 0xA03FE000 - -#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5_socdk.h index 3193684798..b75b0a27fa 100644 --- a/include/configs/socfpga_arria5.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -59,6 +59,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 38ae763653..cece0950e2 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -73,7 +73,6 @@ /* * Cache */ -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS @@ -282,7 +281,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE -#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE 4096 /* diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5_socdk.h index 9e733e5c48..fa67b25a79 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -59,6 +59,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index 2508d037e3..191e1f7a43 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -55,6 +55,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index c5b4b4ca9d..65816a05cf 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -43,6 +43,12 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +/* Environment is in MMC */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 747e988ac9..6c71ef4e23 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -59,6 +59,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index fb1bf66d02..edae831f22 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -97,7 +97,6 @@ #define CONFIG_NAND_FSMC #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_QUIET_TEST /* * Command support defines diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h deleted file mode 100644 index 87df70bdac..0000000000 --- a/include/configs/stamp9g20.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - * - * (C) Copyright 2010 - * Achim Ehrlich <aehrlich@taskit.de> - * taskit GmbH <www.taskit.de> - * - * (C) Copyright 2012 - * Markus Hubig <mhubig@imko.de> - * IMKO GmbH <www.imko.de> - * - * Configuation settings for the stamp9g20 CPU module. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * SoC must be defined first, before hardware.h is included. - * In this case SoC is defined in boards.cfg. - */ -#include <asm/hardware.h> - -/* - * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot - * program. Since the linker has to swallow that define, we must use a pure - * hex number here! - */ -#define CONFIG_SYS_TEXT_BASE 0x23f00000 - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ - -/* misc settings */ -#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */ -#define CONFIG_INITRD_TAG /* pass initrd param to kernel */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ -#define CONFIG_BOARD_EARLY_INIT_f /* call board_early_init_f() */ -#define CONFIG_BOARD_POSTCLK_INIT /* call board_postclk_init() */ -#define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */ - -/* setting board specific options */ -#ifdef CONFIG_PORTUXG20 -# define CONFIG_MACH_TYPE MACH_TYPE_PORTUXG20 -# define CONFIG_MACB -#else -# define CONFIG_MACH_TYPE MACH_TYPE_STAMP9G20 -#endif - -/* - * SDRAM: 1 bank, 64 MB, base address 0x20000000 - * Already initialized before u-boot gets started. - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE (64 << 20) - -/* - * Perform a SDRAM Memtest from the start of SDRAM - * till the beginning of the U-Boot position in RAM. - */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + (128 << 10), 0x1000) - -/* - * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above that - * address while providing maximum stack area below. - */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) - -/* NAND flash settings */ -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO /* enable the GPIO features */ -#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 - -/* LED configuration */ -#define CONFIG_STATUS_LED -#define CONFIG_BOARD_SPECIFIC_LED - -/* The LED PINs */ -#define CONFIG_RED_LED AT91_PIN_PC5 -#define CONFIG_GREEN_LED AT91_PIN_PC4 -#define CONFIG_YELLOW_LED AT91_PIN_PC10 - -#define STATUS_LED_RED 0 -#define STATUS_LED_GREEN 1 -#define STATUS_LED_YELLOW 2 - -/* Red LED */ -#define STATUS_LED_BIT STATUS_LED_RED -#define STATUS_LED_STATE STATUS_LED_OFF -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) - -/* Green LED */ -#define STATUS_LED_BIT1 STATUS_LED_GREEN -#define STATUS_LED_STATE1 STATUS_LED_ON -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) - -/* Yellow LED */ -#define STATUS_LED_BIT2 STATUS_LED_YELLOW -#define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) - -/* Boot status LED */ -#define STATUS_LED_BOOT STATUS_LED_GREEN - -/* - * Ethernet configuration - * - * PortuxG20 has always ethernet but for Stamp9G20 you - * can enable it here if your baseboard features ethernet. - */ - -#define CONFIG_MACB -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_USB_ETHER_MCS7830 - -#ifdef CONFIG_MACB -# define CONFIG_RMII /* use reduced MII inteface */ -# define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */ -#define CONFIG_AT91_WANTS_COMMON_PHY - -/* BOOTP and DHCP options */ -# define CONFIG_BOOTP_BOOTFILESIZE -# define CONFIG_BOOTP_BOOTPATH -# define CONFIG_BOOTP_GATEWAY -# define CONFIG_BOOTP_HOSTNAME -# define CONFIG_NFSBOOTCOMMAND \ - "setenv autoload yes; setenv autoboot yes; " \ - "setenv bootargs ${basicargs} ${mtdparts} " \ - "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \ - "dhcp" -#endif /* CONFIG_MACB */ - -/* Enable the watchdog */ -#define CONFIG_AT91SAM9_WATCHDOG -#define CONFIG_HW_WATCHDOG - -/* USB configuration */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - -/* General Boot Parameter */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING - -/* - * RAM Memory address where to put the - * Linux Kernel befor starting. - */ -#define CONFIG_SYS_LOAD_ADDR 0x22000000 - -/* - * The NAND Flash partitions: - * ========================================== - * 0x0000000-0x001ffff -> 128k, bootstrap - * 0x0020000-0x005ffff -> 256k, u-boot - * 0x0060000-0x007ffff -> 128k, env1 - * 0x0080000-0x009ffff -> 128k, env2 (backup) - * 0x0100000-0x06fffff -> 6M, kernel - * 0x0700000-0x8000000 -> 121M, RootFS - */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET ((128 + 256) << 10) -#define CONFIG_ENV_OFFSET_REDUND ((128 + 256 + 128) << 10) -#define CONFIG_ENV_SIZE (128 << 10) - -/* - * Predefined environment variables. - * Usefull to define some easy to use boot commands. - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - \ - "basicargs=console=ttyS0,115200\0" \ - \ - "mtdparts=mtdparts=atmel_nand:128k(bootstrap)ro," \ - "256k(uboot)ro,128k(env1)ro," \ - "128k(env2)ro,6M(linux),-(root)rw\0" \ - \ - "flashboot=setenv bootargs ${basicargs} ${mtdparts} " \ - "root=/dev/mtdblock5 rootfstype=jffs2; " \ - "nand read 0x22000000 0x100000 0x600000; " \ - "bootm 22000000\0" \ - \ - "sdboot=setenv bootargs ${basicargs} ${mtdparts} " \ - "root=/dev/mmcblk0p1 rootwait; " \ - "nand read 0x22000000 0x100000 0x600000; " \ - "bootm 22000000" - -/* Command line & features configuration */ -#define CONFIG_CMD_NAND -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_CMD_LED - -#ifdef CONFIG_MACB -# define CONFIG_CMD_PING -# define CONFIG_CMD_DHCP -#endif /* CONFIG_MACB */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/stout.h b/include/configs/stout.h new file mode 100644 index 0000000000..87ea530948 --- /dev/null +++ b/include/configs/stout.h @@ -0,0 +1,112 @@ +/* + * include/configs/stout.h + * This file is Stout board configuration. + * + * Copyright (C) 2015 Renesas Electronics Europe GmbH + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __STOUT_H +#define __STOUT_H + +#undef DEBUG +#define CONFIG_R8A7790 +#define CONFIG_RMOBILE_BOARD_STRING "Stout" + +#include "rcar-gen2-common.h" + +/* #define CONFIG_BOARD_LATE_INIT */ + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0xB0000000 +#else +#define CONFIG_SYS_TEXT_BASE 0xE8080000 +#endif + +/* STACK */ +#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC +#else +#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC +#endif +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_SCIF_A + +/* SPI */ +#define CONFIG_SPI +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_QUAD +#define CONFIG_SYS_NO_FLASH + +/* SH Ether */ +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_RCAR +#define CONFIG_SYS_RCAR_I2C0_SPEED 400000 +#define CONFIG_SYS_RCAR_I2C1_SPEED 400000 +#define CONFIG_SYS_RCAR_I2C2_SPEED 400000 +#define CONFIG_SYS_RCAR_I2C3_SPEED 400000 +#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ +#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) +#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) +#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) +#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) + +#define CONFIG_SYS_TMU_CLK_DIV 4 + +/* USB */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_USB_STORAGE + +/* MMC */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC + +/* Module stop status bits */ +/* INTC-RT */ +#define CONFIG_SMSTP0_ENA 0x00400000 +/* MSIF, SCIFA0 */ +#define CONFIG_SMSTP2_ENA 0x00002010 +/* INTC-SYS, IRQC */ +#define CONFIG_SMSTP4_ENA 0x00000180 + +/* SDHI */ +#define CONFIG_SH_SDHI_FREQ 97500000 + +#endif /* __STOUT_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 48cc4ed6f6..e1ba7914cd 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -13,6 +13,7 @@ #ifndef _SUNXI_COMMON_CONFIG_H #define _SUNXI_COMMON_CONFIG_H +#include <asm/arch/cpu.h> #include <linux/stringify.h> #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT @@ -39,23 +40,14 @@ #define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ #endif -#include <asm/arch/cpu.h> /* get chip and board defs */ - -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL) -# define CONFIG_DW_SERIAL -#endif - -/* - * Display CPU information - */ -#define CONFIG_DISPLAY_CPUINFO - /* Serial & console */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ #define CONFIG_SYS_NS16550_CLK 24000000 -#ifndef CONFIG_DM_SERIAL +#ifdef CONFIG_DM_SERIAL +# define CONFIG_DW_SERIAL +#else # define CONFIG_SYS_NS16550_REG_SIZE -4 # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE @@ -65,6 +57,7 @@ #endif /* CPU */ +#define CONFIG_DISPLAY_CPUINFO #define CONFIG_SYS_CACHELINE_SIZE 64 /* @@ -152,8 +145,8 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ #endif -/* 4MB of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) +/* 64MB of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20)) /* * Miscellaneous configurable options @@ -282,11 +275,7 @@ extern int soft_i2c_gpio_scl; * The amount of RAM to keep free at the top of RAM when relocating u-boot, * to use as framebuffer. This must be a multiple of 4096. */ -#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 -#define CONFIG_SUNXI_MAX_FB_SIZE (12 << 20) -#else -#define CONFIG_SUNXI_MAX_FB_SIZE (9 << 20) -#endif +#define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20) /* Do we want to initialize a simple FB? */ #define CONFIG_VIDEO_DT_SIMPLEFB @@ -393,12 +382,12 @@ extern int soft_i2c_gpio_scl; #define CONFIG_PRE_CON_BUF_SZ 4096 /* Aprox 2 80*25 screens */ /* - * 240M RAM (256M minimum minus space for the framebuffer), + * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, * 1M script, 1M pxe and the ramdisk at the end. */ #define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0xf000000\0" \ + "bootm_size=0xa000000\0" \ "kernel_addr_r=" __stringify(SDRAM_OFFSET(2000000)) "\0" \ "fdt_addr_r=" __stringify(SDRAM_OFFSET(3000000)) "\0" \ "scriptaddr=" __stringify(SDRAM_OFFSET(3100000)) "\0" \ @@ -423,7 +412,18 @@ extern int soft_i2c_gpio_scl; #define BOOT_TARGET_DEVICES_USB(func) #endif +/* FEL boot support, auto-execute boot.scr if a script address was provided */ +#define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \ + "bootcmd_fel=" \ + "if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \ + "echo '(FEL boot)'; " \ + "source ${fel_scriptaddr}; " \ + "fi\0" +#define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \ + "fel " + #define BOOT_TARGET_DEVICES(func) \ + func(FEL, fel, na) \ BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_USB(func) \ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 408895f332..bd1c07c3eb 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -126,7 +126,6 @@ /* * Board NAND Info. */ -#define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 66cb274f68..17b0213362 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -20,7 +20,7 @@ #define CONFIG_SYS_HZ 1000 -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 @@ -167,6 +167,8 @@ #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_EDID @@ -190,7 +192,7 @@ "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \ "rdinit=/sbin/init enable_wait_mode=off\0" \ "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \ - "mmc read 0x10800000 0x800 0x4000; bootm\0" \ + "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \ "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \ "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \ "run bootargs_upd; " \ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index e67ff7b957..651c4c4935 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -8,6 +8,21 @@ #ifndef __TEGRA_COMMON_POST_H #define __TEGRA_COMMON_POST_H +/* + * Size of malloc() pool + */ +#ifdef CONFIG_USB_FUNCTION_DFU +#define CONFIG_SYS_MALLOC_LEN (SZ_4M + \ + CONFIG_SYS_DFU_DATA_BUF_SIZE + \ + CONFIG_SYS_DFU_MAX_FILE_SIZE) +#else +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ +#endif + +#ifndef CONFIG_ARM64 +#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ +#endif + #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ diff --git a/include/configs/tegra-common-usb-gadget.h b/include/configs/tegra-common-usb-gadget.h index e51da3f405..f6e1d5c4db 100644 --- a/include/configs/tegra-common-usb-gadget.h +++ b/include/configs/tegra-common-usb-gadget.h @@ -30,7 +30,8 @@ #define CONFIG_CMD_USB_MASS_STORAGE /* DFU protocol */ #define CONFIG_USB_FUNCTION_DFU -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 * 1024 * 1024) +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M +#define CONFIG_SYS_DFU_MAX_FILE_SIZE SZ_32M #define CONFIG_CMD_DFU #ifdef CONFIG_MMC #define CONFIG_DFU_MMC @@ -38,6 +39,7 @@ #ifdef CONFIG_SPI_FLASH #define CONFIG_DFU_SF #endif +#define CONFIG_DFU_RAM #endif #endif /* _TEGRA_COMMON_USB_GADGET_H_ */ diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 6fe5f2ce65..1c469d092e 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -37,20 +37,6 @@ #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ /* - * Size of malloc() pool - */ -#ifdef CONFIG_DFU_MMC -#define CONFIG_SYS_MALLOC_LEN ((4 << 20) + \ - CONFIG_SYS_DFU_DATA_BUF_SIZE) -#else -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ -#endif - -#ifndef CONFIG_ARM64 -#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ -#endif - -/* * NS16550 Configuration */ #define CONFIG_TEGRA_SERIAL @@ -154,6 +140,8 @@ #ifndef CONFIG_SPL_BUILD #include <config_distro_defaults.h> +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_FAT_WRITE #endif #endif /* _TEGRA_COMMON_H_ */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 252e607d73..671071ba98 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -34,7 +34,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x80110000 /* * Memory layout for where various images get loaded by boot scripts: diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 0841f33bfc..00e85c48c4 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -32,7 +32,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x0010E000 +#define CONFIG_SYS_TEXT_BASE 0x00110000 /* * Memory layout for where various images get loaded by boot scripts: diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index e6c815212d..8f35a7bf3d 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -26,7 +26,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x80110000 /* Generic Interrupt Controller */ #define CONFIG_GICV2 diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 3e8e3c1e5b..9afd86484b 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -31,7 +31,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x80110000 /* * Memory layout for where various images get loaded by boot scripts: diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 7fa35a1542..ceeb7fe46b 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -21,6 +21,7 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_OMAP #define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD #include <asm/arch/omap.h> diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 01d8233741..4c192896ad 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -15,6 +15,7 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_OMAP #define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 18fca02c4c..6dc6515899 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -58,6 +58,15 @@ "ramdisk_addr_r=0x88080000\0" \ "bootm_size=0x10000000\0" +#define DEFAULT_MMC_TI_ARGS \ + "mmcdev=0\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "finduuid=part uuid mmc 0:2 uuid\0" \ + "args_mmc=run finduuid;setenv bootargs console=${console} " \ + "${optargs} " \ + "root=PARTUUID=${uuid} rw " \ + "rootfstype=${mmcrootfstype}\0" + /* * Default to a quick boot delay. */ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index be231a5513..e399a879ac 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -66,7 +66,7 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* TWL4030 */ -#define CONFIG_TWL4030_POWER 1 +#define CONFIG_TWL4030_POWER /* SPL */ #define CONFIG_SPL_TEXT_BASE 0x40200800 diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 2eaa3b61b4..1cd7dae85b 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -83,6 +83,7 @@ */ #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ "console=ttyO2,115200n8\0" \ "fdtfile=undefined\0" \ "bootpart=0:2\0" \ @@ -90,13 +91,6 @@ "bootfile=zImage\0" \ "usbtty=cdc_acm\0" \ "vram=16M\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "vram=${vram} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ "source ${loadaddr}\0" \ @@ -106,10 +100,10 @@ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc${mmcdev} ...; " \ - "run mmcargs; " \ + "run args_mmc; " \ "bootz ${loadaddr} - ${fdtaddr}\0" \ "uimageboot=echo Booting from mmc${mmcdev} ...; " \ - "run mmcargs; " \ + "run args_mmc; " \ "bootm ${loadaddr}\0" \ "findfdt="\ "if test $board_name = sdp4430; then " \ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 1c1f8c0830..189ea7e914 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -70,6 +70,7 @@ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ "console=" CONSOLEDEV ",115200n8\0" \ "fdtfile=undefined\0" \ "bootpart=0:2\0" \ @@ -80,14 +81,6 @@ "partitions=" PARTS_DEFAULT "\0" \ "optargs=\0" \ "dofastboot=0\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "vram=${vram} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ "source ${loadaddr}\0" \ @@ -110,7 +103,7 @@ "if run loadimage; then " \ "run loadfdt; " \ "echo Booting from mmc${mmcdev} ...; " \ - "run mmcargs; " \ + "run args_mmc; " \ "bootz ${loadaddr} - ${fdtaddr}; " \ "fi;" \ "fi;\0" \ diff --git a/include/configs/titanium.h b/include/configs/titanium.h index 1b4ca295bc..acfa84ab2c 100644 --- a/include/configs/titanium.h +++ b/include/configs/titanium.h @@ -33,6 +33,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/tk71.h b/include/configs/tk71.h deleted file mode 100644 index 46e8c90b45..0000000000 --- a/include/configs/tk71.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (C) 2012 Marek Vasut <marex@denx.de> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_TK71_H__ -#define __CONFIG_TK71_H__ - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nKa-Ro TK71" - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_NR_DRAM_BANKS 1 - -#define MACH_TYPE_TK71 2399 -#define CONFIG_MACH_TYPE MACH_TYPE_TK71 - -/* - * Commands configuration - */ -#define CONFIG_SYS_HUSH_PARSER - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_DOS_PARTITION -#define CONFIG_SUPPORT_VFAT - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * NAND flash - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS -#define CONFIG_JFFS2_NAND -#define CONFIG_JFFS2_DEV "nand0,3" -#endif - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} -#define CONFIG_PHY_BASE_ADR 0x08 -#endif - -/* - * USB/EHCI - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_KIRKWOOD -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#endif - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 -#else -#define CONFIG_ENV_IS_NOWHERE -#endif - -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_ADDR 0x80000 -#define CONFIG_ENV_OFFSET 0x80000 - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "nand read 0x800000 kernel 0x300000; bootm;" -#define CONFIG_MTDPARTS "512K(u-boot),512K(u-boot-env),3M(kernel),-(root)" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_uboot=dhcp u-boot.kwb; nand erase.part u-boot; nand write ${fileaddr} u-boot ${filesize}\0" \ - "update_kernel=dhcp uImage-tk71; nand erase.part kernel; nand write ${fileaddr} kernel ${filesize} \0" \ - "update_rootfs=dhcp rootfs-tk71; nand erase.part root; nand write ${fileaddr} root ${filesize}\0" \ - "update_all=run update_uboot; run update_kernel; run update_rootfs; reset\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts=mtdparts=orion_nand:"CONFIG_MTDPARTS"\0" \ - "bootargs=console=ttyS0,115200 mtdparts=orion_nand:"CONFIG_MTDPARTS" rootfstype=jffs2 root=/dev/mtdblock3 rw\0" -#define MTDIDS_DEFAULT "nand0=orion_nand" -#define MTDPARTS_DEFAULT "mtdparts=orion_nand:"CONFIG_MTDPARTS - -#define PHYS_SDRAM_1 0x00000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ - -#endif /* __CONFIG_TK71_H__ */ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index f7fade12f1..295e16303c 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -62,6 +62,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h deleted file mode 100644 index 40c8d718d8..0000000000 --- a/include/configs/trizepsiv.h +++ /dev/null @@ -1,309 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefano Babic, DENX Gmbh, sbabic@denx.de - * - * (C) Copyright 2004 - * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * Configuation settings for the LUBBOCK board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_CPU_PXA27X 1 /* This is an PXA27x CPU */ - -#define CONFIG_MMC 1 -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_SYS_TEXT_BASE 0x0 - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -#define RTC - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 /* we use FFUART on Conxs */ -#define CONFIG_BTUART 1 /* we use BTUART on Conxs */ -#define CONFIG_STUART 1 /* we use STUART on Conxs */ -#define CONFIG_CONS_INDEX 3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_DOS_PARTITION 1 - -/* - * Command line configuration. - */ -#define CONFIG_CMD_FAT -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ - -#undef CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_SERVERIP 192.168.1.99 -#define CONFIG_BOOTCOMMAND "run boot_flash" -#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\ - " rw root=/dev/ram initrd=0xa0800000,5m" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "program_boot_mmc=" \ - "mw.b 0xa0010000 0xff 0x20000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0010000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x1ffff; " \ - "erase 0x0 0x1ffff; " \ - "cp.b 0xa0010000 0x0 0x20000; " \ - "fi\0" \ - "program_uzImage_mmc=" \ - "mw.b 0xa0010000 0xff 0x180000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0010000 uzImage; " \ - "then " \ - "protect off 0x40000 0x1bffff; " \ - "erase 0x40000 0x1bffff; " \ - "cp.b 0xa0010000 0x40000 0x180000; " \ - "fi\0" \ - "program_ramdisk_mmc=" \ - "mw.b 0xa0010000 0xff 0x500000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0010000 ramdisk.gz; " \ - "then " \ - "protect off 0x1c0000 0x6bffff; " \ - "erase 0x1c0000 0x6bffff; " \ - "cp.b 0xa0010000 0x1c0000 0x500000; " \ - "fi\0" \ - "boot_mmc=" \ - "if mmcinit && " \ - "fatload mmc 0 0xa0030000 uzImage && " \ - "fatload mmc 0 0xa0800000 ramdisk.gz; " \ - "then " \ - "bootm 0xa0030000; " \ - "fi\0" \ - "boot_flash=" \ - "cp.b 0x1c0000 0xa0800000 0x500000; " \ - "bootm 0x40000\0" \ - -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -/* #define CONFIG_INITRD_TAG 1 */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#undef CONFIG_SYS_PROMPT -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ -#else -#endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ - -#define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ - -#ifdef CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x04000000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPSR0_VAL 0x00018000 -#define CONFIG_SYS_GPSR1_VAL 0x00000000 -#define CONFIG_SYS_GPSR2_VAL 0x400dc000 -#define CONFIG_SYS_GPSR3_VAL 0x00000000 -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -#define CONFIG_SYS_GPCR3_VAL 0x00000000 -#define CONFIG_SYS_GPDR0_VAL 0x00018000 -#define CONFIG_SYS_GPDR1_VAL 0x00028801 -#define CONFIG_SYS_GPDR2_VAL 0x520dc000 -#define CONFIG_SYS_GPDR3_VAL 0x0001E000 -#define CONFIG_SYS_GAFR0_L_VAL 0x801c0000 -#define CONFIG_SYS_GAFR0_U_VAL 0x00000013 -#define CONFIG_SYS_GAFR1_L_VAL 0x6990100A -#define CONFIG_SYS_GAFR1_U_VAL 0x00000008 -#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 -#define CONFIG_SYS_GAFR2_U_VAL 0x010900F2 -#define CONFIG_SYS_GAFR3_L_VAL 0x54000003 -#define CONFIG_SYS_GAFR3_U_VAL 0x00002401 -#define CONFIG_SYS_GRER0_VAL 0x00000000 -#define CONFIG_SYS_GRER1_VAL 0x00000000 -#define CONFIG_SYS_GRER2_VAL 0x00000000 -#define CONFIG_SYS_GRER3_VAL 0x00000000 - -#define CONFIG_SYS_GFER1_VAL 0x00000000 -#define CONFIG_SYS_GFER3_VAL 0x00000020 - -#if CONFIG_POLARIS -#define CONFIG_SYS_GFER0_VAL 0x00000001 -#define CONFIG_SYS_GFER2_VAL 0x00200000 -#else -#define CONFIG_SYS_GFER0_VAL 0x00000000 -#define CONFIG_SYS_GFER2_VAL 0x00000000 -#endif - -#define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */ - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x01FFFFFF /* CHECK */ -#define CONFIG_SYS_CCCR 0x02000290 /* 520Mhz */ - -/* - * Memory settings - */ - -#define CONFIG_SYS_MSC0_VAL 0x4df84df0 -#define CONFIG_SYS_MSC1_VAL 0x7ff87ff4 -#if CONFIG_POLARIS -#define CONFIG_SYS_MSC2_VAL 0xa2697ff8 -#else -#define CONFIG_SYS_MSC2_VAL 0xa26936d4 -#endif -#define CONFIG_SYS_MDCNFG_VAL 0x880009C9 -#define CONFIG_SYS_MDREFR_VAL 0x20ca201e -#define CONFIG_SYS_MDMRS_VAL 0x00220022 - -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000001 -#define CONFIG_SYS_MCMEM0_VAL 0x00004204 -#define CONFIG_SYS_MCMEM1_VAL 0x00010204 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00010504 -#define CONFIG_SYS_MCIO0_VAL 0x00008407 -#define CONFIG_SYS_MCIO1_VAL 0x0000c108 - -#define CONFIG_DRIVER_DM9000 1 - -#if CONFIG_POLARIS -#define CONFIG_DM9000_BASE 0x0C800000 -#else -#define CONFIG_DM9000_BASE 0x08000000 -#endif - -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) - -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1 -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "trizepsiv" -#define CONFIG_USB_STORAGE 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 - -/* - * FLASH and environment organization - */ - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define CONFIG_SYS_MONITOR_BASE 0 -#define CONFIG_SYS_MONITOR_LEN 0x40000 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* write flash less slowly */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -/* Unlock to be used with Intel chips */ -#define CONFIG_SYS_FLASH_PROTECTION 1 - -/* Flash environment locations */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */ -#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/tt01.h b/include/configs/tt01.h deleted file mode 100644 index ca1e2e25fb..0000000000 --- a/include/configs/tt01.h +++ /dev/null @@ -1,266 +0,0 @@ -/* - * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at> - * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> - * - * Configuration settings for the HALE TT-01 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - -/* High Level Configuration Options */ -#define CONFIG_MX31 - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */ -#define CONFIG_SYS_TEXT_BASE 0xA0000000 - - -/* - * Physical Memory Map: - * CS settings are defined by i.MX31: - * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000 - * - CS0 and CS1 are 128MB each, at A0000000 and A8000000 - * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6.. - * - * HALE set-up of the bluetechnix board for now is: - * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface - * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0 - * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM) - * the flash chip is a mirrorbit S29WS256N ! - * - the PSRAM is hooked to CS5 (0xB6000000) - * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1 - * - 64Mbit = 8MByte (will go away in the production set-up) - * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC: - * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks - * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface - * - * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM - * is not used right now. We should be able to reduce the SOM to NAND flash - * only and boot from there. - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD0_BASE -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) - -/* default load address, 1MB up the road */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000) - -/* Size of malloc() pool, make sure possible frame buffer fits */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024) - -/* memtest works on all but the last 1MB (u-boot) and malloc area */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END \ - (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000)) - -/* CFI FLASH driver setup */ -#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ -#define CONFIG_FLASH_SPANSION_S29WS_N -/* - * TODO: Bluetechnix (the supplier of the SOM) did define these values - * in their original version of u-boot (1.2 or so). This should be - * reviewed. - * - * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - * #define CONFIG_SYS_FLASH_PROTECTION - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */ - -/* - * FLASH and environment organization, only the Spansion chip is supported: - * - it has 254 * 128kB + 8 * 32kB blocks - * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF - * and 2 sectors with 128k as environment = - * A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF - * - this could be less, but this is only for developer versions of the board - * and no-one is going to use the NOR flash anyway. - * - * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is - * way to large, but it avoids ENV overwrite (when updating u-boot) in case - * size breaks the next boundary (as it has with 128k). - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (128 * 1024) - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -/* Hardware drivers */ - -/* - * on TT-01 UART1 pins are used by Audio, so we use UART2 - * TT-01 implements a hardware that turns off components depending on - * the power level. In PL=1 the RS232 transceiver is usually off, - * make sure that the transceiver is enabled during PL=1 for testing! - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE - -#define CONFIG_MXC_SPI -#define CONFIG_MXC_GPIO - -/* MC13783 connected to CSPI3 and SS0 */ -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL - -#define CONFIG_FSL_PMIC_BUS 2 -#define CONFIG_FSL_PMIC_CS 0 -#define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 - -#define CONFIG_RTC_MC13XXX - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -/* console is UART2 on TT-01 */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* ethernet setup for the onboard smc9118 */ -#define CONFIG_MII -#define CONFIG_SMC911X -/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */ -#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000) -#define CONFIG_SMC911X_16_BIT - -/* mmc driver */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_MXC_MMC -#define CONFIG_MXC_MCI_REGS_BASE SDHC1_BASE_ADDR - -/* video support */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_MX3 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -/* splash image won't work with NAND boot, use preboot script */ -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_CONSOLE_EXTRA_INFO /* display additional board info */ -#define CONFIG_VGA_AS_SINGLE_DEVICE /* display is an output only device */ - -/* allow stdin, stdout and stderr variables to redirect output */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SILENT_CONSOLE /* UARTs used externally (release) */ -#define CONFIG_SYS_DEVICE_NULLDEV /* allow console to be turned off */ -#define CONFIG_PREBOOT - -/* allow decompressing max. 4MB */ -#define CONFIG_VIDEO_BMP_GZIP -/* this is not only used by cfb_console.c for the logo, but also in cmd_bmp.c */ -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4*1024*1024) - -/* - * Command definition - */ -#define CONFIG_CMD_DATE -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NAND -/* - * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support - * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports - * a software locking scheme. - */ -#define CONFIG_CMD_BMP - -#define CONFIG_BOOTDELAY 3 - -/* - * currently a default setting for booting via script is implemented - * set user to login name and serverip to tftp host, define your - * boot behaviour in bootscript.loginname - * - * TT-01 board specific TFT setup (used by drivers/video/mx3fb.c) - * - * This set-up is for the L5F30947T04 by Epson, which is - * 800x480, 33MHz pixel clock, 60Hz vsync, 31.6kHz hsync - * sync must be set to: DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ -"videomode=epson\0" \ -"epson=video=ctfb:x:800,y:480,depth:16,mode:0,pclk:30076," \ - "le:215,ri:1,up:32,lo:13,hs:7,vs:10,sync:100663296,vmode:0\0" \ -"bootcmd=dhcp bootscript.${user}; source\0" - -#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */ -#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */ - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_HUSH_PARSER - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_CMDLINE_EDITING - -/* MMC boot support */ -#define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT - -#define CONFIG_NAND_MXC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* - * actually this is nothing someone wants to configure! - * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init() - * is not used by the driver. - */ -#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR -#define CONFIG_MXC_NAND_HWECC - -/* the current u-boot driver does not use the nand flash setup! */ -#define CONFIG_SYS_NAND_LARGEPAGE -/* - * it's not 16 bit: - * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT - * the current u-boot mxc_nand.c tries to auto-detect, but this only - * reads the boot settings during reset (which might be wrong) - */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/tx25.h b/include/configs/tx25.h deleted file mode 100644 index 834b6169f6..0000000000 --- a/include/configs/tx25.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby <jrigby@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - -/* - * KARO TX25 board - SoC Configuration - */ -#define CONFIG_MX25 -#define CONFIG_MX25_CLK32 32000 /* OSC32K frequency */ -#define CONFIG_SYS_TIMER_RATE CONFIG_MX25_CLK32 -#define CONFIG_SYS_TIMER_COUNTER \ - (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */ - -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" -#define CONFIG_SPL_MAX_SIZE 2048 -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT - -#define CONFIG_SPL_TEXT_BASE 0x810c0000 -#define CONFIG_SYS_TEXT_BASE 0x81200000 - -#ifndef MACH_TYPE_TX25 -#define MACH_TYPE_TX25 2177 -#endif - -#define CONFIG_MACH_TYPE MACH_TYPE_TX25 - -#ifdef CONFIG_SPL_BUILD -/* Start copying real U-boot from the second page */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 - -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST - -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#else -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -#define CONFIG_DISPLAY_CPUINFO - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Memory Info - */ -/* malloc() len */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ -/* - * Board has 2 32MB banks of DRAM but there is a bug when using - * both so only the first is configured - */ -#define CONFIG_NR_DRAM_BANKS 1 - -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE 0x02000000 -#if (CONFIG_NR_DRAM_BANKS == 2) -#define PHYS_SDRAM_2 0x90000000 -#define PHYS_SDRAM_2_SIZE 0x02000000 -#endif -/* 8MB DRAM test */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000) - -/* - * Serial Info - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ - -#define CONFIG_MXC_GPIO - -/* - * Flash & Environment - */ -/* No NOR flash present */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN -#define CONFIG_ENV_SIZE (128 * 1024) /* 128 kB NAND block size */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) - -/* NAND */ -#define CONFIG_NAND_MXC -#define CONFIG_MXC_NAND_REGS_BASE (0xBB000000) -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE (0xBB000000) -#define CONFIG_JFFS2_NAND -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE - -/* U-Boot general configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Print buffer sz */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP - -/* U-Boot commands */ -#define CONFIG_CMD_NAND -#define CONFIG_CMD_CACHE - -/* - * Ethernet - */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x1f -#define CONFIG_MII -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "u-boot=tx25/u-boot.bin\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "hostname=tx25\0" \ - "bootfile=tx25/uImage\0" \ - "rootpath=/opt/eldk/arm\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm\0" \ - "bootcmd=run net_nfs\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0" \ - "upd=run load update\0" \ - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (IMX_RAM_BASE + IMX_RAM_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/u8500_href.h b/include/configs/u8500_href.h deleted file mode 100644 index a8cc0306cb..0000000000 --- a/include/configs/u8500_href.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_U8500 - -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT - -/* - * Size of malloc() pool - */ -#ifdef CONFIG_BOOT_SRAM -#define CONFIG_ENV_SIZE (32*1024) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64*1024) -#else -#define CONFIG_ENV_SIZE (128*1024) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) -#endif - -/* - * PL011 Configuration - */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_SERIAL_RLCR -#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT - -/* - * U8500 UART registers base for 3 serial devices - */ -#define CFG_UART0_BASE 0x80120000 -#define CFG_UART1_BASE 0x80121000 -#define CFG_UART2_BASE 0x80007000 -#define CFG_SERIAL0 CFG_UART0_BASE -#define CFG_SERIAL1 CFG_UART1_BASE -#define CFG_SERIAL2 CFG_UART2_BASE -#define CONFIG_PL011_CLOCK 38400000 -#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \ - (void *)CFG_SERIAL2 } -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* - * Devices and file systems - */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_DOS_PARTITION - -/* - * Commands - */ -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_I2C - -#ifndef CONFIG_BOOTDELAY -#define CONFIG_BOOTDELAY 1 -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "run emmcboot" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr=0x00100000\0" \ - "console=ttyAMA2,115200n8\0" \ - "memargs256=mem=96M@0 mem_modem=32M@96M mem=30M@128M " \ - "pmem=22M@158M pmem_hwb=44M@180M mem_mali=32@224M\0" \ - "memargs512=mem=96M@0 mem_modem=32M@96M mem=44M@128M " \ - "pmem=22M@172M mem=30M@194M mem_mali=32M@224M " \ - "pmem_hwb=54M@256M mem=202M@310M\0" \ - "commonargs=setenv bootargs cachepolicy=writealloc noinitrd " \ - "init=init " \ - "board_id=${board_id} " \ - "logo.${logo} " \ - "startup_graphics=${startup_graphics}\0" \ - "emmcargs=setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk0p2 " \ - "rootdelay=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console}\0" \ - "emmcboot=echo Booting from eMMC ...; " \ - "run commonargs emmcargs addcons memargs;" \ - "mmc read 0 ${loadaddr} 0xA0000 0x4000;" \ - "bootm ${loadaddr}\0" \ - "flash=mmc init 1;fatload mmc 1 ${loadaddr} flash.scr;" \ - "source ${loadaddr}\0" \ - "loaduimage=mmc init 1;fatload mmc 1 ${loadaddr} uImage\0" \ - "usbtty=cdc_acm\0" \ - "stdout=serial,usbtty\0" \ - "stdin=serial,usbtty\0" \ - "stderr=serial,usbtty\0" - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING - -#define CONFIG_SETUP_MEMORY_TAGS 2 -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ - -/* - * I2C - */ -#define CONFIG_U8500_I2C -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0 /* slave addr of controller */ -#define CONFIG_SYS_U8500_I2C0_BASE 0x80004000 -#define CONFIG_SYS_U8500_I2C1_BASE 0x80122000 -#define CONFIG_SYS_U8500_I2C2_BASE 0x80128000 -#define CONFIG_SYS_U8500_I2C3_BASE 0x80110000 -#define CONFIG_SYS_U8500_I2C_BUS_MAX 4 - -#define CONFIG_SYS_I2C_GPIOE_ADDR 0x42 /* GPIO expander chip addr */ -#define CONFIG_TC35892_GPIO - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ -#define PHYS_SDRAM_SIZE_1 0x20000000 /* 512 MB */ - -/* - * additions for new relocation code - */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET - -/* landing address before relocation */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x0 -#endif - -/* - * MMC related configs - * NB Only externa SD slot is currently supported - */ -#define MMC_BLOCK_SIZE 512 -#define CONFIG_ARM_PL180_MMCI -#define CONFIG_ARM_PL180_MMCI_BASE 0x80126000 /* MMC base for 8500 */ -#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000 -#define CONFIG_MMC_DEV_NUM 1 - -#define CONFIG_CMD_ENV -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET 0x13F80000 -#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */ - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_NO_FLASH - -/* - * base register values for U8500 - */ -#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock - management unit */ -#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index d59564bafd..9109b7f8d9 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -9,73 +9,9 @@ #ifndef __CONFIG_UNIPHIER_COMMON_H__ #define __CONFIG_UNIPHIER_COMMON_H__ -#if defined(CONFIG_MACH_PH1_SLD3) -#define CONFIG_DDR_NUM_CH0 2 -#define CONFIG_DDR_NUM_CH1 1 -#define CONFIG_DDR_NUM_CH2 1 - -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x20000000 -#define CONFIG_SDRAM1_BASE 0xc0000000 -#define CONFIG_SDRAM1_SIZE 0x20000000 -#define CONFIG_SDRAM2_BASE 0xc0000000 -#define CONFIG_SDRAM2_SIZE 0x10000000 -#endif - -#if defined(CONFIG_MACH_PH1_LD4) -#define CONFIG_DDR_NUM_CH0 1 -#define CONFIG_DDR_NUM_CH1 1 - -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x10000000 -#define CONFIG_SDRAM1_BASE 0x90000000 -#define CONFIG_SDRAM1_SIZE 0x10000000 -#endif - -#if defined(CONFIG_MACH_PH1_PRO4) -#define CONFIG_DDR_NUM_CH0 2 -#define CONFIG_DDR_NUM_CH1 2 - -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x20000000 -#define CONFIG_SDRAM1_BASE 0xa0000000 -#define CONFIG_SDRAM1_SIZE 0x20000000 -#endif - -#if defined(CONFIG_MACH_PH1_SLD8) -#define CONFIG_DDR_NUM_CH0 1 -#define CONFIG_DDR_NUM_CH1 1 - -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x10000000 -#define CONFIG_SDRAM1_BASE 0x90000000 -#define CONFIG_SDRAM1_SIZE 0x10000000 -#endif - #define CONFIG_I2C_EEPROM #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -/* - * Support card address map - */ -#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) -# define CONFIG_SUPPORT_CARD_BASE 0x03f00000 -# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) -# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000) -# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000) -#endif - -#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) -# define CONFIG_SUPPORT_CARD_BASE 0x08000000 -# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) -# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630) -# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000) -#endif - #ifdef CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE @@ -90,7 +26,8 @@ #define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE +/* dummy: referenced by examples/standalone/smc911x_eeprom.c */ +#define CONFIG_SMC911X_BASE 0 #define CONFIG_SMC911X_32_BIT /*----------------------------------------------------------------------- @@ -140,7 +77,7 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 /* serial console configuration */ #define CONFIG_BAUDRATE 115200 @@ -191,7 +128,7 @@ #define CONFIG_NAND_DENALI_ECC_SIZE 1024 -#ifdef CONFIG_MACH_PH1_SLD3 +#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 #else @@ -240,21 +177,17 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ "tftpboot; bootm;" -#define CONFIG_BOOTARGS " earlyprintk loglevel=8" - #ifdef CONFIG_FIT #define CONFIG_BOOTFILE "fitImage" #define LINUXBOOT_ENV_SETTINGS \ "fit_addr=0x00100000\0" \ "fit_addr_r=0x84100000\0" \ "fit_size=0x00f00000\0" \ - "norboot=run add_default_bootargs &&" \ + "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ "bootm $fit_addr\0" \ - "nandboot=run add_default_bootargs &&" \ - "nand read $fit_addr_r $fit_addr $fit_size &&" \ + "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ "bootm $fit_addr_r\0" \ - "tftpboot=run add_default_bootargs &&" \ - "tftpboot $fit_addr_r $bootfile &&" \ + "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ "bootm $fit_addr_r\0" #else #define CONFIG_BOOTFILE "uImage" @@ -270,15 +203,15 @@ "ramdisk_addr_r=0x84a00000\0" \ "ramdisk_size=0x00600000\0" \ "ramdisk_file=rootfs.cpio.uboot\0" \ - "norboot=run add_default_bootargs &&" \ + "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ + "setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \ + "setexpr fdt_addr $nor_base + $fdt_addr &&" \ "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \ - "nandboot=run add_default_bootargs &&" \ - "nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ + "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ - "tftpboot=run add_default_bootargs &&" \ - "tftpboot $kernel_addr_r $bootfile &&" \ + "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ "tftpboot $fdt_addr_r $fdt_file &&" \ "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" @@ -287,35 +220,25 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "verify=n\0" \ + "norbase=0x42000000\0" \ "nandupdate=nand erase 0 0x00100000 &&" \ "tftpboot u-boot-spl-dtb.bin &&" \ "nand write $loadaddr 0 0x00010000 &&" \ "tftpboot u-boot-dtb.img &&" \ "nand write $loadaddr 0x00010000 0x000f0000\0" \ - "add_default_bootargs=setenv bootargs $bootargs" \ - " console=ttyS0,$baudrate\0" \ LINUXBOOT_ENV_SETTINGS /* Open Firmware flat tree */ #define CONFIG_OF_LIBFDT -/* Memory Size & Mapping */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE - -#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE -/* Thre is no memory hole */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE) -#else +#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_NR_DRAM_BANKS 2 -#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE) -#endif -#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \ - defined(CONFIG_MACH_PH1_SLD8) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) #define CONFIG_SPL_TEXT_BASE 0x00040000 -#endif -#if defined(CONFIG_MACH_PH1_PRO4) +#else #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 4a7702cd09..714e3e2ca2 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -67,6 +67,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ /* Fuse */ #define CONFIG_CMD_FUSE diff --git a/include/configs/versatile.h b/include/configs/versatile.h deleted file mode 100644 index 636ca436d9..0000000000 --- a/include/configs/versatile.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta <kshitij@ti.com> - * Configuation settings for the TI OMAP Innovator board. - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, <philippe.robin@arm.com> - * Configuration for Versatile PB. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_VERSATILE 1 /* This is Versatile Platform Board */ -#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */ - -#define CONFIG_SYS_MEMTEST_START 0x100000 -#define CONFIG_SYS_MEMTEST_END 0x10000000 - -#define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */ -#define CONFIG_SYS_TIMER_RATE (1000000 / 256) -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) -#define CONFIG_SYS_TIMER_COUNTS_DOWN - -/* - * control registers - */ -#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ - -/* - * System controller bit assignment - */ -#define VERSATILE_REFCLK 0 -#define VERSATILE_TIMCLK 1 - -#define VERSATILE_TIMER1_EnSel 15 -#define VERSATILE_TIMER2_EnSel 17 -#define VERSATILE_TIMER3_EnSel 19 -#define VERSATILE_TIMER4_EnSel 21 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_MISC_INIT_R 1 -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE 8192 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_SMC91111 -#define CONFIG_SMC_USE_32_BIT -#define CONFIG_SMC91111_BASE 0x10010000 -#undef CONFIG_SMC91111_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS \ - {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1 } -#define CONFIG_CONS_INDEX 0 - -#define CONFIG_BAUDRATE 38400 -#define CONFIG_SYS_SERIAL0 0x101F1000 -#define CONFIG_SYS_SERIAL1 0x101F2000 - -/* - * Command line configuration. - */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK - -#define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\ - "netdev=25,0,0xf1010000,0xf1010010,eth0 "\ - "console=ttyAMA0,38400n1" - -/* - * Static configuration when assigning fixed address - */ -#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Monitor Command Prompt */ -#undef CONFIG_SYS_PROMPT -#ifdef CONFIG_ARCH_VERSATILE_AB -# define CONFIG_SYS_PROMPT "VersatileAB # " -#else -# define CONFIG_SYS_PROMPT "VersatilePB # " -#endif -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x00800000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -#define CONFIG_BOARD_EARLY_INIT_F - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#ifdef CONFIG_ARCH_VERSATILE_QEMU -#define CONFIG_SYS_TEXT_BASE 0x10000 -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#else -#define CONFIG_SYS_TEXT_BASE 0x01000000 -/* - * Use the CFI flash driver for ease of use - */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_ENV_IS_IN_FLASH 1 -/* - * System control register - */ -#define VERSATILE_SYS_BASE 0x10000000 -#define VERSATILE_SYS_FLASH_OFFSET 0x4C -#define VERSATILE_FLASHCTRL \ - (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET) -/* Enable writing to flash */ -#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ - -/* - * Note that CONFIG_SYS_MAX_FLASH_SECT allows for a parameter block - * i.e. - * the bottom "sector" (bottom boot), or top "sector" - * (top boot), is a seperate erase region divided into - * 4 (equal) smaller sectors. This, notionally, allows - * quicker erase/rewrire of the most frequently changed - * area...... - * CONFIG_SYS_MAX_FLASH_SECT is padded up to a multiple of 4 - */ - -#ifdef CONFIG_ARCH_VERSATILE_AB -#define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB sectors */ -#define CONFIG_ENV_SECT_SIZE (2 * FLASH_SECTOR_SIZE) -#define CONFIG_SYS_MAX_FLASH_SECT (520) -#endif - -#ifdef CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */ -#define FLASH_SECTOR_SIZE 0x00040000 /* 256 KB sectors */ -#define CONFIG_ENV_SECT_SIZE FLASH_SECTOR_SIZE -#define CONFIG_SYS_MAX_FLASH_SECT (260) -#endif - -#define CONFIG_SYS_FLASH_BASE 0x34000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#define CONFIG_SYS_MONITOR_LEN (4 * CONFIG_ENV_SECT_SIZE) - -/* The ARM Boot Monitor is shipped in the lowest sector of flash */ - -#define FLASH_TOP (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE) -#define CONFIG_ENV_ADDR (FLASH_TOP - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_MONITOR_BASE (CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN) - -#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 6107c64dd2..ef3014d68b 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -30,7 +30,8 @@ #define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a" /* Link Definitions */ -#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP +#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ + defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) /* ATF loads u-boot here for BASE_FVP model */ #define CONFIG_SYS_TEXT_BASE 0x88000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) @@ -41,6 +42,8 @@ #error "Unknown board variant" #endif +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT @@ -101,7 +104,8 @@ #define GICR_BASE (0x2f100000) #else -#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP +#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ + defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) #define GICD_BASE (0x2f000000) #define GICC_BASE (0x2c000000) #elif CONFIG_TARGET_VEXPRESS64_JUNO @@ -183,25 +187,46 @@ * be copied into DRAM */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_name=Image\0" \ + "kernel_name=norkern\0" \ + "kernel_alt_name=Image\0" \ "kernel_addr=0x80000000\0" \ - "fdt_name=juno\0" \ + "initrd_name=ramdisk.img\0" \ + "initrd_addr=0x84000000\0" \ + "fdt_name=board.dtb\0" \ + "fdt_alt_name=juno\0" \ "fdt_addr=0x83000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ /* Assume we boot with root on the first partition of a USB stick */ #define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " \ - "root=/dev/sda1 rw " \ + "root=/dev/sda2 rw " \ "rootwait "\ - "earlyprintk=pl011,0x7ff80000 debug user_debug=31 "\ + "earlyprintk=pl011,0x7ff80000 debug "\ + "user_debug=31 "\ + "androidboot.hardware=juno "\ "loglevel=9" /* Copy the kernel and FDT to DRAM memory and boot */ #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \ + "if test $? -eq 1; then "\ + " echo Loading ${kernel_alt_name} instead of "\ + "${kernel_name}; "\ + " afs load ${kernel_alt_name} ${kernel_addr};"\ + "fi ; "\ "afs load ${fdt_name} ${fdt_addr} ; " \ + "if test $? -eq 1; then "\ + " echo Loading ${fdt_alt_name} instead of "\ + "${fdt_name}; "\ + " afs load ${fdt_alt_name} ${fdt_addr}; "\ + "fi ; "\ "fdt addr ${fdt_addr}; fdt resize; " \ - "booti ${kernel_addr} - ${fdt_addr}" + "if afs load ${initrd_name} ${initrd_addr} ; "\ + "then "\ + " setenv initrd_param ${initrd_addr}; "\ + " else setenv initrd_param -; "\ + "fi ; " \ + "booti ${kernel_addr} ${initrd_param} ${fdt_addr}" #define CONFIG_BOOTDELAY 1 @@ -222,13 +247,33 @@ #define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \ "smhload ${fdt_name} ${fdt_addr}; " \ - "smhload ${initrd_name} ${initrd_addr} initrd_end; " \ + "smhload ${initrd_name} ${initrd_addr} "\ + "initrd_end; " \ "fdt addr ${fdt_addr}; fdt resize; " \ "fdt chosen ${initrd_addr} ${initrd_end}; " \ "booti $kernel_addr - $fdt_addr" #define CONFIG_BOOTDELAY 1 +#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=0x80080000\0" \ + "initrd_addr=0x84000000\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" + +#define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\ + "0x1c090000 debug user_debug=31 "\ + "androidboot.hardware=fvpbase "\ + "root=/dev/vda2 rw "\ + "rootwait "\ + "loglevel=9" + +#define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr" + +#define CONFIG_BOOTDELAY 1 + #else #error "Unknown board variant" #endif diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index c5131af340..324ba8f0cc 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -110,6 +110,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/vision2.h b/include/configs/vision2.h deleted file mode 100644 index b43373f134..0000000000 --- a/include/configs/vision2.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * Configuration settings for the MX51-3Stack Freescale board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - - -#define CONFIG_MX51 /* in a mx51 */ -#define CONFIG_SYS_TEXT_BASE 0x97800000 - -#include <asm/arch/imx-regs.h> - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_BOARD_LATE_INIT - -#ifndef MACH_TYPE_TTC_VISION2 -#define MACH_TYPE_TTC_VISION2 2775 -#endif -#define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* - * Hardware drivers - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART3_BASE -#define CONFIG_MXC_GPIO -#define CONFIG_MXC_SPI -#define CONFIG_HW_WATCHDOG - - /* - * SPI Configs - * */ -#define CONFIG_FSL_SF -#define CONFIG_CMD_SF - -#define CONFIG_SPI_FLASH_STMICRO - -/* - * Use gpio 4 pin 25 as chip select for SPI flash - * This corresponds to gpio 121 - */ -#define CONFIG_SF_DEFAULT_CS 1 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SF_DEFAULT_SPEED 25000000 - -#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_MAX_HZ 25000000 -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 - -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) -#define CONFIG_ENV_SIZE (4 * 1024) - -#define CONFIG_FSL_ENV_IN_SF -#define CONFIG_ENV_IS_IN_SPI_FLASH - -/* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL -#define CONFIG_FSL_PMIC_BUS 0 -#define CONFIG_FSL_PMIC_CS 0 -#define CONFIG_FSL_PMIC_CLK 2500000 -#define CONFIG_FSL_PMIC_MODE SPI_MODE_0 -#define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX - -/* - * MMC Configs - */ -#define CONFIG_FSL_ESDHC -#ifdef CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000) -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -#define CONFIG_MMC - -#define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif - -#define CONFIG_CMD_DATE - -/* - * Eth Configs - */ -#define CONFIG_HAS_ETH1 -#define CONFIG_MII - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1F - -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 3 -#define CONFIG_BAUDRATE 115200 - -/*********************************************************** - * Command definition - ***********************************************************/ - -#define CONFIG_CMD_SPI - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=0x90800000\0" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x90000000 -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_HUSH_PARSER - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_BOARD_EARLY_INIT_F - -/* 166 MHz DDR RAM */ -#define CONFIG_SYS_DDR_CLKSEL 0 -#define CONFIG_SYS_CLKTL_CBCDR 0x19239100 -#define CONFIG_SYS_MAIN_PWR_ON - -#define CONFIG_SYS_NO_FLASH - -/* - * Framebuffer and LCD - */ -#define CONFIG_PREBOOT -#define CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_CMD_BMP -#define CONFIG_BMP_16BPP -#define CONFIG_IPUV3_CLK 133000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h deleted file mode 100644 index 3facd7f257..0000000000 --- a/include/configs/vl_ma2sc.h +++ /dev/null @@ -1,429 +0,0 @@ -/* - * (C) Copyright 2009-2012 - * Jens Scharsig <esw@bus-elekronik.de> - * BuS Elektronik GmbH & Co. KG - * - * Configuation settings for the VL_MA2SC board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*--------------------------------------------------------------------------*/ - -#define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/ -#define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */ -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_MISC_INIT_R - -#include <asm/hardware.h> - -#define MACH_TYPE_VL_MA2SC 2412 -#define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC - -#define CONFIG_SYS_DCACHE_OFF - -#ifdef CONFIG_RAMLOAD -#define CONFIG_SYS_TEXT_BASE 0x21000000 -#else -#define CONFIG_SYS_TEXT_BASE 0x00000000 -#endif -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ - -#define CONFIG_IDENT_STRING " on MiS Activ 2" -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AT91_GPIO - -#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD) -#define CONFIG_SYS_USE_NORFLASH -#define CONFIG_SYS_USE_BOOT_NORFLASH -#endif - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#ifndef CONFIG_SYS_USE_BOOT_NORFLASH -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* - * Hardware drivers - */ - -#define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_WATCHDOG - -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -/* LCD */ -#define CONFIG_LCD -#define CONFIG_ATMEL_LCD -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SYS_BLACK_ON_WHITE -#define LCD_BPP LCD_COLOR8 -#define CONFIG_ATMEL_LCD_BGR555 - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_BOOTDELAY 3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BMP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NAND -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_MD5SUM -#define CONFIG_CMD_SHA1SUM -/* -#define CONFIG_CMD_SPI -*/ -#define CONFIG_CMD_FAT -#define CONFIG_CMD_USB - -#define CONFIG_SYS_LONGHELP -#define CONFIG_MD5 -#define CONFIG_SHA1 - -/*---------------------------------------------------------------------------- - * Hardware confuguration - *---------------------------------------------------------------------------*/ - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE -#define CONFIG_AT91C_PQFP_UHPBUG - -/* I2C-Bus */ - -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ - -#ifndef CONFIG_HARD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE - -/* Software I2C driver configuration */ -#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) - -#define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */ -#define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */ - -#define I2C_INIT i2c_init_board(); -#define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr); -#define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder); -#define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0) -#define I2C_SDA(bit) \ - do { \ - if (bit) \ - writel(AT91_PIN_SDA, &pio->piob.sodr); \ - else \ - writel(AT91_PIN_SDA, &pio->piob.codr); \ - } while (0); -#define I2C_SCL(bit) \ - do { \ - if (bit) \ - writel(AT91_PIN_SCL, &pio->piob.sodr); \ - else \ - writel(AT91_PIN_SCL, &pio->piob.codr); \ - } while (0); -#endif - -/* I2C-RTC */ - -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#endif - -/* EEPROM */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 - -/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 - -/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ - (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ - AT91_MATRIX_CSA_EBI_CS1A) - -/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ - (AT91_RSTC_KEY | \ - AT91_RSTC_MR_URSTEN | \ - AT91_RSTC_MR_ERSTL(15)) - -/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ - AT91_WDT_MR_WDV(0xFFF) | \ - AT91_WDT_MR_WDDIS | \ - AT91_WDT_MR_WDD(0xFFF)) - -/* clocks */ - -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define MHZ180 -#if defined(MHZ199) -/* 199,8994 MHZ */ -#define MASTER_PLL_MUL 911 -#define MASTER_PLL_DIV 56 -#define MASTER_PLL_OUT 2 -#elif defined(MHZ180) -/* 180 MHZ */ -#define MASTER_PLL_MUL 1875 -#define MASTER_PLL_DIV 128 -#define MASTER_PLL_OUT 2 -#elif defined(MHZTEST) -/* Test MHZ */ -#define CONFIG_DISPLAY_CPUINFO -#define MASTER_PLL_MUL 8 -#define MASTER_PLL_DIV 1 -#define MASTER_PLL_OUT 2 -#else -/* 176.9472 MHZ */ -#define MASTER_PLL_MUL 72 -#define MASTER_PLL_DIV 5 -#define MASTER_PLL_OUT 2 -#endif - -#define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) - -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLAR_29 | \ - AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ - AT91_PMC_PLLXR_PLLCOUNT(63) | \ - AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ - AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_2) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_2) - -/* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ -#define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */ - -#define CONFIG_SYS_SDRC_MR_VAL1 0 -#define CONFIG_SYS_SDRC_TR_VAL1 700 -#define CONFIG_SYS_SDRC_CR_VAL \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_3 | \ - AT91_SDRAMC_DBW_32 | \ - (2 << 8) | /* Write Recovery Delay */ \ - (7 << 12) | /* Row Cycle Delay */ \ - (2 << 16) | /* Row Precharge Delay */ \ - (2 << 20) | /* Row to Column Delay */ \ - (5 << 24) | /* Active to Precharge Delay */ \ - (8 << 28)) /* Exit Self Refresh to Active Delay */ - -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ - -/* NOR flash */ - -#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) - -/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ - AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ - AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ - AT91_SMC_MODE_DBW_16 | \ - AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) -#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(0) -#endif - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 5 -#define CONFIG_AT91_WANTS_COMMON_PHY - -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x21e00000 - -/* Address and size of Primary Environment Sector */ -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 0x20000 -#else -#define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \ - 38400, 57600, 9600 } - -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) - -#ifndef CONFIG_RAMLOAD -#define CONFIG_BOOTCOMMAND "run nfsboot" -#endif -#define CONFIG_BOOT_RETRY_TIME -1 -#define CONFIG_BOOT_RETRY_MIN 15 - -#define CONFIG_NFSBOOTCOMMAND \ - "dhcp $(copy_addr) $(kernelname);" \ - "run bootargsdefaults;" \ - "set bootargs $(bootargs) boot=nfs " \ - ";echo $(bootargs)" \ - ";bootm" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ubootaddr=10000000\0" \ - "splashimage=10080000\0" \ - "kerneladdr=100A0000\0" \ - "kernelsize=00800000\0" \ - "minifsaddr=108A0000\0" \ - "minifssize=00060000\0" \ - "rootfsaddr=10900000\0" \ - "copy_addr=20200000\0" \ - "rootfssize=01700000\0" \ - "kernelname=uImage_vl_ma2sc\0" \ - "bootargsdefaults=set bootargs " \ - "console=ttyS0,115200 " \ - "video=atmel_lcdfb " \ - "mem=62M " \ - "panic=10 " \ - "boardrevison=\\\"${revision}\\\" " \ - "uboot=\\\"${ver}\\\" " \ - "\0" \ - "update_all=run update_kernel;run update_root;" \ - "run update_splash; run update_uboot\0" \ - "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \ - "dhcp $(copy_addr) $(kernelname);" \ - "erase $(kerneladdr) +$(kernelsize);" \ - "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \ - "protect on $(kerneladdr) +$(kernelsize)" \ - "\0" \ - "update_root=protect off $(rootfsaddr) +$(rootfssize);" \ - "dhcp $(copy_addr) vl_ma2sc.root;" \ - "erase $(rootfsaddr) +$(rootfssize);" \ - "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \ - "\0" \ - "update_splash=protect off $(splashimage) +20000;" \ - "dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \ - "erase $(splashimage) +20000;" \ - "cp.b $(fileaddr) 10080000 $(filesize);" \ - "protect on $(splashimage) +20000\0" \ - "update_uboot=protect off 10000000 1005FFFF;" \ - "dhcp $(copy_addr) u-boot_vl_ma2sc;" \ - "erase 10000000 1005FFFF;" \ - "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \ - "protect on 10000000 1005FFFF;reset\0" \ - "emergency=run bootargsdefaults;" \ - "set bootargs $(bootargs) root=initramfs boot=emergency " \ - ";bootm $(kerneladdr)\0" \ - "netemergency=run bootargsdefaults;" \ - "dhcp $(copy_addr) $(kernelname);" \ - "set bootargs $(bootargs) root=initramfs boot=emergency " \ - ";bootm $(copy_addr)\0" \ - "norboot=run bootargsdefaults;" \ - "set bootargs $(bootargs) root=initramfs boot=local quiet " \ - ";bootm $(kerneladdr)\0" \ - "nandboot=run bootargsdefaults;" \ - "set bootargs $(bootargs) root=initramfs boot=nand " \ - ";bootm $(kerneladdr)\0" \ - "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \ - "clearenv=protect off 10060000 1007FFFF;" \ - "erase 10060000 1007FFFF;reset\0" \ - " " - -#endif diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h deleted file mode 100644 index 976ba5db74..0000000000 --- a/include/configs/vpac270.h +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Voipac PXA270 configuration file - * - * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ -#define CONFIG_VPAC270 1 /* Voipac PXA270 board */ -#define CONFIG_SYS_TEXT_BASE 0xa0000000 - -#ifdef CONFIG_ONENAND -#define CONFIG_SPL_ONENAND_SUPPORT -#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x2000 -#define CONFIG_SPL_ONENAND_LOAD_SIZE \ - (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR) -#define CONFIG_SPL_TEXT_BASE 0x5c000000 -#define CONFIG_SPL_LDSCRIPT "board/vpac270/u-boot-spl.lds" -#endif - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_MALLOC_LEN (128*1024) -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_BOOTCOMMAND \ - "if mmc init && fatload mmc 0 0xa4000000 uImage; then " \ - "bootm 0xa4000000; " \ - "fi; " \ - "if usb reset && fatload usb 0 0xa4000000 uImage; then " \ - "bootm 0xa4000000; " \ - "fi; " \ - "if ide reset && fatload ide 0 0xa4000000 uImage; then " \ - "bootm 0xa4000000; " \ - "fi; " \ - "bootm 0x60000;" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_onenand=" \ - "onenand erase 0x0 0x80000 ; " \ - "onenand write 0xa0000000 0x0 0x80000" - -#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_LZMA /* LZMA compression support */ -#define CONFIG_OF_LIBFDT - -/* - * Serial Console Configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 -#define CONFIG_CONS_INDEX 3 -#define CONFIG_BAUDRATE 115200 - -/* - * Bootloader Components Configuration - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MMC -#define CONFIG_CMD_USB -#undef CONFIG_LCD -#define CONFIG_CMD_IDE - -#ifdef CONFIG_ONENAND -#define CONFIG_CMD_ONENAND -#else -#undef CONFIG_CMD_ONENAND -#endif - -/* - * Networking Configuration - * chip on the Voipac PXA270 board - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */ -#define DM9000_IO (CONFIG_DM9000_BASE) -#define DM9000_DATA (CONFIG_DM9000_BASE + 4) -#define CONFIG_NET_RETRY_COUNT 10 - -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#endif - -/* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_DOS_PARTITION -#endif - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#endif - -/* - * HUSH Shell Configuration - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP -#ifdef CONFIG_SYS_HUSH_PARSER -#else -#endif -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_DEVICE_NULLDEV 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_AUTO_COMPLETE 1 - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */ - - -/* - * DRAM Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ - -#ifdef CONFIG_RAM_256M -#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ -#endif - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#ifdef CONFIG_RAM_256M -#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */ -#else -#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ -#endif - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 - -/* - * NOR FLASH - */ -#define CONFIG_SYS_MONITOR_BASE 0x0 -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 - -#if defined(CONFIG_CMD_FLASH) /* NOR */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#ifdef CONFIG_RAM_256M -#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ -#endif - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) -#ifdef CONFIG_RAM_256M -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } -#else -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#endif - -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_FLASH_PROTECTION 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 - -#elif defined(CONFIG_CMD_ONENAND) /* OneNAND */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_ONENAND_BASE 0x00000000 - -#define CONFIG_ENV_IS_IN_ONENAND 1 - -#else /* No flash */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_NOWHERE -#endif - -/* - * IDE - */ -#ifdef CONFIG_CMD_IDE -#define CONFIG_LBA48 -#undef CONFIG_IDE_LED -#undef CONFIG_IDE_RESET - -#define __io - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 - -#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x120 -#define CONFIG_SYS_ATA_REG_OFFSET 0x120 -#define CONFIG_SYS_ATA_ALT_OFFSET 0x120 - -#define CONFIG_SYS_ATA_STRIDE 2 -#endif - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPSR0_VAL 0x01308800 -#define CONFIG_SYS_GPSR1_VAL 0x00cf0000 -#define CONFIG_SYS_GPSR2_VAL 0x922ac000 -#define CONFIG_SYS_GPSR3_VAL 0x0161e800 - -#define CONFIG_SYS_GPCR0_VAL 0x00010000 -#define CONFIG_SYS_GPCR1_VAL 0x0 -#define CONFIG_SYS_GPCR2_VAL 0x0 -#define CONFIG_SYS_GPCR3_VAL 0x0 - -#define CONFIG_SYS_GPDR0_VAL 0xcbb18800 -#define CONFIG_SYS_GPDR1_VAL 0xfccfa981 -#define CONFIG_SYS_GPDR2_VAL 0x922affff -#define CONFIG_SYS_GPDR3_VAL 0x0161e904 - -#define CONFIG_SYS_GAFR0_L_VAL 0x00100000 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510 -#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa -#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x4109a401 -#define CONFIG_SYS_GAFR3_L_VAL 0x54010310 -#define CONFIG_SYS_GAFR3_U_VAL 0x00025401 - -#define CONFIG_SYS_PSSR_VAL 0x30 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x00500240 -#define CONFIG_SYS_CCCR 0x02000290 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x3ffc95f9 -#define CONFIG_SYS_MSC1_VAL 0x02ccf974 -#define CONFIG_SYS_MSC2_VAL 0x00000000 -#ifdef CONFIG_RAM_256M -#define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3 -#else -#define CONFIG_SYS_MDCNFG_VAL 0x88000ad3 -#endif -#define CONFIG_SYS_MDREFR_VAL 0x201fe01e -#define CONFIG_SYS_MDMRS_VAL 0x00000000 -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000001 -#define CONFIG_SYS_MCMEM0_VAL 0x00014307 -#define CONFIG_SYS_MCMEM1_VAL 0x00014307 -#define CONFIG_SYS_MCATT0_VAL 0x0001c787 -#define CONFIG_SYS_MCATT1_VAL 0x0001c787 -#define CONFIG_SYS_MCIO0_VAL 0x0001430f -#define CONFIG_SYS_MCIO1_VAL 0x0001430f - -/* - * LCD - */ -#ifdef CONFIG_LCD -#define CONFIG_VOIPAC_LCD -#endif - -/* - * USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "vpac270" -#define CONFIG_USB_STORAGE -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index f4e9cf20c5..6e8aec267d 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -37,6 +37,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/warp.h b/include/configs/warp.h index fa102bbae7..3e9a5a3ef3 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -98,6 +98,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_SPEED 100000 /* PMIC */ diff --git a/include/configs/wireless_space.h b/include/configs/wireless_space.h deleted file mode 100644 index 191ac1b73f..0000000000 --- a/include/configs/wireless_space.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (C) 2011 Albert ARIBAUD <albert.u.boot@aribaud.net> - * - * Based on the netspace_v2 code which is - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_WIRELESS_SPACE_H -#define _CONFIG_WIRELESS_SPACE_H - -/* - * Machine number definition - */ -#define MACH_TYPE_WIRELESS_SPACE 2500 /* is missing in mach-types.h */ -#define CONFIG_MACH_TYPE MACH_TYPE_WIRELESS_SPACE -#define CONFIG_IDENT_STRING " Wireless Space" - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -/* SoC name */ -#define CONFIG_KW88F6281 -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* no NOR or SPI flash */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_USB - -/* - * Core clock definition - */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ - -/* - * SDRAM configuration - */ -#define CONFIG_NR_DRAM_BANKS 1 - -/* - * Different SDRAM configuration and size for some of the boards derived - * from the Network Space v2 - */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* Remove or override few declarations from mv-common.h */ -#undef CONFIG_RBTREE -#undef CONFIG_SYS_IDE_MAXBUS -#undef CONFIG_SYS_IDE_MAXDEVICE -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable only egiga0... */ -#define PORT_SERIAL_CONTROL_VALUE 0x00A4260E /* ... tied to the switch... */ -#define CONFIG_PHY_BASE_ADR 0xa /* ... through a 'fake' PHY */ -#define CONFIG_MII -#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#define CONFIG_NETCONSOLE -#define CONFIG_MV88E61XX_SWITCH -#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE -#define CONFIG_MV88E61XX_CMD -#define CONFIG_CMD_TFTPPUT -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /* CONFIG_MVSATA_IDE */ - -/* - * Enable GPI0 support - */ -#define CONFIG_KIRKWOOD_GPIO - -/* - * Enable I2C support - */ -#ifdef CONFIG_CMD_I2C -/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ -#define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ -#endif /* CONFIG_CMD_I2C */ - -/* - * Partition support - */ -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION - -/* - * File systems support - */ -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT - -/* - * Use the HUSH parser - */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * Console configuration - */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -/* - * Enable device tree support - */ -#define CONFIG_OF_LIBFDT - -/* - * Environment variables configurations - */ - -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */ -#define CONFIG_ENV_SIZE 0x20000 /* 128KB */ -#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ - -/* - * Board-specific command to make using buttons etc easier - */ - -#define CONFIG_WIRELESS_SPACE_CMD - -/* - * Default environment variables - */ -#define CONFIG_PREBOOT - -#define CONFIG_BOOTARGS "console=ttyS0,115200" - -#define CONFIG_BOOTCOMMAND \ - "if run usbload || run diskload; then bootm; fi" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "bootfile=uImage\0" \ - "loadaddr=0x800000\0" \ - "autoload=no\0" \ - "netconsole=" \ - "set stdin $stdin,nc; " \ - "set stdout $stdout,nc; " \ - "set stderr $stderr,nc;\0" \ - "diskload=ide reset && " \ - "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ - "usbload=usb start && " \ - "fatload usb 0:1 $loadaddr /boot/$bootfile\0" \ - "preboot=" \ - "dhcp && run netconsole\0" - -#endif /* _CONFIG_WIRELESS_SPACE_H */ diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index 5d9f5297ce..fc4656567d 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -47,6 +47,8 @@ */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_MXC_SPI diff --git a/include/configs/x600.h b/include/configs/x600.h index 6a5738863a..73ba67c3e9 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -17,6 +17,7 @@ #define CONFIG_SPEAR600 /* SPEAr600 SoC */ #define CONFIG_X600 /* on X600 board */ #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_THUMB_BUILD #include <asm/arch/hardware.h> @@ -67,6 +68,8 @@ #define CONFIG_MTD_ECC_SOFT #define CONFIG_SYS_FSMC_NAND_8BIT #define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_ECC_BCH +#define CONFIG_BCH /* UBI/UBI config options */ #define CONFIG_MTD_DEVICE diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h deleted file mode 100644 index 8d19bffa02..0000000000 --- a/include/configs/xaeniax.h +++ /dev/null @@ -1,539 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> - * - * (C) Copyright 2004 - * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * Configuation settings for the xaeniax board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_CPU_PXA25X 1 /* This is an PXA255 CPU */ -#define CONFIG_XAENIAX 1 /* on a xaeniax board */ -#define CONFIG_SYS_TEXT_BASE 0x0 - -#define CONFIG_BOARD_LATE_INIT - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* - * select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */ -#define CONFIG_CONS_INDEX 4 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_DTT - - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.68.201 -#define CONFIG_SERVERIP 192.168.68.62 - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTCOMMAND "bootm 0x00100000" -#define CONFIG_BOOTARGS "console=ttyS1,115200" -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#endif - -/* - * Size of malloc() pool; this lives below the uppermost 128 KiB which are - * used for the RAM copy of the uboot code - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#undef CONFIG_SYS_PROMPT -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "u-boot$ " /* Monitor Command Prompt */ -#else -#define CONFIG_SYS_PROMPT "u-boot=> " /* Monitor Command Prompt */ -#endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ - -#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks (partition) of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x04000000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* FIXME */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector */ -#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* - * SMSC91C111 Network Card - */ -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */ -#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */ -#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ -#undef CONFIG_SHOW_ACTIVITY -#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ - -/* - * GPIO settings - */ - -/* - * GP05 == nUSBReset is 1 - * GP10 == CFReset is 1 - * GP13 == nCFDataEnable is 1 - * GP14 == nCFAddrEnable is 1 - * GP15 == nCS1 is 1 - * GP21 == ComBrdReset is 1 - * GP24 == SFRM is 1 - * GP25 == TXD is 1 - * GP31 == SYNC is 1 - * GP33 == nCS5 is 1 - * GP39 == FFTXD is 1 - * GP41 == RTS is 1 - * GP43 == BTTXD is 1 - * GP45 == BTRTS is 1 - * GP47 == TXD is 1 - * GP48 == nPOE is 1 - * GP49 == nPWE is 1 - * GP50 == nPIOR is 1 - * GP51 == nPIOW is 1 - * GP52 == nPCE[1] is 1 - * GP53 == nPCE[2] is 1 - * GP54 == nPSKTSEL is 1 - * GP55 == nPREG is 1 - * GP78 == nCS2 is 1 - * GP79 == nCS3 is 1 - * GP80 == nCS4 is 1 - * GP82 == NSSPSFRM is 1 - * GP83 == NSSPTXD is 1 - */ -#define CONFIG_SYS_GPSR0_VAL 0x8320E420 -#define CONFIG_SYS_GPSR1_VAL 0x00FFAA82 -#define CONFIG_SYS_GPSR2_VAL 0x000DC000 - -/* - * GP03 == LANReset is 0 - * GP06 == USBWakeUp is 0 - * GP11 == USBControl is 0 - * GP12 == Buzzer is 0 - * GP16 == PWM0 is 0 - * GP17 == PWM1 is 0 - * GP23 == SCLK is 0 - * GP30 == SDATA_OUT is 0 - * GP81 == NSSPCLK is 0 - */ -#define CONFIG_SYS_GPCR0_VAL 0x40C31848 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00020000 - -/* - * GP00 == CPUWakeUpUSB is input - * GP01 == GP reset is input - * GP02 == LANInterrupt is input - * GP03 == LANReset is output - * GP04 == USBInterrupt is input - * GP05 == nUSBReset is output - * GP06 == USBWakeUp is output - * GP07 == CFReady/nBusy is input - * GP08 == nCFCardDetect1 is input - * GP09 == nCFCardDetect2 is input - * GP10 == nCFReset is output - * GP11 == USBControl is output - * GP12 == Buzzer is output - * GP13 == CFDataEnable is output - * GP14 == CFAddressEnable is output - * GP15 == nCS1 is output - * GP16 == PWM0 is output - * GP17 == PWM1 is output - * GP18 == RDY is input - * GP19 == ReaderReady is input - * GP20 == ReaderReset is input - * GP21 == ComBrdReset is output - * GP23 == SCLK is output - * GP24 == SFRM is output - * GP25 == TXD is output - * GP26 == RXD is input - * GP27 == EXTCLK is input - * GP28 == BITCLK is output - * GP29 == SDATA_IN0 is input - * GP30 == SDATA_OUT is output - * GP31 == SYNC is output - * GP32 == SYSSCLK is output - * GP33 == nCS5 is output - * GP34 == FFRXD is input - * GP35 == CTS is input - * GP36 == DCD is input - * GP37 == DSR is input - * GP38 == RI is input - * GP39 == FFTXD is output - * GP40 == DTR is output - * GP41 == RTS is output - * GP42 == BTRXD is input - * GP43 == BTTXD is output - * GP44 == BTCTS is input - * GP45 == BTRTS is output - * GP46 == RXD is input - * GP47 == TXD is output - * GP48 == nPOE is output - * GP49 == nPWE is output - * GP50 == nPIOR is output - * GP51 == nPIOW is output - * GP52 == nPCE[1] is output - * GP53 == nPCE[2] is output - * GP54 == nPSKTSEL is output - * GP55 == nPREG is output - * GP56 == nPWAIT is input - * GP57 == nPIOS16 is input - * GP58 == LDD[0] is output - * GP59 == LDD[1] is output - * GP60 == LDD[2] is output - * GP61 == LDD[3] is output - * GP62 == LDD[4] is output - * GP63 == LDD[5] is output - * GP64 == LDD[6] is output - * GP65 == LDD[7] is output - * GP66 == LDD[8] is output - * GP67 == LDD[9] is output - * GP68 == LDD[10] is output - * GP69 == LDD[11] is output - * GP70 == LDD[12] is output - * GP71 == LDD[13] is output - * GP72 == LDD[14] is output - * GP73 == LDD[15] is output - * GP74 == LCD_FCLK is output - * GP75 == LCD_LCLK is output - * GP76 == LCD_PCLK is output - * GP77 == LCD_ACBIAS is output - * GP78 == nCS2 is output - * GP79 == nCS3 is output - * GP80 == nCS4 is output - * GP81 == NSSPCLK is output - * GP82 == NSSPSFRM is output - * GP83 == NSSPTXD is output - * GP84 == NSSPRXD is input - */ -#define CONFIG_SYS_GPDR0_VAL 0xD3E3FC68 -#define CONFIG_SYS_GPDR1_VAL 0xFCFFAB83 -#define CONFIG_SYS_GPDR2_VAL 0x000FFFFF - -/* - * GP01 == GP reset is AF01 - * GP15 == nCS1 is AF10 - * GP16 == PWM0 is AF10 - * GP17 == PWM1 is AF10 - * GP18 == RDY is AF01 - * GP23 == SCLK is AF10 - * GP24 == SFRM is AF10 - * GP25 == TXD is AF10 - * GP26 == RXD is AF01 - * GP27 == EXTCLK is AF01 - * GP28 == BITCLK is AF01 - * GP29 == SDATA_IN0 is AF10 - * GP30 == SDATA_OUT is AF01 - * GP31 == SYNC is AF01 - * GP32 == SYSCLK is AF01 - * GP33 == nCS5 is AF10 - * GP34 == FFRXD is AF01 - * GP35 == CTS is AF01 - * GP36 == DCD is AF01 - * GP37 == DSR is AF01 - * GP38 == RI is AF01 - * GP39 == FFTXD is AF10 - * GP40 == DTR is AF10 - * GP41 == RTS is AF10 - * GP42 == BTRXD is AF01 - * GP43 == BTTXD is AF10 - * GP44 == BTCTS is AF01 - * GP45 == BTRTS is AF10 - * GP46 == RXD is AF10 - * GP47 == TXD is AF01 - * GP48 == nPOE is AF10 - * GP49 == nPWE is AF10 - * GP50 == nPIOR is AF10 - * GP51 == nPIOW is AF10 - * GP52 == nPCE[1] is AF10 - * GP53 == nPCE[2] is AF10 - * GP54 == nPSKTSEL is AF10 - * GP55 == nPREG is AF10 - * GP56 == nPWAIT is AF01 - * GP57 == nPIOS16 is AF01 - * GP58 == LDD[0] is AF10 - * GP59 == LDD[1] is AF10 - * GP60 == LDD[2] is AF10 - * GP61 == LDD[3] is AF10 - * GP62 == LDD[4] is AF10 - * GP63 == LDD[5] is AF10 - * GP64 == LDD[6] is AF10 - * GP65 == LDD[7] is AF10 - * GP66 == LDD[8] is AF10 - * GP67 == LDD[9] is AF10 - * GP68 == LDD[10] is AF10 - * GP69 == LDD[11] is AF10 - * GP70 == LDD[12] is AF10 - * GP71 == LDD[13] is AF10 - * GP72 == LDD[14] is AF10 - * GP73 == LDD[15] is AF10 - * GP74 == LCD_FCLK is AF10 - * GP75 == LCD_LCLK is AF10 - * GP76 == LCD_PCLK is AF10 - * GP77 == LCD_ACBIAS is AF10 - * GP78 == nCS2 is AF10 - * GP79 == nCS3 is AF10 - * GP80 == nCS4 is AF10 - * GP81 == NSSPCLK is AF01 - * GP82 == NSSPSFRM is AF01 - * GP83 == NSSPTXD is AF01 - * GP84 == NSSPRXD is AF10 - */ -#define CONFIG_SYS_GAFR0_L_VAL 0x80000004 -#define CONFIG_SYS_GAFR0_U_VAL 0x595A801A -#define CONFIG_SYS_GAFR1_L_VAL 0x699A9559 -#define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA -#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA -#define CONFIG_SYS_GAFR2_U_VAL 0x00000256 - -/* - * clock settings - */ -/* RDH = 1 - * PH = 0 - * VFS = 0 - * BFS = 0 - * SSS = 0 - */ -#define CONFIG_SYS_PSSR_VAL 0x00000030 - -#define CONFIG_SYS_CKEN 0x00000080 /* */ -#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */ -#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 - - -/* - * Memory settings - * - * This is the configuration for nCS0/1 -> flash banks - * configuration for nCS1 : - * [31] 0 - - * [30:28] 000 - - * [27:24] 0000 - - * [23:20] 0000 - - * [19] 0 - - * [18:16] 000 - - * configuration for nCS0: - * [15] 0 - Slower Device - * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns - * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns - * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?) - * [03] 0 - 32 Bit bus width - * [02:00] 010 - burst OF 4 ROM or FLASH -*/ -#define CONFIG_SYS_MSC0_VAL 0x000023D2 - -/* This is the configuration for nCS2/3 -> USB controller, LAN - * configuration for nCS3: LAN - * [31] 0 - Slower Device - * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns - * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns - * [19] 0 - 32 Bit bus width - * [18:16] 100 - variable latency I/O - * configuration for nCS2: USB - * [15] 1 - Faster Device - * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns - * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns - * [03] 1 - 16 Bit bus width - * [02:00] 100 - variable latency I/O - */ -#define CONFIG_SYS_MSC1_VAL 0x1224A26C - -/* This is the configuration for nCS4/5 -> LAN - * configuration for nCS5: - * [31] 0 - - * [30:28] 000 - - * [27:24] 0000 - - * [23:20] 0000 - - * [19] 0 - - * [18:16] 000 - - * configuration for nCS4: LAN - * [15] 1 - Faster Device - * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns - * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns - * [03] 0 - 32 Bit bus width - * [02:00] 100 - variable latency I/O - */ -#define CONFIG_SYS_MSC2_VAL 0x00001224 - -/* MDCNFG: SDRAM Configuration Register - * - * [31:29] 000 - reserved - * [28] 0 - no SA1111 compatiblity mode - * [27] 0 - latch return data with return clock - * [26] 0 - alternate addressing for pair 2/3 - * [25:24] 00 - timings - * [23] 0 - internal banks in lower partition 2/3 (not used) - * [22:21] 00 - row address bits for partition 2/3 (not used) - * [20:19] 00 - column address bits for partition 2/3 (not used) - * [18] 0 - SDRAM partition 2/3 width is 32 bit - * [17] 0 - SDRAM partition 3 disabled - * [16] 0 - SDRAM partition 2 disabled - * [15:13] 000 - reserved - * [12] 0 - no SA1111 compatiblity mode - * [11] 1 - latch return data with return clock - * [10] 0 - no alternate addressing for pair 0/1 - * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk - * [7] 1 - 4 internal banks in lower partition pair - * [06:05] 10 - 13 row address bits for partition 0/1 - * [04:03] 01 - 9 column address bits for partition 0/1 - * [02] 0 - SDRAM partition 0/1 width is 32 bit - * [01] 0 - disable SDRAM partition 1 - * [00] 1 - enable SDRAM partition 0 - */ -/* use the configuration above but disable partition 0 */ -#define CONFIG_SYS_MDCNFG_VAL 0x00000AC9 - -/* MDREFR: SDRAM Refresh Control Register - * - * [32:26] 0 - reserved - * [25] 0 - K2FREE: not free running - * [24] 0 - K1FREE: not free running - * [23] 0 - K0FREE: not free running - * [22] 0 - SLFRSH: self refresh disabled - * [21] 0 - reserved - * [20] 1 - APD: auto power down - * [19] 0 - K2DB2: SDCLK2 is MemClk - * [18] 0 - K2RUN: disable SDCLK2 - * [17] 0 - K1DB2: SDCLK1 is MemClk - * [16] 1 - K1RUN: enable SDCLK1 - * [15] 1 - E1PIN: SDRAM clock enable - * [14] 0 - K0DB2: SDCLK0 is MemClk - * [13] 0 - K0RUN: disable SDCLK0 - * [12] 0 - E0PIN: disable SDCKE0 - * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 - */ -#define CONFIG_SYS_MDREFR_VAL 0x00138018 /* mh: was 0x00118018 */ - -/* MDMRS: Mode Register Set Configuration Register - * - * [31] 0 - reserved - * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) - * [22:20] 011 - MDCL2: SDRAM2/3 Cas Latency. (not used) - * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) - * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) - * [15] 0 - reserved - * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. - * [06:04] 011 - MDCL0: SDRAM0/1 Cas Latency. - * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. - * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. - */ -#define CONFIG_SYS_MDMRS_VAL 0x00320032 - -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00010504 -#define CONFIG_SYS_MCMEM1_VAL 0x00010504 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00010504 -#define CONFIG_SYS_MCIO0_VAL 0x00004715 -#define CONFIG_SYS_MCIO1_VAL 0x00004715 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 669aa53c91..b5d1126d59 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -138,7 +138,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */ #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */ #define CONFIG_SYS_NAND_ACTL_DELAY 25 -#define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_JFFS2_NAND /* diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 58ace2cf48..0d2423499d 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -131,7 +131,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ CONFIG_SYS_NAND_BASE2} #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */ #define CONFIG_NAND_FSL_ELBC /* diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 765aaadf10..f30d1996c0 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -122,7 +122,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ CONFIG_SYS_NAND_BASE2} #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */ #define CONFIG_NAND_FSL_ELBC /* diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h deleted file mode 100644 index 0199190eb8..0000000000 --- a/include/configs/zipitz2.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Aeronix Zipit Z2 configuration file - * - * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ -#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */ -#define CONFIG_SYS_TEXT_BASE 0x0 - -#undef CONFIG_BOARD_LATE_INIT -#undef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_PREBOOT - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x40000 -#define CONFIG_ENV_SIZE 0x20000 - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -#define CONFIG_SYS_MALLOC_LEN (128*1024) -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_BOOTCOMMAND \ - "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\ - "then " \ - "source 0xa0000000; " \ - "else " \ - "bootm 0x60000; " \ - "fi; " -#define CONFIG_BOOTARGS \ - "console=tty0 console=ttyS2,115200 fbcon=rotate:3" -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_TEXT_BASE 0x0 -#define CONFIG_LZMA /* LZMA compression support */ - -/* - * Serial Console Configuration - * STUART - the lower serial port on Colibri board - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_STUART 1 -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* - * Bootloader Components Configuration - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MMC -#define CONFIG_CMD_SPI - -/* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_DOS_PARTITION -#endif - -/* - * SPI and LCD - */ -#ifdef CONFIG_CMD_SPI -#define CONFIG_SOFT_SPI -#define CONFIG_LCD -#define CONFIG_PXA_LCD -#define CONFIG_LMS283GF05 -#define CONFIG_VIDEO_LOGO -#define CONFIG_CMD_BMP -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) - -#define SPI_DELAY udelay(10) -#define SPI_SDA(val) zipitz2_spi_sda(val) -#define SPI_SCL(val) zipitz2_spi_scl(val) -#define SPI_READ zipitz2_spi_read() -#ifndef __ASSEMBLY__ -void zipitz2_spi_sda(int); -void zipitz2_spi_scl(int); -unsigned char zipitz2_spi_read(void); -#endif -#endif - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * HUSH Shell Configuration - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ - -/* - * SRAM Map - */ -#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */ -#define PHYS_SRAM_SIZE 0x00040000 /* 256k */ - -/* - * DRAM Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048) - -/* - * NOR FLASH - */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ -#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 -#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_PROTECTION - -/* - * GPIO settings - */ -#define CONFIG_SYS_GAFR0_L_VAL 0x02000140 -#define CONFIG_SYS_GAFR0_U_VAL 0x59188000 -#define CONFIG_SYS_GAFR1_L_VAL 0x63900002 -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950 -#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x29000308 -#define CONFIG_SYS_GAFR3_L_VAL 0x54000000 -#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5 -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000020 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -#define CONFIG_SYS_GPCR3_VAL 0x00000000 -#define CONFIG_SYS_GPDR0_VAL 0xdafcee00 -#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab -#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff -#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a -#define CONFIG_SYS_GPSR0_VAL 0x06080400 -#define CONFIG_SYS_GPSR1_VAL 0x007f0000 -#define CONFIG_SYS_GPSR2_VAL 0x032a0000 -#define CONFIG_SYS_GPSR3_VAL 0x00000180 - -#define CONFIG_SYS_PSSR_VAL 0x30 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x00511220 -#define CONFIG_SYS_CCCR 0x00000190 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8 -#define CONFIG_SYS_MSC1_VAL 0x0000ccd1 -#define CONFIG_SYS_MSC2_VAL 0x0000b884 -#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9 -#define CONFIG_SYS_MDREFR_VAL 0x2011a01e -#define CONFIG_SYS_MDMRS_VAL 0x00000000 -#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000001 -#define CONFIG_SYS_MCMEM0_VAL 0x00014307 -#define CONFIG_SYS_MCMEM1_VAL 0x00014307 -#define CONFIG_SYS_MCATT0_VAL 0x0001c787 -#define CONFIG_SYS_MCATT1_VAL 0x0001c787 -#define CONFIG_SYS_MCIO0_VAL 0x0001430f -#define CONFIG_SYS_MCIO1_VAL 0x0001430f - -#endif /* __CONFIG_H */ diff --git a/include/dm/device.h b/include/dm/device.h index a239be6469..85196124b4 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -485,6 +485,17 @@ bool device_is_last_sibling(struct udevice *dev); */ int device_set_name(struct udevice *dev, const char *name); +/** + * device_is_on_pci_bus - Test if a device is on a PCI bus + * + * @dev: device to test + * @return: true if it is on a PCI bus, false otherwise + */ +static inline bool device_is_on_pci_bus(struct udevice *dev) +{ + return device_get_uclass_id(dev->parent) == UCLASS_PCI; +} + /* device resource management */ typedef void (*dr_release_t)(struct udevice *dev, void *res); typedef int (*dr_match_t)(struct udevice *dev, void *res, void *match_data); diff --git a/include/env_flags.h b/include/env_flags.h index 2d2de88fc0..8823fb9602 100644 --- a/include/env_flags.h +++ b/include/env_flags.h @@ -109,6 +109,13 @@ enum env_flags_varaccess env_flags_parse_varaccess(const char *flags); */ enum env_flags_varaccess env_flags_parse_varaccess_from_binflags(int binflags); +#ifdef CONFIG_CMD_NET +/* + * Check if a string has the format of an Ethernet MAC address + */ +int eth_validate_ethaddr_str(const char *addr); +#endif + #ifdef USE_HOSTCC /* * Look up the type of a variable directly from the .flags var. diff --git a/include/ethsw.h b/include/ethsw.h new file mode 100644 index 0000000000..2d3c12a39e --- /dev/null +++ b/include/ethsw.h @@ -0,0 +1,95 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Ethernet Switch commands + */ + +#ifndef _CMD_ETHSW_H_ +#define _CMD_ETHSW_H_ + +#define ETHSW_MAX_CMD_PARAMS 20 +#define ETHSW_CMD_PORT_ALL -1 +#define ETHSW_CMD_VLAN_ALL -1 + +/* IDs used to track keywords in a command */ +enum ethsw_keyword_id { + ethsw_id_key_end = -1, + ethsw_id_help, + ethsw_id_show, + ethsw_id_port, + ethsw_id_enable, + ethsw_id_disable, + ethsw_id_statistics, + ethsw_id_clear, + ethsw_id_learning, + ethsw_id_auto, + ethsw_id_vlan, + ethsw_id_fdb, + ethsw_id_add, + ethsw_id_del, + ethsw_id_flush, + ethsw_id_pvid, + ethsw_id_untagged, + ethsw_id_all, + ethsw_id_none, + ethsw_id_egress, + ethsw_id_tag, + ethsw_id_classified, + ethsw_id_shared, + ethsw_id_private, + ethsw_id_ingress, + ethsw_id_filtering, + ethsw_id_count, /* keep last */ +}; + +enum ethsw_keyword_opt_id { + ethsw_id_port_no = ethsw_id_count + 1, + ethsw_id_vlan_no, + ethsw_id_pvid_no, + ethsw_id_add_del_no, + ethsw_id_add_del_mac, + ethsw_id_count_all, /* keep last */ +}; + +struct ethsw_command_def { + int cmd_to_keywords[ETHSW_MAX_CMD_PARAMS]; + int cmd_keywords_nr; + int port; + int vid; + uchar ethaddr[6]; + int (*cmd_function)(struct ethsw_command_def *parsed_cmd); +}; + +/* Structure to be created and initialized by an Ethernet Switch driver */ +struct ethsw_command_func { + const char *ethsw_name; + int (*port_enable)(struct ethsw_command_def *parsed_cmd); + int (*port_disable)(struct ethsw_command_def *parsed_cmd); + int (*port_show)(struct ethsw_command_def *parsed_cmd); + int (*port_stats)(struct ethsw_command_def *parsed_cmd); + int (*port_stats_clear)(struct ethsw_command_def *parsed_cmd); + int (*port_learn)(struct ethsw_command_def *parsed_cmd); + int (*port_learn_show)(struct ethsw_command_def *parsed_cmd); + int (*fdb_show)(struct ethsw_command_def *parsed_cmd); + int (*fdb_flush)(struct ethsw_command_def *parsed_cmd); + int (*fdb_entry_add)(struct ethsw_command_def *parsed_cmd); + int (*fdb_entry_del)(struct ethsw_command_def *parsed_cmd); + int (*pvid_show)(struct ethsw_command_def *parsed_cmd); + int (*pvid_set)(struct ethsw_command_def *parsed_cmd); + int (*vlan_show)(struct ethsw_command_def *parsed_cmd); + int (*vlan_set)(struct ethsw_command_def *parsed_cmd); + int (*port_untag_show)(struct ethsw_command_def *parsed_cmd); + int (*port_untag_set)(struct ethsw_command_def *parsed_cmd); + int (*port_egr_vlan_show)(struct ethsw_command_def *parsed_cmd); + int (*port_egr_vlan_set)(struct ethsw_command_def *parsed_cmd); + int (*vlan_learn_show)(struct ethsw_command_def *parsed_cmd); + int (*vlan_learn_set)(struct ethsw_command_def *parsed_cmd); + int (*port_ingr_filt_show)(struct ethsw_command_def *parsed_cmd); + int (*port_ingr_filt_set)(struct ethsw_command_def *parsed_cmd); +}; + +int ethsw_define_functions(const struct ethsw_command_func *cmd_func); + +#endif /* _CMD_ETHSW_H_ */ diff --git a/include/fdtdec.h b/include/fdtdec.h index a422ecedb8..2de6dda04c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -295,10 +295,90 @@ int fdtdec_next_compatible(const void *blob, int node, int fdtdec_next_compatible_subnode(const void *blob, int node, enum fdt_compat_id id, int *depthp); -/** - * Look up an address property in a node and return it as an address. - * The property must hold either one address with no trailing data or - * one address with a length. This is only tested on 32-bit machines. +/* + * Look up an address property in a node and return the parsed address, and + * optionally the parsed size. + * + * This variant assumes a known and fixed number of cells are used to + * represent the address and size. + * + * You probably don't want to use this function directly except to parse + * non-standard properties, and never to parse the "reg" property. Instead, + * use one of the "auto" variants below, which automatically honor the + * #address-cells and #size-cells properties in the parent node. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param index which address to retrieve from a list of addresses. Often 0. + * @param na the number of cells used to represent an address + * @param ns the number of cells used to represent a size + * @param sizep a pointer to store the size into. Use NULL if not required + * @return address, if found, or FDT_ADDR_T_NONE if not + */ +fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node, + const char *prop_name, int index, int na, int ns, + fdt_size_t *sizep); + +/* + * Look up an address property in a node and return the parsed address, and + * optionally the parsed size. + * + * This variant automatically determines the number of cells used to represent + * the address and size by parsing the provided parent node's #address-cells + * and #size-cells properties. + * + * @param blob FDT blob + * @param parent parent node of @node + * @param node node to examine + * @param prop_name name of property to find + * @param index which address to retrieve from a list of addresses. Often 0. + * @param sizep a pointer to store the size into. Use NULL if not required + * @return address, if found, or FDT_ADDR_T_NONE if not + */ +fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent, + int node, const char *prop_name, int index, fdt_size_t *sizep); + +/* + * Look up an address property in a node and return the parsed address, and + * optionally the parsed size. + * + * This variant automatically determines the number of cells used to represent + * the address and size by parsing the parent node's #address-cells + * and #size-cells properties. The parent node is automatically found. + * + * The automatic parent lookup implemented by this function is slow. + * Consequently, fdtdec_get_addr_size_auto_parent() should be used where + * possible. + * + * @param blob FDT blob + * @param parent parent node of @node + * @param node node to examine + * @param prop_name name of property to find + * @param index which address to retrieve from a list of addresses. Often 0. + * @param sizep a pointer to store the size into. Use NULL if not required + * @return address, if found, or FDT_ADDR_T_NONE if not + */ +fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node, + const char *prop_name, int index, fdt_size_t *sizep); + +/* + * Look up an address property in a node and return the parsed address. + * + * This variant hard-codes the number of cells used to represent the address + * and size based on sizeof(fdt_addr_t) and sizeof(fdt_size_t). It also + * always returns the first address value in the property (index 0). + * + * Use of this function is not recommended due to the hard-coding of cell + * counts. There is no programmatic validation that these hard-coded values + * actually match the device tree content in any way at all. This assumption + * can be satisfied by manually ensuring CONFIG_PHYS_64BIT is appropriately + * set in the U-Boot build and exercising strict control over DT content to + * ensure use of matching #address-cells/#size-cells properties. However, this + * approach is error-prone; those familiar with DT will not expect the + * assumption to exist, and could easily invalidate it. If the assumption is + * invalidated, this function will not report the issue, and debugging will + * be required. Instead, use fdtdec_get_addr_size_auto_parent(). * * @param blob FDT blob * @param node node to examine @@ -308,14 +388,29 @@ int fdtdec_next_compatible_subnode(const void *blob, int node, fdt_addr_t fdtdec_get_addr(const void *blob, int node, const char *prop_name); -/** - * Look up an address property in a node and return it as an address. - * The property must hold one address with a length. This is only tested - * on 32-bit machines. +/* + * Look up an address property in a node and return the parsed address, and + * optionally the parsed size. + * + * This variant hard-codes the number of cells used to represent the address + * and size based on sizeof(fdt_addr_t) and sizeof(fdt_size_t). It also + * always returns the first address value in the property (index 0). + * + * Use of this function is not recommended due to the hard-coding of cell + * counts. There is no programmatic validation that these hard-coded values + * actually match the device tree content in any way at all. This assumption + * can be satisfied by manually ensuring CONFIG_PHYS_64BIT is appropriately + * set in the U-Boot build and exercising strict control over DT content to + * ensure use of matching #address-cells/#size-cells properties. However, this + * approach is error-prone; those familiar with DT will not expect the + * assumption to exist, and could easily invalidate it. If the assumption is + * invalidated, this function will not report the issue, and debugging will + * be required. Instead, use fdtdec_get_addr_size_auto_parent(). * * @param blob FDT blob * @param node node to examine * @param prop_name name of property to find + * @param sizep a pointer to store the size into. Use NULL if not required * @return address, if found, or FDT_ADDR_T_NONE if not */ fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index 9106f25f68..9517a4a7b5 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -12,7 +12,6 @@ #define MC_CCSR_BASE_ADDR \ ((struct mc_ccsr_registers __iomem *)0x8340000) -#define BIT(x) (1 << (x)) #define GCR1_P1_STOP BIT(31) #define GCR1_P2_STOP BIT(30) #define GCR1_P1_DE_RST BIT(23) diff --git a/include/fsl_wdog.h b/include/fsl_wdog.h new file mode 100644 index 0000000000..d15a70cedb --- /dev/null +++ b/include/fsl_wdog.h @@ -0,0 +1,18 @@ +/* + * (C) Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +struct watchdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ +}; + +#define WCR_WDZST 0x01 +#define WCR_WDBG 0x02 +#define WCR_WDE 0x04 +#define WCR_WDT 0x08 +#define WCR_SRS 0x10 +#define SET_WCR_WT(x) (x << 8) diff --git a/include/image.h b/include/image.h index 8a864aeb22..08ae24a86b 100644 --- a/include/image.h +++ b/include/image.h @@ -259,6 +259,7 @@ struct lmb; #define IH_COMP_BZIP2 2 /* bzip2 Compression Used */ #define IH_COMP_LZMA 3 /* lzma Compression Used */ #define IH_COMP_LZO 4 /* lzo Compression Used */ +#define IH_COMP_LZ4 5 /* lz4 Compression Used */ #define IH_MAGIC 0x27051956 /* Image Magic Number */ #define IH_NMLEN 32 /* Image Name Length */ diff --git a/include/linux/bitops.h b/include/linux/bitops.h index e724310298..7d30ace41f 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -3,6 +3,8 @@ #include <asm/types.h> +#define BIT(nr) (1UL << (nr)) + /* * ffs: find first bit set. This is defined the same way as * the libc and compiler builtin ffs routines, therefore diff --git a/include/memalign.h b/include/memalign.h new file mode 100644 index 0000000000..a960039083 --- /dev/null +++ b/include/memalign.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ALIGNMEM_H +#define __ALIGNMEM_H + +/* + * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It + * is used to align DMA buffers. + */ +#ifndef __ASSEMBLY__ +#include <asm/cache.h> +#include <malloc.h> + +/* + * The ALLOC_CACHE_ALIGN_BUFFER macro is used to allocate a buffer on the + * stack that meets the minimum architecture alignment requirements for DMA. + * Such a buffer is useful for DMA operations where flushing and invalidating + * the cache before and after a read and/or write operation is required for + * correct operations. + * + * When called the macro creates an array on the stack that is sized such + * that: + * + * 1) The beginning of the array can be advanced enough to be aligned. + * + * 2) The size of the aligned portion of the array is a multiple of the minimum + * architecture alignment required for DMA. + * + * 3) The aligned portion contains enough space for the original number of + * elements requested. + * + * The macro then creates a pointer to the aligned portion of this array and + * assigns to the pointer the address of the first element in the aligned + * portion of the array. + * + * Calling the macro as: + * + * ALLOC_CACHE_ALIGN_BUFFER(uint32_t, buffer, 1024); + * + * Will result in something similar to saying: + * + * uint32_t buffer[1024]; + * + * The following differences exist: + * + * 1) The resulting buffer is guaranteed to be aligned to the value of + * ARCH_DMA_MINALIGN. + * + * 2) The buffer variable created by the macro is a pointer to the specified + * type, and NOT an array of the specified type. This can be very important + * if you want the address of the buffer, which you probably do, to pass it + * to the DMA hardware. The value of &buffer is different in the two cases. + * In the macro case it will be the address of the pointer, not the address + * of the space reserved for the buffer. However, in the second case it + * would be the address of the buffer. So if you are replacing hard coded + * stack buffers with this macro you need to make sure you remove the & from + * the locations where you are taking the address of the buffer. + * + * Note that the size parameter is the number of array elements to allocate, + * not the number of bytes. + * + * This macro can not be used outside of function scope, or for the creation + * of a function scoped static buffer. It can not be used to create a cache + * line aligned global buffer. + */ +#define PAD_COUNT(s, pad) (((s) - 1) / (pad) + 1) +#define PAD_SIZE(s, pad) (PAD_COUNT(s, pad) * pad) +#define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad) \ + char __##name[ROUND(PAD_SIZE((size) * sizeof(type), pad), align) \ + + (align - 1)]; \ + \ + type *name = (type *)ALIGN((uintptr_t)__##name, align) +#define ALLOC_ALIGN_BUFFER(type, name, size, align) \ + ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, 1) +#define ALLOC_CACHE_ALIGN_BUFFER_PAD(type, name, size, pad) \ + ALLOC_ALIGN_BUFFER_PAD(type, name, size, ARCH_DMA_MINALIGN, pad) +#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \ + ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) + +/* + * DEFINE_CACHE_ALIGN_BUFFER() is similar to ALLOC_CACHE_ALIGN_BUFFER, but it's + * purpose is to allow allocating aligned buffers outside of function scope. + * Usage of this macro shall be avoided or used with extreme care! + */ +#define DEFINE_ALIGN_BUFFER(type, name, size, align) \ + static char __##name[ALIGN(size * sizeof(type), align)] \ + __aligned(align); \ + \ + static type *name = (type *)__##name +#define DEFINE_CACHE_ALIGN_BUFFER(type, name, size) \ + DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) + +/** + * malloc_cache_aligned() - allocate a memory region aligned to cache line size + * + * This allocates memory at a cache-line boundary. The amount allocated may + * be larger than requested as it is rounded up to the nearest multiple of the + * cache-line size. This ensured that subsequent cache operations on this + * memory (flush, invalidate) will not affect subsequently allocated regions. + * + * @size: Minimum number of bytes to allocate + * + * @return pointer to new memory region, or NULL if there is no more memory + * available. + */ +static inline void *malloc_cache_aligned(size_t size) +{ + return memalign(ARCH_DMA_MINALIGN, ALIGN(size, ARCH_DMA_MINALIGN)); +} +#endif + +#endif /* __ALIGNMEM_H */ diff --git a/include/net.h b/include/net.h index f1671e38de..3a787cc4e9 100644 --- a/include/net.h +++ b/include/net.h @@ -149,7 +149,9 @@ struct udevice *eth_get_dev(void); /* get the current device */ */ struct udevice *eth_get_dev_by_name(const char *devname); unsigned char *eth_get_ethaddr(void); /* get the current device MAC */ + /* Used only when NetConsole is enabled */ +int eth_is_active(struct udevice *dev); /* Test device for active state */ int eth_init_state_only(void); /* Set active state */ void eth_halt_state_only(void); /* Set passive state */ #endif @@ -195,6 +197,8 @@ static inline unsigned char *eth_get_ethaddr(void) return NULL; } +/* Used only when NetConsole is enabled */ +int eth_is_active(struct eth_device *dev); /* Test device for active state */ /* Set active state */ static inline __attribute__((always_inline)) int eth_init_state_only(void) { diff --git a/include/nomadik.h b/include/nomadik.h deleted file mode 100644 index ea65b2d828..0000000000 --- a/include/nomadik.h +++ /dev/null @@ -1,40 +0,0 @@ -/* Collection of constants used to access Nomadik registers */ - -#ifndef __NOMADIK_H__ -#define __NOMADIK_H__ - -/* Base addresses of our peripherals */ -#define NOMADIK_CLCDC_BASE 0x10120000 /* CLCD Controller */ -#define NOMADIK_SRC_BASE 0x101E0000 /* System and Reset Cnt */ -#define NOMADIK_PMU_BASE 0x101E9000 /* Power Management Unit */ -#define NOMADIK_MPMC_BASE 0x10110000 /* SDRAM Controller */ -#define NOMADIK_FSMC_BASE 0x10100000 /* FSMC Controller */ -#define NOMADIK_1NAND_BASE 0x30000000 -#define NOMADIK_GPIO0_BASE 0x101E4000 -#define NOMADIK_GPIO1_BASE 0x101E5000 -#define NOMADIK_GPIO2_BASE 0x101E6000 -#define NOMADIK_GPIO3_BASE 0x101E7000 -#define NOMADIK_CPLD_BASE 0x36000000 -#define NOMADIK_UART0_BASE 0x101FD000 -#define NOMADIK_UART1_BASE 0x101FB000 -#define NOMADIK_UART2_BASE 0x101F2000 - -#define NOMADIK_I2C1_BASE 0x101F7000 /* I2C1 interface */ -#define NOMADIK_I2C0_BASE 0x101F8000 /* I2C0 interface */ - -#define NOMADIK_RTC_BASE 0x101E8000 -#define NOMADIK_ETH0_BASE 0x36800300 -#define NOMADIK_CPLD_UART_BASE 0x36480000 - -/* Chip select registers ("Flexible Static Memory Controller") */ - -#define REG_FSMC_BCR0 (NOMADIK_FSMC_BASE + 0x00) -#define REG_FSMC_BTR0 (NOMADIK_FSMC_BASE + 0x04) -#define REG_FSMC_BCR1 (NOMADIK_FSMC_BASE + 0x08) -#define REG_FSMC_BTR1 (NOMADIK_FSMC_BASE + 0x0c) -#define REG_FSMC_PCR0 (NOMADIK_FSMC_BASE + 0x40) -#define REG_FSMC_PMEM0 (NOMADIK_FSMC_BASE + 0x48) -#define REG_FSMC_PATT0 (NOMADIK_FSMC_BASE + 0x4c) -#define REG_FSMC_ECCR0 (NOMADIK_FSMC_BASE + 0x54) - -#endif /* __NOMADIK_H__ */ diff --git a/include/vsc9953.h b/include/vsc9953.h index 3d11b87a1f..cd5cfc76b0 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -1,14 +1,9 @@ /* - * vsc9953.h + * Copyright 2013, 2015 Freescale Semiconductor, Inc. * - * Driver for the Vitesse VSC9953 L2 Switch - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * Copyright 2013 Freescale Semiconductor, Inc. + * SPDX-License-Identifier: GPL-2.0+ * + * Driver for the Vitesse VSC9953 L2 Switch */ #ifndef _VSC9953_H_ @@ -17,11 +12,11 @@ #include <config.h> #include <miiphy.h> #include <asm/types.h> -#include <malloc.h> #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) #define VSC9953_SYS_OFFSET 0x010000 +#define VSC9953_REW_OFFSET 0x030000 #define VSC9953_DEV_GMII_OFFSET 0x100000 #define VSC9953_QSYS_OFFSET 0x200000 #define VSC9953_ANA_OFFSET 0x280000 @@ -33,29 +28,131 @@ #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 #define VSC9953_PHY_REGS_OFFST 0x0000AC -#define CONFIG_VSC9953_SOFT_SWC_RST_ENA 0x00000001 -#define CONFIG_VSC9953_CORE_ENABLE 0x80 -#define CONFIG_VSC9953_MEM_ENABLE 0x40 -#define CONFIG_VSC9953_MEM_INIT 0x20 - -#define CONFIG_VSC9953_PORT_ENA 0x00003a00 -#define CONFIG_VSC9953_MAC_ENA_CFG 0x00000011 -#define CONFIG_VSC9953_MAC_MODE_CFG 0x00000011 -#define CONFIG_VSC9953_MAC_IFG_CFG 0x00000515 -#define CONFIG_VSC9953_MAC_HDX_CFG 0x00001043 -#define CONFIG_VSC9953_CLOCK_CFG 0x00000001 -#define CONFIG_VSC9953_CLOCK_CFG_1000M 0x00000001 -#define CONFIG_VSC9953_PFC_FC 0x00000001 -#define CONFIG_VSC9953_PFC_FC_QSGMII 0x00000000 -#define CONFIG_VSC9953_MAC_FC_CFG 0x04700000 -#define CONFIG_VSC9953_MAC_FC_CFG_QSGMII 0x00700000 -#define CONFIG_VSC9953_PAUSE_CFG 0x001ffffe -#define CONFIG_VSC9953_TOT_TAIL_DROP_LVL 0x000003ff -#define CONFIG_VSC9953_FRONT_PORT_MODE 0x00000000 -#define CONFIG_VSC9953_MAC_MAX_LEN 0x000005ee - -#define CONFIG_VSC9953_VCAP_MV_CFG 0x0000ffff -#define CONFIG_VSC9953_VCAP_UPDATE_CTRL 0x01000004 +/* Macros for vsc9953_chip_regs.soft_rst register */ +#define VSC9953_SOFT_SWC_RST_ENA 0x00000001 + +/* Macros for vsc9953_sys_sys.reset_cfg register */ +#define VSC9953_CORE_ENABLE 0x80 +#define VSC9953_MEM_ENABLE 0x40 +#define VSC9953_MEM_INIT 0x20 + +/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */ +#define VSC9953_MAC_ENA_CFG 0x00000011 + +/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */ +#define VSC9953_MAC_MODE_CFG 0x00000011 + +/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */ +#define VSC9953_MAC_IFG_CFG 0x00000515 + +/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */ +#define VSC9953_MAC_HDX_CFG 0x00001043 + +/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */ +#define VSC9953_MAC_MAX_LEN 0x000005ee + +/* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */ +#define VSC9953_CLOCK_CFG 0x00000001 +#define VSC9953_CLOCK_CFG_1000M 0x00000001 + +/* Macros for vsc9953_sys_sys.front_port_mode register */ +#define VSC9953_FRONT_PORT_MODE 0x00000000 + +/* Macros for vsc9953_ana_pfc.pfc_cfg register */ +#define VSC9953_PFC_FC 0x00000001 +#define VSC9953_PFC_FC_QSGMII 0x00000000 + +/* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */ +#define VSC9953_MAC_FC_CFG 0x04700000 +#define VSC9953_MAC_FC_CFG_QSGMII 0x00700000 + +/* Macros for vsc9953_sys_pause_cfg.pause_cfg register */ +#define VSC9953_PAUSE_CFG 0x001ffffe + +/* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */ +#define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff + +/* Macros for vsc9953_sys_sys.stat_cfg register */ +#define VSC9953_STAT_CLEAR_RX 0x00000400 +#define VSC9953_STAT_CLEAR_TX 0x00000800 +#define VSC9953_STAT_CLEAR_DR 0x00001000 + +/* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */ +#define VSC9953_VCAP_MV_CFG 0x0000ffff +#define VSC9953_VCAP_UPDATE_CTRL 0x01000004 + +/* Macros for register vsc9953_ana_ana_tables.mac_access register */ +#define VSC9953_MAC_CMD_IDLE 0x00000000 +#define VSC9953_MAC_CMD_LEARN 0x00000001 +#define VSC9953_MAC_CMD_FORGET 0x00000002 +#define VSC9953_MAC_CMD_AGE 0x00000003 +#define VSC9953_MAC_CMD_NEXT 0x00000004 +#define VSC9953_MAC_CMD_READ 0x00000006 +#define VSC9953_MAC_CMD_WRITE 0x00000007 +#define VSC9953_MAC_CMD_MASK 0x00000007 +#define VSC9953_MAC_CMD_VALID 0x00000800 +#define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000 +#define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200 +#define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400 +#define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600 +#define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600 +#define VSC9953_MAC_DESTIDX_MASK 0x000001f8 +#define VSC9953_MAC_VID_MASK 0x1fff0000 +#define VSC9953_MAC_MACH_MASK 0x0000ffff + +/* Macros for vsc9953_ana_port.vlan_cfg register */ +#define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000 +#define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000 +#define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000 +#define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000 +#define VSC9953_VLAN_CFG_VID_MASK 0x00000fff + +/* Macros for vsc9953_rew_port.port_vlan_cfg register */ +#define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff + +/* Macros for vsc9953_ana_ana_tables.vlan_tidx register */ +#define VSC9953_ANA_TBL_VID_MASK 0x00000fff + +/* Macros for vsc9953_ana_ana_tables.vlan_access register */ +#define VSC9953_VLAN_PORT_MASK 0x00001ffc +#define VSC9953_VLAN_CMD_MASK 0x00000003 +#define VSC9953_VLAN_CMD_IDLE 0x00000000 +#define VSC9953_VLAN_CMD_READ 0x00000001 +#define VSC9953_VLAN_CMD_WRITE 0x00000002 +#define VSC9953_VLAN_CMD_INIT 0x00000003 + +/* Macros for vsc9953_ana_port.port_cfg register */ +#define VSC9953_PORT_CFG_LEARN_ENA 0x00000080 +#define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100 +#define VSC9953_PORT_CFG_LEARN_CPU 0x00000200 +#define VSC9953_PORT_CFG_LEARN_DROP 0x00000400 + +/* Macros for vsc9953_qsys_sys.switch_port_mode register */ +#define VSC9953_PORT_ENA 0x00002000 + +/* Macros for vsc9953_ana_ana.agen_ctrl register */ +#define VSC9953_FID_MASK_ALL 0x00fff000 + +/* Macros for vsc9953_ana_ana.adv_learn register */ +#define VSC9953_VLAN_CHK 0x00000400 + +/* Macros for vsc9953_rew_port.port_tag_cfg register */ +#define VSC9953_TAG_CFG_MASK 0x00000180 +#define VSC9953_TAG_CFG_NONE 0x00000000 +#define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080 +#define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100 +#define VSC9953_TAG_CFG_ALL 0x00000180 +#define VSC9953_TAG_VID_PVID 0x00000010 + +/* Macros for vsc9953_ana_ana.anag_efil register */ +#define VSC9953_AGE_PORT_EN 0x00080000 +#define VSC9953_AGE_PORT_MASK 0x0007c000 +#define VSC9953_AGE_VID_EN 0x00002000 +#define VSC9953_AGE_VID_MASK 0x00001fff + +/* Macros for vsc9953_ana_ana_tables.mach_data register */ +#define VSC9953_MACHDATA_VID_MASK 0x1fff0000 + #define VSC9953_MAX_PORTS 10 #define VSC9953_PORT_CHECK(port) \ (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) @@ -64,6 +161,9 @@ (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \ ) ? 0 : 1 \ ) +#define VSC9953_MAX_VLAN 4096 +#define VSC9953_VLAN_CHECK(vid) \ + (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1) #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" @@ -74,9 +174,9 @@ struct vsc9953_mdio_info { char *name; }; -/* VSC9953 ANA structure for T1040 U-boot*/ +/* VSC9953 ANA structure */ -struct vsc9953_ana_port { +struct vsc9953_ana_port { u32 vlan_cfg; u32 drop_cfg; u32 qos_cfg; @@ -116,6 +216,7 @@ struct vsc9953_ana_ana_tables { struct vsc9953_ana_ana { u32 adv_learn; u32 vlan_mask; + u32 reserved; u32 anag_efil; u32 an_events; u32 storm_limit_burst; @@ -138,7 +239,7 @@ struct vsc9953_ana_pgid { u32 port_grp_id[91]; }; -struct vsc9953_ana_pfc { +struct vsc9953_ana_pfc { u32 pfc_cfg; u32 reserved1[15]; }; @@ -149,7 +250,7 @@ struct vsc9953_ana_pol_misc { u32 pol_hyst; }; -struct vsc9953_ana_common { +struct vsc9953_ana_common { u32 aggr_cfg; u32 cpuq_cfg; u32 cpuq_8021_cfg; @@ -176,18 +277,18 @@ struct vsc9953_analyzer { u32 reserved5[196]; struct vsc9953_ana_common common; }; -/* END VSC9953 ANA structure for T1040 U-boot*/ +/* END VSC9953 ANA structure t*/ -/* VSC9953 DEV_GMII structure for T1040 U-boot*/ +/* VSC9953 DEV_GMII structure */ -struct vsc9953_dev_gmii_port_mode { +struct vsc9953_dev_gmii_port_mode { u32 clock_cfg; u32 port_misc; u32 reserved1; u32 eee_cfg; }; -struct vsc9953_dev_gmii_mac_cfg_status { +struct vsc9953_dev_gmii_mac_cfg_status { u32 mac_ena_cfg; u32 mac_mode_cfg; u32 mac_maxlen_cfg; @@ -205,11 +306,11 @@ struct vsc9953_dev_gmii { struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status; }; -/* END VSC9953 DEV_GMII structure for T1040 U-boot*/ +/* END VSC9953 DEV_GMII structure */ -/* VSC9953 QSYS structure for T1040 U-boot*/ +/* VSC9953 QSYS structure */ -struct vsc9953_qsys_hsch { +struct vsc9953_qsys_hsch { u32 cir_cfg; u32 reserved1; u32 se_cfg; @@ -218,7 +319,7 @@ struct vsc9953_qsys_hsch { u32 reserved2[20]; }; -struct vsc9953_qsys_sys { +struct vsc9953_qsys_sys { u32 port_mode[12]; u32 switch_port_mode[11]; u32 stat_cnt_cfg; @@ -232,32 +333,32 @@ struct vsc9953_qsys_sys { u32 reserved1[23]; }; -struct vsc9953_qsys_qos_cfg { +struct vsc9953_qsys_qos_cfg { u32 red_profile[16]; u32 res_qos_mode; }; -struct vsc9953_qsys_drop_cfg { +struct vsc9953_qsys_drop_cfg { u32 egr_drop_mode; }; -struct vsc9953_qsys_mmgt { +struct vsc9953_qsys_mmgt { u32 eq_cntrl; u32 reserved1; }; -struct vsc9953_qsys_hsch_misc { +struct vsc9953_qsys_hsch_misc { u32 hsch_misc_cfg; u32 reserved1[546]; }; -struct vsc9953_qsys_res_ctrl { +struct vsc9953_qsys_res_ctrl { u32 res_cfg; u32 res_stat; }; -struct vsc9953_qsys_reg { +struct vsc9953_qsys_reg { struct vsc9953_qsys_hsch hsch[108]; struct vsc9953_qsys_sys sys; struct vsc9953_qsys_qos_cfg qos_cfg; @@ -267,18 +368,123 @@ struct vsc9953_qsys_reg { struct vsc9953_qsys_res_ctrl res_ctrl[1024]; }; -/* END VSC9953 QSYS structure for T1040 U-boot*/ - -/* VSC9953 SYS structure for T1040 U-boot*/ - -struct vsc9953_sys_stat { - u32 rx_cntrs[64]; - u32 tx_cntrs[64]; - u32 drop_cntrs[64]; +/* END VSC9953 QSYS structure */ + +/* VSC9953 SYS structure */ + +struct vsc9953_rx_cntrs { + u32 c_rx_oct; + u32 c_rx_uc; + u32 c_rx_mc; + u32 c_rx_bc; + u32 c_rx_short; + u32 c_rx_frag; + u32 c_rx_jabber; + u32 c_rx_crc; + u32 c_rx_symbol_err; + u32 c_rx_sz_64; + u32 c_rx_sz_65_127; + u32 c_rx_sz_128_255; + u32 c_rx_sz_256_511; + u32 c_rx_sz_512_1023; + u32 c_rx_sz_1024_1526; + u32 c_rx_sz_jumbo; + u32 c_rx_pause; + u32 c_rx_control; + u32 c_rx_long; + u32 c_rx_cat_drop; + u32 c_rx_red_prio_0; + u32 c_rx_red_prio_1; + u32 c_rx_red_prio_2; + u32 c_rx_red_prio_3; + u32 c_rx_red_prio_4; + u32 c_rx_red_prio_5; + u32 c_rx_red_prio_6; + u32 c_rx_red_prio_7; + u32 c_rx_yellow_prio_0; + u32 c_rx_yellow_prio_1; + u32 c_rx_yellow_prio_2; + u32 c_rx_yellow_prio_3; + u32 c_rx_yellow_prio_4; + u32 c_rx_yellow_prio_5; + u32 c_rx_yellow_prio_6; + u32 c_rx_yellow_prio_7; + u32 c_rx_green_prio_0; + u32 c_rx_green_prio_1; + u32 c_rx_green_prio_2; + u32 c_rx_green_prio_3; + u32 c_rx_green_prio_4; + u32 c_rx_green_prio_5; + u32 c_rx_green_prio_6; + u32 c_rx_green_prio_7; + u32 reserved[20]; +}; + +struct vsc9953_tx_cntrs { + u32 c_tx_oct; + u32 c_tx_uc; + u32 c_tx_mc; + u32 c_tx_bc; + u32 c_tx_col; + u32 c_tx_drop; + u32 c_tx_pause; + u32 c_tx_sz_64; + u32 c_tx_sz_65_127; + u32 c_tx_sz_128_255; + u32 c_tx_sz_256_511; + u32 c_tx_sz_512_1023; + u32 c_tx_sz_1024_1526; + u32 c_tx_sz_jumbo; + u32 c_tx_yellow_prio_0; + u32 c_tx_yellow_prio_1; + u32 c_tx_yellow_prio_2; + u32 c_tx_yellow_prio_3; + u32 c_tx_yellow_prio_4; + u32 c_tx_yellow_prio_5; + u32 c_tx_yellow_prio_6; + u32 c_tx_yellow_prio_7; + u32 c_tx_green_prio_0; + u32 c_tx_green_prio_1; + u32 c_tx_green_prio_2; + u32 c_tx_green_prio_3; + u32 c_tx_green_prio_4; + u32 c_tx_green_prio_5; + u32 c_tx_green_prio_6; + u32 c_tx_green_prio_7; + u32 c_tx_aged; + u32 reserved[33]; +}; + +struct vsc9953_drop_cntrs { + u32 c_dr_local; + u32 c_dr_tail; + u32 c_dr_yellow_prio_0; + u32 c_dr_yellow_prio_1; + u32 c_dr_yellow_prio_2; + u32 c_dr_yellow_prio_3; + u32 c_dr_yellow_prio_4; + u32 c_dr_yellow_prio_5; + u32 c_dr_yellow_prio_6; + u32 c_dr_yellow_prio_7; + u32 c_dr_green_prio_0; + u32 c_dr_green_prio_1; + u32 c_dr_green_prio_2; + u32 c_dr_green_prio_3; + u32 c_dr_green_prio_4; + u32 c_dr_green_prio_5; + u32 c_dr_green_prio_6; + u32 c_dr_green_prio_7; + u32 reserved[46]; +}; + +struct vsc9953_sys_stat { + struct vsc9953_rx_cntrs rx_cntrs; + struct vsc9953_tx_cntrs tx_cntrs; + struct vsc9953_drop_cntrs drop_cntrs; u32 reserved1[6]; }; -struct vsc9953_sys_sys { +struct vsc9953_sys_sys { u32 reset_cfg; u32 reserved1; u32 vlan_etype_cfg; @@ -289,7 +495,7 @@ struct vsc9953_sys_sys { u32 reserved2[50]; }; -struct vsc9953_sys_pause_cfg { +struct vsc9953_sys_pause_cfg { u32 pause_cfg[11]; u32 pause_tot_cfg; u32 tail_drop_level[11]; @@ -297,29 +503,52 @@ struct vsc9953_sys_pause_cfg { u32 mac_fc_cfg[10]; }; -struct vsc9953_sys_mmgt { +struct vsc9953_sys_mmgt { u16 free_cnt; }; -struct vsc9953_system_reg { +struct vsc9953_system_reg { struct vsc9953_sys_stat stat; struct vsc9953_sys_sys sys; struct vsc9953_sys_pause_cfg pause_cfg; struct vsc9953_sys_mmgt mmgt; }; -/* END VSC9953 SYS structure for T1040 U-boot*/ +/* END VSC9953 SYS structure */ + +/* VSC9953 REW structure */ + +struct vsc9953_rew_port { + u32 port_vlan_cfg; + u32 port_tag_cfg; + u32 port_port_cfg; + u32 port_dscp_cfg; + u32 port_pcp_dei_qos_map_cfg[16]; + u32 reserved[12]; +}; + +struct vsc9953_rew_common { + u32 reserve[4]; + u32 dscp_remap_dp1_cfg[64]; + u32 dscp_remap_cfg[64]; +}; + +struct vsc9953_rew_reg { + struct vsc9953_rew_port port[12]; + struct vsc9953_rew_common common; +}; +/* END VSC9953 REW structure */ -/* VSC9953 DEVCPU_GCB structure for T1040 U-boot*/ +/* VSC9953 DEVCPU_GCB structure */ -struct vsc9953_chip_regs { +struct vsc9953_chip_regs { u32 chipd_id; u32 gpr; u32 soft_rst; }; -struct vsc9953_gpio { +struct vsc9953_gpio { u32 gpio_out_set[10]; u32 gpio_out_clr[10]; u32 gpio_out[10]; @@ -338,31 +567,31 @@ struct vsc9953_mii_mng { u32 miiscan_lst_rslts_valid; }; -struct vsc9953_mii_read_scan { +struct vsc9953_mii_read_scan { u32 mii_scan_results_sticky[2]; }; -struct vsc9953_devcpu_gcb { +struct vsc9953_devcpu_gcb { struct vsc9953_chip_regs chip_regs; struct vsc9953_gpio gpio; struct vsc9953_mii_mng mii_mng[2]; struct vsc9953_mii_read_scan mii_read_scan; }; -/* END VSC9953 DEVCPU_GCB structure for T1040 U-boot*/ +/* END VSC9953 DEVCPU_GCB structure */ -/* VSC9953 IS* structure for T1040 U-boot*/ +/* VSC9953 IS* structure */ -struct vsc9953_vcap_core_cfg { +struct vsc9953_vcap_core_cfg { u32 vcap_update_ctrl; u32 vcap_mv_cfg; }; -struct vsc9953_vcap { -struct vsc9953_vcap_core_cfg vcap_core_cfg; +struct vsc9953_vcap { + struct vsc9953_vcap_core_cfg vcap_core_cfg; }; -/* END VSC9953 IS* structure for T1040 U-boot*/ +/* END VSC9953 IS* structure */ #define VSC9953_PORT_INFO_INITIALIZER(idx) \ { \ @@ -388,15 +617,15 @@ struct vsc9953_port_info { /* Structure to describe a VSC9953 switch */ struct vsc9953_info { - struct vsc9953_port_info port[VSC9953_MAX_PORTS]; + struct vsc9953_port_info port[VSC9953_MAX_PORTS]; }; void vsc9953_init(bd_t *bis); -void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus); -void vsc9953_port_info_set_phy_address(int port, int address); -void vsc9953_port_enable(int port); -void vsc9953_port_disable(int port); -void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int); +void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus); +void vsc9953_port_info_set_phy_address(int port_no, int address); +void vsc9953_port_enable(int port_no); +void vsc9953_port_disable(int port_no); +void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int); #endif /* _VSC9953_H_ */ |