diff options
Diffstat (limited to 'include')
97 files changed, 3397 insertions, 138 deletions
diff --git a/include/adc.h b/include/adc.h new file mode 100644 index 0000000000..4b14017849 --- /dev/null +++ b/include/adc.h @@ -0,0 +1,288 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ADC_H_ +#define _ADC_H_ + +/* ADC_CHANNEL() - ADC channel bit mask, to select only required channels */ +#define ADC_CHANNEL(x) (1 << x) + +/* The last possible selected channel with 32-bit mask */ +#define ADC_MAX_CHANNEL 31 + +/** + * adc_data_format: define the ADC output data format, can be useful when + * the device's input Voltage range is bipolar. + * - ADC_DATA_FORMAT_BIN - binary offset + * - ADC_DATA_FORMAT_2S - two's complement + * + * Note: Device's driver should fill the 'data_format' field of its uclass's + * platform data using one of the above data format types. + */ +enum adc_data_format { + ADC_DATA_FORMAT_BIN, + ADC_DATA_FORMAT_2S, +}; + +/** + * struct adc_channel - structure to hold channel conversion data. + * Useful to keep the result of a multi-channel conversion output. + * + * @id - channel id + * @data - channel conversion data + */ +struct adc_channel { + int id; + unsigned int data; +}; + +/** + * struct adc_uclass_platdata - basic ADC info + * + * Note: The positive/negative reference Voltage is only a name and it doesn't + * provide an information about the value polarity. It is possible, for both + * values to be a negative or positive. For this purpose the uclass's platform + * data provides a bool fields: 'vdd/vss_supply_is_negative'. This is useful, + * since the regulator API returns only a positive Voltage values. + * + * To get the reference Voltage values with polarity, use functions: + * - adc_vdd_value() + * - adc_vss_value() + * Those are useful for some cases of ADC's references, e.g.: + * * Vdd: +3.3V; Vss: -3.3V -> 6.6 Vdiff + * * Vdd: +3.3V; Vss: +0.3V -> 3.0 Vdiff + * * Vdd: +3.3V; Vss: 0.0V -> 3.3 Vdiff + * The last one is usually standard and doesn't require the fdt polarity info. + * + * For more informations read binding info: + * - doc/device-tree-bindings/adc/adc.txt + * + * @data_mask - conversion output data mask + * @data_timeout_us - single channel conversion timeout + * @multidata_timeout_us - multi channel conversion timeout + * @channel_mask - bit mask of available channels [0:31] + * @vdd_supply - positive reference Voltage supply (regulator) + * @vss_supply - negative reference Voltage supply (regulator) + * @vdd_polarity_negative - positive reference Voltage has negative polarity + * @vss_polarity_negative - negative reference Voltage has negative polarity + * @vdd_microvolts - positive reference Voltage value + * @vss_microvolts - negative reference Voltage value + */ +struct adc_uclass_platdata { + int data_format; + unsigned int data_mask; + unsigned int data_timeout_us; + unsigned int multidata_timeout_us; + unsigned int channel_mask; + struct udevice *vdd_supply; + struct udevice *vss_supply; + bool vdd_polarity_negative; + bool vss_polarity_negative; + int vdd_microvolts; + int vss_microvolts; +}; + +/** + * struct adc_ops - ADC device operations for single/multi-channel operation. + */ +struct adc_ops { + /** + * start_channel() - start conversion with its default parameters + * for the given channel number. + * + * @dev: ADC device to init + * @channel: analog channel number + * @return: 0 if OK, -ve on error + */ + int (*start_channel)(struct udevice *dev, int channel); + + /** + * start_channels() - start conversion with its default parameters + * for the channel numbers selected by the bit mask. + * + * This is optional, useful when the hardware supports multichannel + * conversion by the single software trigger. + * + * @dev: ADC device to init + * @channel_mask: bit mask of selected analog channels + * @return: 0 if OK, -ve on error + */ + int (*start_channels)(struct udevice *dev, unsigned int channel_mask); + + /** + * channel_data() - get conversion output data for the given channel. + * + * Note: The implementation of this function should only check, that + * the conversion data is available at the call time. If the hardware + * requires some delay to get the data, then this function should + * return with -EBUSY value. The ADC API will call it in a loop, + * until the data is available or the timeout expires. The maximum + * timeout for this operation is defined by the field 'data_timeout_us' + * in ADC uclasses platform data structure. + * + * @dev: ADC device to trigger + * @channel: selected analog channel number + * @data: returned pointer to selected channel's output data + * @return: 0 if OK, -EBUSY if busy, and other negative on error + */ + int (*channel_data)(struct udevice *dev, int channel, + unsigned int *data); + + /** + * channels_data() - get conversion data for the selected channels. + * + * This is optional, useful when multichannel conversion is supported + * by the hardware, by the single software trigger. + * + * For the proper implementation, please look at the 'Note' for the + * above method. The only difference is in used timeout value, which + * is defined by field 'multidata_timeout_us'. + * + * @dev: ADC device to trigger + * @channel_mask: bit mask of selected analog channels + * @channels: returned pointer to array of output data for channels + * selected by the given mask + * @return: 0 if OK, -ve on error + */ + int (*channels_data)(struct udevice *dev, unsigned int channel_mask, + struct adc_channel *channels); + + /** + * stop() - stop conversion of the given ADC device + * + * @dev: ADC device to stop + * @return: 0 if OK, -ve on error + */ + int (*stop)(struct udevice *dev); +}; + +/** + * adc_start_channel() - start conversion for given device/channel and exit. + * + * @dev: ADC device + * @channel: analog channel number + * @return: 0 if OK, -ve on error + */ +int adc_start_channel(struct udevice *dev, int channel); + +/** + * adc_start_channels() - start conversion for given device/channels and exit. + * + * Note: + * To use this function, device must implement method: start_channels(). + * + * @dev: ADC device to start + * @channel_mask: channel selection - a bit mask + * @channel_mask: bit mask of analog channels + * @return: 0 if OK, -ve on error + */ +int adc_start_channels(struct udevice *dev, unsigned int channel_mask); + +/** + * adc_channel_data() - get conversion data for the given device channel number. + * + * @dev: ADC device to read + * @channel: analog channel number + * @data: pointer to returned channel's data + * @return: 0 if OK, -ve on error + */ +int adc_channel_data(struct udevice *dev, int channel, unsigned int *data); + +/** + * adc_channels_data() - get conversion data for the channels selected by mask + * + * Note: + * To use this function, device must implement methods: + * - start_channels() + * - channels_data() + * + * @dev: ADC device to read + * @channel_mask: channel selection - a bit mask + * @channels: pointer to structure array of returned data for each channel + * @return: 0 if OK, -ve on error + */ +int adc_channels_data(struct udevice *dev, unsigned int channel_mask, + struct adc_channel *channels); + +/** + * adc_data_mask() - get data mask (ADC resolution bitmask) for given ADC device + * + * This can be used if adc uclass platform data is filled. + * + * @dev: ADC device to check + * @data_mask: pointer to the returned data bitmask + * @return: 0 if OK, -ve on error + */ +int adc_data_mask(struct udevice *dev, unsigned int *data_mask); + +/** + * adc_channel_single_shot() - get output data of conversion for the ADC + * device's channel. This function searches for the device with the given name, + * starts the given channel conversion and returns the output data. + * + * Note: To use this function, device must implement metods: + * - start_channel() + * - channel_data() + * + * @name: device's name to search + * @channel: device's input channel to init + * @data: pointer to conversion output data + * @return: 0 if OK, -ve on error + */ +int adc_channel_single_shot(const char *name, int channel, unsigned int *data); + +/** + * adc_channels_single_shot() - get ADC conversion output data for the selected + * device's channels. This function searches for the device by the given name, + * starts the selected channels conversion and returns the output data as array + * of type 'struct adc_channel'. + * + * Note: This function can be used if device implements one of ADC's single + * or multi-channel operation API. If multi-channel operation is not supported, + * then each selected channel is triggered by the sequence start/data in a loop. + * + * @name: device's name to search + * @channel_mask: channel selection - a bit mask + * @channels: pointer to conversion output data for the selected channels + * @return: 0 if OK, -ve on error + */ +int adc_channels_single_shot(const char *name, unsigned int channel_mask, + struct adc_channel *channels); + +/** + * adc_vdd_value() - get the ADC device's positive reference Voltage value + * + * Note: Depending on bool value 'vdd_supply_is_negative' of platform data, + * the returned uV value can be negative, and it's not an error. + * + * @dev: ADC device to check + * @uV: Voltage value with polarization sign (uV) + * @return: 0 on success or -ve on error +*/ +int adc_vdd_value(struct udevice *dev, int *uV); + +/** + * adc_vss_value() - get the ADC device's negative reference Voltage value + * + * Note: Depending on bool value 'vdd_supply_is_negative' of platform data, + * the returned uV value can be negative, and it's not an error. + * + * @dev: ADC device to check + * @uV: Voltage value with polarization sign (uV) + * @return: 0 on success or -ve on error +*/ +int adc_vss_value(struct udevice *dev, int *uV); + +/** + * adc_stop() - stop operation for given ADC device. + * + * @dev: ADC device to stop + * @return: 0 if OK, -ve on error + */ +int adc_stop(struct udevice *dev); + +#endif diff --git a/include/asm-generic/bitops/__ffs.h b/include/asm-generic/bitops/__ffs.h new file mode 100644 index 0000000000..937d7c4355 --- /dev/null +++ b/include/asm-generic/bitops/__ffs.h @@ -0,0 +1,43 @@ +#ifndef _ASM_GENERIC_BITOPS___FFS_H_ +#define _ASM_GENERIC_BITOPS___FFS_H_ + +#include <asm/types.h> + +/** + * __ffs - find first bit in word. + * @word: The word to search + * + * Undefined if no bit exists, so code should check against 0 first. + */ +static __always_inline unsigned long __ffs(unsigned long word) +{ + int num = 0; + +#if BITS_PER_LONG == 64 + if ((word & 0xffffffff) == 0) { + num += 32; + word >>= 32; + } +#endif + if ((word & 0xffff) == 0) { + num += 16; + word >>= 16; + } + if ((word & 0xff) == 0) { + num += 8; + word >>= 8; + } + if ((word & 0xf) == 0) { + num += 4; + word >>= 4; + } + if ((word & 0x3) == 0) { + num += 2; + word >>= 2; + } + if ((word & 0x1) == 0) + num += 1; + return num; +} + +#endif /* _ASM_GENERIC_BITOPS___FFS_H_ */ diff --git a/include/asm-generic/bitops/__fls.h b/include/asm-generic/bitops/__fls.h new file mode 100644 index 0000000000..a60a7ccb67 --- /dev/null +++ b/include/asm-generic/bitops/__fls.h @@ -0,0 +1,43 @@ +#ifndef _ASM_GENERIC_BITOPS___FLS_H_ +#define _ASM_GENERIC_BITOPS___FLS_H_ + +#include <asm/types.h> + +/** + * __fls - find last (most-significant) set bit in a long word + * @word: the word to search + * + * Undefined if no set bit exists, so code should check against 0 first. + */ +static __always_inline unsigned long __fls(unsigned long word) +{ + int num = BITS_PER_LONG - 1; + +#if BITS_PER_LONG == 64 + if (!(word & (~0ul << 32))) { + num -= 32; + word <<= 32; + } +#endif + if (!(word & (~0ul << (BITS_PER_LONG-16)))) { + num -= 16; + word <<= 16; + } + if (!(word & (~0ul << (BITS_PER_LONG-8)))) { + num -= 8; + word <<= 8; + } + if (!(word & (~0ul << (BITS_PER_LONG-4)))) { + num -= 4; + word <<= 4; + } + if (!(word & (~0ul << (BITS_PER_LONG-2)))) { + num -= 2; + word <<= 2; + } + if (!(word & (~0ul << (BITS_PER_LONG-1)))) + num -= 1; + return num; +} + +#endif /* _ASM_GENERIC_BITOPS___FLS_H_ */ diff --git a/include/asm-generic/bitops/fls.h b/include/asm-generic/bitops/fls.h new file mode 100644 index 0000000000..0576d1f42f --- /dev/null +++ b/include/asm-generic/bitops/fls.h @@ -0,0 +1,41 @@ +#ifndef _ASM_GENERIC_BITOPS_FLS_H_ +#define _ASM_GENERIC_BITOPS_FLS_H_ + +/** + * fls - find last (most-significant) bit set + * @x: the word to search + * + * This is defined the same way as ffs. + * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. + */ + +static __always_inline int fls(int x) +{ + int r = 32; + + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; +} + +#endif /* _ASM_GENERIC_BITOPS_FLS_H_ */ diff --git a/include/asm-generic/bitops/fls64.h b/include/asm-generic/bitops/fls64.h new file mode 100644 index 0000000000..b097cf8444 --- /dev/null +++ b/include/asm-generic/bitops/fls64.h @@ -0,0 +1,36 @@ +#ifndef _ASM_GENERIC_BITOPS_FLS64_H_ +#define _ASM_GENERIC_BITOPS_FLS64_H_ + +#include <asm/types.h> + +/** + * fls64 - find last set bit in a 64-bit word + * @x: the word to search + * + * This is defined in a similar way as the libc and compiler builtin + * ffsll, but returns the position of the most significant set bit. + * + * fls64(value) returns 0 if value is 0 or the position of the last + * set bit if value is nonzero. The last (most significant) bit is + * at position 64. + */ +#if BITS_PER_LONG == 32 +static __always_inline int fls64(__u64 x) +{ + __u32 h = x >> 32; + if (h) + return fls(h) + 32; + return fls(x); +} +#elif BITS_PER_LONG == 64 +static __always_inline int fls64(__u64 x) +{ + if (x == 0) + return 0; + return __fls(x) + 1; +} +#else +#error BITS_PER_LONG not 32 or 64 +#endif + +#endif /* _ASM_GENERIC_BITOPS_FLS64_H_ */ diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index 458952fb58..328bc62948 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -71,6 +71,7 @@ extern char __bss_start[]; extern char __bss_end[]; extern char __image_copy_start[]; extern char __image_copy_end[]; +extern char _image_binary_end[]; extern char __rel_dyn_start[]; extern char __rel_dyn_end[]; diff --git a/include/common.h b/include/common.h index ecb1f0682e..09a131da0b 100644 --- a/include/common.h +++ b/include/common.h @@ -76,6 +76,12 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_SOC_DA8XX #include <asm/arch/hardware.h> #endif +#ifdef CONFIG_FSL_LSCH3 +#include <asm/arch/immap_lsch3.h> +#endif +#ifdef CONFIG_FSL_LSCH2 +#include <asm/arch/immap_lsch2.h> +#endif #include <part.h> #include <flash.h> diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h new file mode 100644 index 0000000000..ab7dd08914 --- /dev/null +++ b/include/configs/10m50_devboard.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * BOARD/CPU + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* + * SERIAL + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */ + +/* + * Flash + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define CONFIG_MTD_DEVICE + +/* + * NET options + */ +#define CONFIG_SYS_RX_ETH_BUFFER 0 +#define CONFIG_CMD_MII +#define CONFIG_PHY_GIGE +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_PHY_MARVELL + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * FDT options + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_LMB + +/* + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + */ +#define CONFIG_ENV_IS_IN_FLASH + +#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CONFIG_ENV_ADDR 0xf4040000 + +/* + * MEMORY ORGANIZATION + * -Monitor at top of sdram. + * -The heap is placed below the monitor + * -The stack is placed below the heap (&grows down). + */ +#define CONFIG_SYS_SDRAM_BASE 0xc8000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_MALLOC_LEN 0x20000 + +/* + * MISC + */ +#define CONFIG_SYS_LONGHELP /* Provide extended help */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ +#define CONFIG_SYS_MAXARGS 16 /* Max command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + \ + 16) /* Print buf size */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \ + CONFIG_ENV_SIZE - \ + CONFIG_SYS_MALLOC_LEN - \ + 0x10000) +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CMD_GPIO + +#endif /* __CONFIG_H */ diff --git a/include/configs/nios2-generic.h b/include/configs/3c120_devboard.h index b38513e99b..856c836385 100644 --- a/include/configs/nios2-generic.h +++ b/include/configs/3c120_devboard.h @@ -24,22 +24,22 @@ /* * CFI Flash */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* - * MII/PHY + * NET options */ -#define CONFIG_CMD_MII 1 -#define CONFIG_PHY_GIGE 1 -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 -#define CONFIG_PHY_MARVELL 1 +#define CONFIG_SYS_RX_ETH_BUFFER 0 +#define CONFIG_CMD_MII +#define CONFIG_PHY_GIGE +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_PHY_MARVELL /* * BOOTP options @@ -77,15 +77,13 @@ */ #define CONFIG_SYS_SDRAM_BASE 0xD0000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_MONITOR_IS_IN_RAM #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_SDRAM_SIZE - \ CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x20000) -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - \ - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_MALLOC_BASE +#define CONFIG_SYS_MALLOC_LEN 0x20000 /* * MISC @@ -99,7 +97,10 @@ 16) /* Print buf size */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - 0x20000) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \ + CONFIG_ENV_SIZE - \ + CONFIG_SYS_MALLOC_LEN - \ + 0x10000) #define CONFIG_CMDLINE_EDITING #define CONFIG_CMD_GPIO diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index a006dcebaa..54dcf3b954 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -17,7 +17,6 @@ #define CONFIG_BSC9132 #endif -#define CONFIG_FSL_CLK #define CONFIG_MISC_INIT_R #ifdef CONFIG_SDCARD diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index cfa5931311..551b72d153 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -10,7 +10,6 @@ #define __CONFIG_H #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK /* * High Level Configuration Options diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 990fc04e87..7d1262d510 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -9,7 +9,6 @@ #define __CONFIG_H #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK /* * High Level Configuration Options diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index fcc531b600..ab68e63881 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -16,7 +16,6 @@ #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XERDB 1 #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #define CONFIG_SYS_TEXT_BASE 0xFE000000 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index af8eb8c0d2..29c27fa9a7 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -12,7 +12,6 @@ #define __CONFIG_H #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_36BIT diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 9f784e0adb..6f614b0cbe 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -12,7 +12,6 @@ #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 9e40730395..81b085572d 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -15,7 +15,6 @@ #define CONFIG_PHYS_64BIT #endif #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #define CONFIG_P1010 #define CONFIG_E500 /* BOOKE e500 family */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index c571fac666..a9d825baf5 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -12,7 +12,6 @@ #include "../board/freescale/common/ics307_clk.h" #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 0cd990477b..2c4c8b5a02 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -15,7 +15,6 @@ #define CONFIG_PHYS_64BIT #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_PPC_P2041 -#define CONFIG_FSL_CLK #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 4f22657703..52942edbd4 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -20,7 +20,6 @@ #define CONFIG_MP /* support multiple processors */ #define CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_FSL_CLK #ifdef CONFIG_PHYS_64BIT #define CONFIG_ADDR_MAP 1 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index d412d0b2b7..39fa5e2b18 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -20,7 +20,6 @@ #define CONFIG_MP /* support multiple processors */ #define CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_FSL_CLK #ifdef CONFIG_PHYS_64BIT #define CONFIG_ADDR_MAP 1 diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 18df2372a4..fc263dfcb6 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -29,7 +29,6 @@ #define CONFIG_T1040QDS #define CONFIG_PHYS_64BIT #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE @@ -593,12 +592,14 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC +#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_FSL_ESDHC_ADAPTER_IDENT #endif /* Qman/Bman */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 2091015638..840be047cd 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -13,7 +13,6 @@ #define CONFIG_T104xRDB #define CONFIG_PHYS_64BIT #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #define CONFIG_E500 /* BOOKE e500 family */ #include <asm/config_mpc85xx.h> @@ -742,7 +741,9 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #ifdef CONFIG_FMAN_ENET #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 -#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB) +#elif defined(CONFIG_T1040D4RDB) +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 +#elif defined(CONFIG_T1042D4RDB) #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index d35b9d2d90..a81f1e66f3 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -13,7 +13,6 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#define CONFIG_FSL_CLK #define CONFIG_MMC #define CONFIG_USB_EHCI #if defined(CONFIG_PPC_T2080) diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index c632b8e328..8b762346ac 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -14,7 +14,6 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_T2080RDB #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#define CONFIG_FSL_CLK #define CONFIG_MMC #define CONFIG_USB_EHCI #define CONFIG_FSL_SATA_V2 diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index dd8dd73f98..4edb3cb91f 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -12,7 +12,6 @@ #define CONFIG_T4240QDS #define CONFIG_PHYS_64BIT -#define CONFIG_FSL_CLK #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 2c5f800cbd..2e875d2fc1 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -13,7 +13,6 @@ #define CONFIG_T4240RDB #define CONFIG_PHYS_64BIT #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index 0b609af2c9..8611473773 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -15,7 +15,6 @@ #define __CONFIG_H #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #define CONFIG_FSL_ELBC #define CONFIG_PCI diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index f9385349ae..9db4a4ff27 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -97,8 +97,8 @@ #elif CONFIG_SYS_USE_SERIALFLASH /* u-boot env in serial flash, by default is bus 0 and cs 0 */ #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_ENV_OFFSET 0x6000 +#define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x1000 #define CONFIG_BOOTCOMMAND "sf probe 0; " \ "sf read 0x21000000 0x60000 0xc000; " \ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 9fa8f817f2..7658e61367 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -18,7 +18,7 @@ #define CONFIG_SYS_THUMB_BUILD #define CONFIG_USE_ARCH_MEMCPY #define CONFIG_USE_ARCH_MEMSET -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_ARCH_MISC_INIT #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 77c2edcbb3..600bb835ce 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -44,7 +44,6 @@ #define CONFIG_P1022 #define CONFIG_CONTROLCENTERD #define CONFIG_MP /* support multiple processors */ -#define CONFIG_FSL_CLK #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 3c9a529162..921021634d 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -11,7 +11,6 @@ #define __CONFIG_H #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #include "../board/freescale/common/ics307_clk.h" diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h new file mode 100644 index 0000000000..5d25fb1400 --- /dev/null +++ b/include/configs/cyrus.h @@ -0,0 +1,587 @@ +/* + * Based on corenet_ds.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CYRUS + +#define CONFIG_PHYS_64BIT + +#if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040) +#error Must call Cyrus CONFIG with a specific CPU enabled. +#endif + + +#define CONFIG_MMC +#define CONFIG_SDCARD +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE3 +#define CONFIG_PCIE4 +#ifdef CONFIG_PPC_P5020 +#define CONFIG_SYS_FSL_RAID_ENGINE +#define CONFIG_SYS_DPAA_RMAN +#endif +#define CONFIG_SYS_DPAA_PME + +/* + * Corenet DS style board configuration file + */ +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg +#if defined(CONFIG_PPC_P5020) +#define CONFIG_SYS_CLK_FREQ 133000000 +#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg +#elif defined(CONFIG_PPC_P5040) +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg +#endif + + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ + + +#define CONFIG_SYS_MMC_MAX_DEVICE 1 + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SYS_NO_FLASH + +#if defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 1658) +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +/* test POST memory test */ +#undef CONFIG_POST +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) +#else +#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#endif +#define CONFIG_SYS_L3_SIZE (1024 << 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR3 + +#define CONFIG_SYS_SPD_BUS_NUM 1 +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * Local Bus Definitions + */ + +#define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull +#else +#define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE +#endif + +#define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull +#else +#define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE +#endif + +/* Set the local bus clock 1/16 of platform clock */ +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) + +#define CONFIG_SYS_BR0_PRELIM \ +(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_BR1_PRELIM \ +(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) + +#define CONFIG_SYS_OR0_PRELIM 0xfff00010 +#define CONFIG_SYS_OR1_PRELIM 0xfff00010 + + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ +{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 + +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 + +#define CONFIG_SYS_I2C_GENERIC_MAC +#define CONFIG_SYS_I2C_MAC1_BUS 3 +#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 +#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 +#define CONFIG_SYS_I2C_MAC2_BUS 0 +#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 +#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa + +#define CONFIG_CMD_DATE 1 +#define CONFIG_RTC_MCP79411 1 +#define CONFIG_SYS_RTC_BUS_NUM 3 +#define CONFIG_SYS_I2C_RTC_ADDR 0x6f + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 +#endif +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + +/* Qman/Bman */ +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#else +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#endif +#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +/* Default address of microcode for the Linux Fman driver */ +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) + +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#endif + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_NET_MULTI + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_TBIPA_VALUE 8 +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC4" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#endif + +/* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_HAS_FSL_MPH_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL + /* _VIA_CONTROL_EP */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#endif + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define CONFIG_BAUDRATE 115200 + +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ +"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ +"bank_intlv=cs0_cs1;" \ +"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ +"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ +"netdev=eth0\0" \ +"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ +"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ +"consoledev=ttyS0\0" \ +"ramdiskaddr=2000000\0" \ +"fdtaddr=c00000\0" \ +"bdev=sda3\0" + +#define CONFIG_HDBOOT \ +"setenv bootargs root=/dev/$bdev rw " \ +"console=$consoledev,$baudrate $othbootargs;" \ +"tftp $loadaddr $bootfile;" \ +"tftp $fdtaddr $fdtfile;" \ +"bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ +"setenv bootargs root=/dev/nfs rw " \ +"nfsroot=$serverip:$rootpath " \ +"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +"console=$consoledev,$baudrate $othbootargs;" \ +"tftp $loadaddr $bootfile;" \ +"tftp $fdtaddr $fdtfile;" \ +"bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ +"setenv bootargs root=/dev/ram rw " \ +"console=$consoledev,$baudrate $othbootargs;" \ +"tftp $ramdiskaddr $ramdiskfile;" \ +"tftp $loadaddr $bootfile;" \ +"tftp $fdtaddr $fdtfile;" \ +"bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#include <asm/fsl_secure_boot.h> + +#ifdef CONFIG_SECURE_BOOT +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 6e32de8546..cb9544b49e 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -82,11 +82,24 @@ "fdt ram 0x80f80000 0x80000;" \ "ramdisk ram 0x81000000 0x4000000\0" +#define DFU_ALT_INFO_QSPI \ + "dfu_alt_info_qspi=" \ + "MLO raw 0x0 0x010000;" \ + "MLO.backup1 raw 0x010000 0x010000;" \ + "MLO.backup2 raw 0x020000 0x010000;" \ + "MLO.backup3 raw 0x030000 0x010000;" \ + "u-boot.img raw 0x040000 0x0100000;" \ + "u-boot-spl-os raw 0x140000 0x080000;" \ + "u-boot-env raw 0x1C0000 0x010000;" \ + "u-boot-env.backup raw 0x1D0000 0x010000;" \ + "kernel raw 0x1E0000 0x800000\0" + #define DFUARGS \ "dfu_bufsiz=0x10000\0" \ DFU_ALT_INFO_MMC \ DFU_ALT_INFO_EMMC \ - DFU_ALT_INFO_RAM + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_QSPI /* Fastboot */ #define CONFIG_USB_FUNCTION_FASTBOOT @@ -207,6 +220,7 @@ #define CONFIG_DFU_MMC #define CONFIG_DFU_RAM +#define CONFIG_DFU_SF /* SATA */ #define CONFIG_BOARD_LATE_INIT diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index e2b9deba9e..3cb279a912 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -23,7 +23,6 @@ #define CONFIG_IDENT_STRING " hrcon 0.01" -#define CONFIG_FSL_CLK #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_LAST_STAGE_INIT diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index b8477e89d2..562e78f0a5 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -11,7 +11,7 @@ #define CONFIG_ARMV7_PSCI -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -69,7 +69,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 #define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1a000 @@ -82,7 +82,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0xc0000 #endif #ifdef CONFIG_QSPI_BOOT @@ -563,7 +563,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ARMV7_NONSEC #define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LS102XA_NS_ACCESS +#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_TIMER_CLK_FREQ 12500000 @@ -574,7 +574,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTDELAY 3 -#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 +#define CONFIG_SYS_QE_FW_ADDR 0x600c0000 #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -658,6 +658,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS #define CONFIG_CMD_BOOTZ #define CONFIG_MISC_INIT_R diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 784331ff8e..fdbbfc1196 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -11,7 +11,7 @@ #define CONFIG_ARMV7_PSCI -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -109,7 +109,13 @@ #endif #ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg +#else +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg +#endif #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT @@ -139,6 +145,9 @@ #ifdef CONFIG_QSPI_BOOT #define CONFIG_SYS_TEXT_BASE 0x40010000 +#endif + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_NO_FLASH #endif @@ -165,7 +174,7 @@ /* * IFC Definitions */ -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -280,7 +289,6 @@ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* EEPROM */ -#ifndef CONFIG_SD_BOOT #define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 1 @@ -288,7 +296,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#endif /* * MMC @@ -302,7 +309,7 @@ #define CONFIG_DOS_PARTITION /* SPI */ -#ifdef CONFIG_QSPI_BOOT +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) /* QSPI */ #define CONFIG_FSL_QSPI #define QSPI0_AMBA_BASE 0x40000000 @@ -412,10 +419,14 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#undef CONFIG_CMD_IMLS +#endif + #define CONFIG_ARMV7_NONSEC #define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LS102XA_NS_ACCESS +#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_TIMER_CLK_FREQ 12500000 @@ -429,13 +440,13 @@ #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ - "initrd_high=0xcfffffff\0" \ - "fdt_high=0xcfffffff\0" + "initrd_high=0xffffffff\0" \ + "fdt_high=0xffffffff\0" #else #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ - "initrd_high=0xcfffffff\0" \ - "fdt_high=0xcfffffff\0" + "initrd_high=0xffffffff\0" \ + "fdt_high=0xffffffff\0" #endif /* @@ -478,7 +489,7 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif -#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 +#define CONFIG_SYS_QE_FW_ADDR 0x600c0000 /* * Environment @@ -504,6 +515,7 @@ #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS #define CONFIG_CMD_BOOTZ #define CONFIG_MISC_INIT_R diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h new file mode 100644 index 0000000000..1f22dd34df --- /dev/null +++ b/include/configs/ls1043a_common.h @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1043A_COMMON_H +#define __LS1043A_COMMON_H + +#define CONFIG_REMAKE_ELF +#define CONFIG_FSL_LAYERSCAPE +#define CONFIG_FSL_LSCH2 +#define CONFIG_LS1043A +#define CONFIG_MP +#define CONFIG_SYS_FSL_CLK +#define CONFIG_GICV2 + +#include <asm/arch/config.h> +#ifdef CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_HAS_SERDES +#endif + +/* Link Definitions */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) + +#define CONFIG_SUPPORT_RAW_INITRD + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F 1 + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#ifndef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ +#endif + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* SD boot SPL */ +#ifdef CONFIG_SD_BOOT +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1d000 +#define CONFIG_SPL_STACK 0x1001e000 +#define CONFIG_SPL_PAD_TO 0x1d000 + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0xa0000 +#endif + +/* NAND SPL */ +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_PBL_PAD +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0xa0000 +#endif + +/* IFC */ +#define CONFIG_FSL_IFC +/* + * CONFIG_SYS_FLASH_BASE has the final address (core view) + * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting + */ +#define CONFIG_SYS_FLASH_BASE 0x60000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ +#endif + +/* I2C */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 +#define CONFIG_SYS_I2C_MXC_I2C2 +#define CONFIG_SYS_I2C_MXC_I2C3 +#define CONFIG_SYS_I2C_MXC_I2C4 + +/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" + +#define CONFIG_SYS_PCI_64BIT + +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ + +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 +#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP +#define CONFIG_E1000 +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI +#endif + +/* Command line configuration */ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_PING + +/* MMC */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION +#endif + +/* FMan ucode */ +#define CONFIG_SYS_DPAA_FMAN +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 + +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +/* FMan fireware Pre-load address */ +#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x61200000\0" \ + "kernel_load=0x807f0000\0" \ + "kernel_size=0x1000000\0" \ + "console=ttyAMA0,38400n8\0" + +#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ + "earlycon=uart8250,0x21c0500,115200" +#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ + "$kernel_size && bootm $kernel_load" +#define CONFIG_BOOTDELAY 10 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#endif /* __LS1043A_COMMON_H */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h new file mode 100644 index 0000000000..307d947405 --- /dev/null +++ b/include/configs/ls1043ardb.h @@ -0,0 +1,271 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1043ARDB_H__ +#define __LS1043ARDB_H__ + +#include "ls1043a_common.h" + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x82000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x60100000 +#endif + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define CONFIG_MISC_INIT_R + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +/* Physical Memory Map */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_SPD_BUS_NUM 0 + +#define CONFIG_FSL_DDR_BIST +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg +#endif + +/* + * NOR Flash Definitions + */ +#define CONFIG_SYS_NOR_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CONFIG_SYS_NOR_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_TRHZ_80) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x1) | \ + FTIM0_NOR_TAVDS(0x0) | \ + FTIM0_NOR_TEAHC(0xc)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ + FTIM1_NOR_TRAD_NOR(0xb) | \ + FTIM1_NOR_TSEQRAD_NOR(0x9)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x8) | \ + FTIM2_NOR_TWP(0x10)) +#define CONFIG_SYS_NOR_FTIM3 0 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) +#endif + +/* + * CPLD + */ +#define CONFIG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE + +#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) +#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* CPLD Timing parameters for IFC GPCM */ +#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ + FTIM0_GPCM_TEADC(0xf) | \ + FTIM0_GPCM_TEAHC(0xf)) +#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0xff)) +#define CONFIG_SYS_CPLD_FTIM3 0x0 + +/* IFC Timing Params */ +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET (1024 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x20000 +#endif + +/* FMan */ +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_CMD_MII +#define CONFIG_PHYLIB +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#define CONFIG_PHY_AQUANTIA + +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 + +#define QSGMII_PORT1_PHY_ADDR 0x4 +#define QSGMII_PORT2_PHY_ADDR 0x5 +#define QSGMII_PORT3_PHY_ADDR 0x6 +#define QSGMII_PORT4_PHY_ADDR 0x7 + +#define FM1_10GEC1_PHY_ADDR 0x1 + +#define CONFIG_ETHPRIME "FM1@DTSEC3" +#endif + +#endif /* __LS1043ARDB_H__ */ diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 9c8a8642e5..0011e720ea 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -9,8 +9,10 @@ #define CONFIG_REMAKE_ELF +#define CONFIG_FSL_LAYERSCAPE #define CONFIG_FSL_LSCH3 #define CONFIG_LS2085A +#define CONFIG_MP #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 @@ -18,12 +20,15 @@ #define CONFIG_ARM_ERRATA_828024 #define CONFIG_ARM_ERRATA_826974 -#include <asm/arch-fsl-lsch3/ls2085a_stream_id.h> -#include <asm/arch-fsl-lsch3/config.h> +#include <asm/arch/ls2085a_stream_id.h> +#include <asm/arch/config.h> #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) #define CONFIG_SYS_HAS_SERDES #endif +/* Link Definitions */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) + /* We need architecture specific misc initializations */ #define CONFIG_ARCH_MISC_INIT @@ -46,6 +51,7 @@ /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS /* new uImage format support */ #define CONFIG_FIT @@ -61,6 +67,7 @@ #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ +#define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h index 4cfcf98094..406d0e6d47 100644 --- a/include/configs/ls2085aqds.h +++ b/include/configs/ls2085aqds.h @@ -16,7 +16,7 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h index 583fed574a..f95d7b2732 100644 --- a/include/configs/ls2085ardb.h +++ b/include/configs/ls2085ardb.h @@ -18,7 +18,7 @@ unsigned long get_board_sys_clk(void); #endif -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ 133333333 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) @@ -331,6 +331,7 @@ unsigned long get_board_sys_clk(void); /* MAC/PHY configuration */ #ifdef CONFIG_FSL_MC_ENET #define CONFIG_PHYLIB_10G +#define CONFIG_PHY_AQUANTIA #define CONFIG_PHY_CORTINA #define CONFIG_PHYLIB #define CONFIG_SYS_CORTINA_FW_IN_NOR diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index 152e295778..fbaa6000bc 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -17,7 +17,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_REVISION_TAG #define CONFIG_SYS_NO_FLASH -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_FIT diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 9c53fb4ad8..10a6ce995f 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -3,7 +3,7 @@ * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * - * (C) Copyright 2009-2011 + * (C) Copyright 2009-2015 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> * esd electronic system design gmbh <www.esd.eu> * @@ -27,7 +27,7 @@ * Since the linker has to swallow that define, we must use a pure * hex number here! */ -#define CONFIG_SYS_TEXT_BASE 0x20002000 +#define CONFIG_SYS_TEXT_BASE 0x21F00000 /* * since a number of boards are not being listed in linux @@ -56,14 +56,13 @@ #define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */ #define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT /* * Hardware drivers */ -/* required until arch/arm/include/asm/arch-at91/at91sam9263.h is reworked */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP - /* general purpose I/O */ #define CONFIG_AT91_GPIO @@ -87,10 +86,17 @@ /* * Command line configuration. */ +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP + +#ifdef CONFIG_SYS_USE_NANDFLASH #define CONFIG_CMD_NAND -#define CONFIG_CMD_USB +#endif /* LED */ #define CONFIG_AT91_LED @@ -99,9 +105,12 @@ * SDRAM: 1 bank, min 32, max 128 MB * Initialized before u-boot gets started. */ +#define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ +#define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */ + #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0x20000000 /* ATMEL_BASE_CS1 */ -#define CONFIG_SYS_SDRAM_SIZE 0x02000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000) @@ -133,7 +142,7 @@ #ifdef CONFIG_CMD_NAND # define CONFIG_NAND_ATMEL # define CONFIG_SYS_MAX_NAND_DEVICE 1 -# define CONFIG_SYS_NAND_BASE 0x40000000 /* ATMEL_BASE_CS3 */ +# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ # define CONFIG_SYS_NAND_DBW_8 # define CONFIG_SYS_NAND_MASK_ALE (1 << 21) # define CONFIG_SYS_NAND_MASK_CLE (1 << 22) @@ -148,19 +157,6 @@ #define CONFIG_NET_RETRY_COUNT 20 #undef CONFIG_RESET_PHY_R -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - -/* CAN */ -#define CONFIG_AT91_CAN - /* hw-controller addresses */ #define CONFIG_ET1100_BASE 0x70000000 @@ -190,6 +186,8 @@ sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP #define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER /* * Size of malloc() pool diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index 0ee8e0d97c..f113302695 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -14,7 +14,7 @@ #define CONFIG_MX25 #define CONFIG_SYS_TEXT_BASE 0x81200000 #define CONFIG_MXC_GPIO -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_TIMER_RATE 32768 #define CONFIG_SYS_TIMER_COUNTER \ diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 41f518e49b..1b2f952975 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -19,7 +19,7 @@ #define CONFIG_MX35 #define CONFIG_DISPLAY_CPUINFO -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK /* Set TEXT at the beginning of the NOR flash */ #define CONFIG_SYS_TEXT_BASE 0xA0000000 diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 35c9346638..32cd58ef44 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -18,7 +18,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_TEXT_BASE 0x97800000 #include <asm/arch/imx-regs.h> diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index be37ce5342..fdb4134b13 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -23,7 +23,7 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 81af248696..37430f0a2a 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -23,7 +23,7 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_OF_LIBFDT diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 53fb4f79ef..54d3e3edd5 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -22,7 +22,7 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index f5fcd838ed..d915b883ce 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -23,7 +23,7 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index ba13178384..29bfbde3c5 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -45,7 +45,7 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_DISPLAY_CPUINFO -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK /* ATAGs */ #define CONFIG_CMDLINE_TAG diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index fc6aa9da2c..ffe4d81656 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -21,6 +21,7 @@ #define CONFIG_MXC_GPT_HCLK #define CONFIG_SYSCOUNTER_TIMER #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ +#define CONFIG_SYS_FSL_CLK /* Enable iomux-lpsr support */ #define CONFIG_IOMUX_LPSR diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 3c701587bf..648e48bcf4 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -94,6 +94,8 @@ "boot.scr fat 0 1;" \ "boot.cmd fat 0 1;" \ "exynos5422-odroidxu3.dtb fat 0 1;" \ + "exynos5422-odroidxu3-lite.dtb fat 0 1;" \ + "exynos5422-odroidxu4.dtb fat 0 1;" \ "boot part 0 1;" \ "root part 0 2\0" @@ -113,9 +115,19 @@ /* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */ #define CONFIG_MISC_COMMON +#define CONFIG_MISC_INIT_R #define CONFIG_SET_DFU_ALT_INFO #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) +/* Set soc_rev, soc_id, board_rev, boardname, fdtfile */ +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_ODROID_REV_AIN 9 +#define CONFIG_REVISION_TAG +#define CONFIG_BOARD_TYPES + +#undef CONFIG_SYS_BOARD +#define CONFIG_SYS_BOARD "odroid" + /* Define new extra env settings, including DFU settings */ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/openrd.h b/include/configs/openrd.h new file mode 100644 index 0000000000..62f15b7688 --- /dev/null +++ b/include/configs/openrd.h @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2009 + * Net Insight <www.netinsight.net> + * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> + * + * Based on sheevaplug.h: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_OPENRD_H +#define _CONFIG_OPENRD_H + +/* + * Version number information + */ +#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE +# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate" +#else +# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT +# define CONFIG_IDENT_STRING "\nOpenRD-Client" +# else +# ifdef CONFIG_BOARD_IS_OPENRD_BASE +# define CONFIG_IDENT_STRING "\nOpenRD-Base" +# else +# error Unknown OpenRD board specified +# endif +# endif +#endif + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_MACH_OPENRD_BASE /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SYS_THUMB_BUILD + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_IDE + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0x60000 +#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ +/* + * Environment is right behind U-Boot in flash. Make sure U-Boot + * doesn't grow into the environment area. + */ +#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ + "${x_bootcmd_usb}; bootm 0x6400000;" + +#define MTDIDS_DEFAULT "nand0=nand_mtd" +#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\ + "0x400000@0x100000(uImage),"\ + "0x1fb00000@0x500000(rootfs)" + +#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ + "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ + "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ + "x_bootcmd_usb=usb start\0" \ + "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \ + "mtdids="MTDIDS_DEFAULT"\0" \ + "mtdparts="MTDPARTS_DEFAULT"\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +# ifdef CONFIG_BOARD_IS_OPENRD_BASE +# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +# else +# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ +# endif +# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE +# define CONFIG_PHY_BASE_ADR 0x0 +# define PHY_NO "88E1121" +# else +# define CONFIG_PHY_BASE_ADR 0x8 +# define PHY_NO "88E1116" +# endif +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /*CONFIG_MVSATA_IDE*/ + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MVEBU_MMC +#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE +#endif /* CONFIG_CMD_MMC */ + +#endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 03eb185e16..433c409336 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -11,7 +11,6 @@ #define __CONFIG_H #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 46f5f0f70e..d83daa0255 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -11,7 +11,6 @@ #define __CONFIG_H #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #if defined(CONFIG_TWR_P1025) #define CONFIG_BOARDNAME "TWR-P1025" #define CONFIG_P1025 diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 17969952d1..8191fb2b8a 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -9,6 +9,7 @@ #define __CONFIG_H #define CONFIG_STM32F4 +#define CONFIG_SYS_THUMB_BUILD #define CONFIG_STM32F4DISCOVERY #define CONFIG_OF_LIBFDT diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 651c4c4935..68da23e8b7 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -19,9 +19,7 @@ #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ #endif -#ifndef CONFIG_ARM64 #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ -#endif #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 02b0e6351f..0ab69e665a 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -17,6 +17,7 @@ #define __CONFIG_H /* High Level Configuration Options */ +#define CONFIG_SYS_THUMB_BUILD #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP_COMMON /* Common ARM Erratas */ diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 6735055a61..6f6666281a 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -14,7 +14,7 @@ #define CONFIG_MX53 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_OF_LIBFDT #define CONFIG_MXC_GPIO diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index abd1e98d9b..a3ea2e0a1f 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -15,7 +15,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_MACH_TYPE 4146 diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index e6f3e28fe1..2acebf1a56 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -16,7 +16,7 @@ /* High Level Configuration Options */ #define CONFIG_MX35 #define CONFIG_MX35_HCLK_FREQ 24000000 -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_CACHELINE_SIZE 32 diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 32ee0fc149..36c11009fc 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -55,9 +55,7 @@ # define CONFIG_ARM_DCC # define CONFIG_CPU_ARMV8 #else -# if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1) -# define CONFIG_ZYNQ_SERIAL -# endif +# define CONFIG_ZYNQ_SERIAL #endif #define CONFIG_CONS_INDEX 0 diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index e476eb1b49..ed6023a7bf 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -18,7 +18,6 @@ #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 -#define CONFIG_ZYNQ_SERIAL_UART0 #define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_I2C0 #define CONFIG_SYS_I2C_ZYNQ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index ca5ef04302..f98101fc27 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -179,7 +179,10 @@ # define CONFIG_CMD_FS_GENERIC #endif +#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1) #define CONFIG_SYS_I2C_ZYNQ +#endif + /* I2C */ #if defined(CONFIG_SYS_I2C_ZYNQ) # define CONFIG_CMD_I2C @@ -329,7 +332,11 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#ifdef CONFIG_OF_CONTROL +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +#else +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif #endif /* Disable dcache for SPL just for sure */ diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h index 549a664ef5..b5ffafb561 100644 --- a/include/configs/zynq_microzed.h +++ b/include/configs/zynq_microzed.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) -#define CONFIG_ZYNQ_SERIAL_UART1 #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 diff --git a/include/configs/zynq_picozed.h b/include/configs/zynq_picozed.h index d116e05ac7..ffc73bd0e3 100644 --- a/include/configs/zynq_picozed.h +++ b/include/configs/zynq_picozed.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) -#define CONFIG_ZYNQ_SERIAL_UART1 #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index b6590547a9..468a6bc7bf 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) -#define CONFIG_ZYNQ_SERIAL_UART1 #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h index 7a1b8729e5..63224dd744 100644 --- a/include/configs/zynq_zc770.h +++ b/include/configs/zynq_zc770.h @@ -15,26 +15,20 @@ #define CONFIG_SYS_NO_FLASH #if defined(CONFIG_ZC770_XM010) -# define CONFIG_ZYNQ_SERIAL_UART1 # define CONFIG_ZYNQ_GEM0 # define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 # define CONFIG_ZYNQ_SDHCI0 # define CONFIG_ZYNQ_SPI #elif defined(CONFIG_ZC770_XM011) -# define CONFIG_ZYNQ_SERIAL_UART1 #elif defined(CONFIG_ZC770_XM012) -# define CONFIG_ZYNQ_SERIAL_UART1 # undef CONFIG_SYS_NO_FLASH #elif defined(CONFIG_ZC770_XM013) -# define CONFIG_ZYNQ_SERIAL_UART0 # define CONFIG_ZYNQ_GEM1 # define CONFIG_ZYNQ_GEM_PHY_ADDR1 7 -#else -# define CONFIG_ZYNQ_SERIAL_UART0 #endif #include <configs/zynq-common.h> diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h index 946de953e4..6ec6117f17 100644 --- a/include/configs/zynq_zed.h +++ b/include/configs/zynq_zed.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024) -#define CONFIG_ZYNQ_SERIAL_UART1 #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h index 191f2a5f30..e2270cd2ea 100644 --- a/include/configs/zynq_zybo.h +++ b/include/configs/zynq_zybo.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024) -#define CONFIG_ZYNQ_SERIAL_UART1 #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 886a44c134..327de3486b 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -25,6 +25,7 @@ enum uclass_id { UCLASS_SIMPLE_BUS, /* bus with child devices */ /* U-Boot uclasses start here - in alphabetical order */ + UCLASS_ADC, /* Analog-to-digital converter */ UCLASS_CLK, /* Clock source, e.g. used by peripherals */ UCLASS_CPU, /* CPU, typically part of an SoC */ UCLASS_CROS_EC, /* Chrome OS EC */ @@ -42,6 +43,7 @@ enum uclass_id { UCLASS_MISC, /* Miscellaneous device */ UCLASS_MMC, /* SD / MMC card or chip */ UCLASS_MOD_EXP, /* RSA Mod Exp device */ + UCLASS_MTD, /* Memory Technology Device (MTD) device */ UCLASS_PCH, /* x86 platform controller hub */ UCLASS_PCI, /* PCI bus */ UCLASS_PCI_GENERIC, /* Generic PCI bus device */ diff --git a/include/fdtdec.h b/include/fdtdec.h index 2de6dda04c..0e36664dca 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -490,6 +490,19 @@ s32 fdtdec_get_int(const void *blob, int node, const char *prop_name, s32 default_val); /** + * Unsigned version of fdtdec_get_int. The property must have at least + * 4 bytes of data. The value of the first cell is returned. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param default_val default value to return if the property is not found + * @return unsigned integer value, if found, or default_val if not + */ +unsigned int fdtdec_get_uint(const void *blob, int node, const char *prop_name, + unsigned int default_val); + +/** * Get a variable-sized number from a property * * This reads a number from one or more cells. @@ -628,7 +641,16 @@ int fdtdec_get_alias_seq(const void *blob, const char *base, int node, int *seqp); /** - * Get the offset of the given chosen node + * Get a property from the /chosen node + * + * @param blob Device tree blob (if NULL, then NULL is returned) + * @param name Property name to look up + * @return Value of property, or NULL if it does not exist + */ +const char *fdtdec_get_chosen_prop(const void *blob, const char *name); + +/** + * Get the offset of the given /chosen node * * This looks up a property in /chosen containing the path to another node, * then finds the offset of that node. diff --git a/include/flash.h b/include/flash.h index 5754cf9773..13e03842c8 100644 --- a/include/flash.h +++ b/include/flash.h @@ -41,6 +41,9 @@ typedef struct { ulong addr_unlock2; /* unlock address 2 for AMD flash roms */ const char *name; /* human-readable name */ #endif +#ifdef CONFIG_MTD + struct mtd_info *mtd; +#endif } flash_info_t; extern flash_info_t flash_info[]; /* info for FLASH chips */ diff --git a/include/fm_eth.h b/include/fm_eth.h index 3e1b9f4281..d43f801fdc 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -45,8 +45,10 @@ enum fm_eth_type { #ifdef CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000) #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) +#if (CONFIG_SYS_NUM_FMAN == 2) #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000) #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000) +#endif #else #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120) #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000) @@ -89,6 +91,7 @@ enum fm_eth_type { offsetof(struct ccsr_fman, memac[n-1]),\ } #else +#if (CONFIG_SYS_NUM_FMAN == 2) #define FM_TGEC_INFO_INITIALIZER(idx, n) \ { \ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \ @@ -101,6 +104,20 @@ enum fm_eth_type { .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ offsetof(struct ccsr_fman, memac[n-1+8]),\ } +#else +#define FM_TGEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_10G_E, \ + .port = FM##idx##_10GEC##n, \ + .rx_port_id = RX_PORT_10G_BASE + n - 1, \ + .tx_port_id = TX_PORT_10G_BASE + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1+8]),\ +} +#endif #endif #if (CONFIG_SYS_NUM_FM1_10GEC >= 3) diff --git a/include/fsl_csu.h b/include/fsl_csu.h new file mode 100644 index 0000000000..f4d97fb605 --- /dev/null +++ b/include/fsl_csu.h @@ -0,0 +1,34 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __FSL_CSU_H__ +#define __FSL_CSU_H__ + +enum csu_cslx_access { + CSU_NS_SUP_R = 0x08, + CSU_NS_SUP_W = 0x80, + CSU_NS_SUP_RW = 0x88, + CSU_NS_USER_R = 0x04, + CSU_NS_USER_W = 0x40, + CSU_NS_USER_RW = 0x44, + CSU_S_SUP_R = 0x02, + CSU_S_SUP_W = 0x20, + CSU_S_SUP_RW = 0x22, + CSU_S_USER_R = 0x01, + CSU_S_USER_W = 0x10, + CSU_S_USER_RW = 0x11, + CSU_ALL_RW = 0xff, +}; + +struct csu_ns_dev { + unsigned long ind; + uint32_t val; +}; + +void enable_layerscape_ns_access(void); + +#endif diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index e5b6e03c8f..c79fce0898 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -324,6 +324,8 @@ typedef struct memctl_options_s { unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ /* SREN - self-refresh during sleep */ unsigned int self_refresh_in_sleep; + /* SR_IE - Self-refresh interrupt enable */ + unsigned int self_refresh_interrupt_en; unsigned int dynamic_power; /* DYN_PWR */ /* memory data width to use (16-bit, 32-bit, 64-bit) */ unsigned int data_bus_width; diff --git a/include/fsl_dtsec.h b/include/fsl_dtsec.h new file mode 100644 index 0000000000..41b8398ecd --- /dev/null +++ b/include/fsl_dtsec.h @@ -0,0 +1,231 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DTSEC_H__ +#define __DTSEC_H__ + +#include <asm/types.h> + +struct dtsec { + u32 tsec_id; /* controller ID and version */ + u32 tsec_id2; /* controller ID and configuration */ + u32 ievent; /* interrupt event */ + u32 imask; /* interrupt mask */ + u32 res0; + u32 ecntrl; /* ethernet control and configuration */ + u32 ptv; /* pause time value */ + u32 tbipa; /* TBI PHY address */ + u32 res1[8]; + u32 tctrl; /* Transmit control register */ + u32 res2[3]; + u32 rctrl; /* Receive control register */ + u32 res3[11]; + u32 igaddr[8]; /* Individual group address */ + u32 gaddr[8]; /* group address */ + u32 res4[16]; + u32 maccfg1; /* MAC configuration register 1 */ + u32 maccfg2; /* MAC configuration register 2 */ + u32 ipgifg; /* inter-packet/inter-frame gap */ + u32 hafdup; /* half-duplex control */ + u32 maxfrm; /* Maximum frame size */ + u32 res5[3]; + u32 miimcfg; /* MII management configuration */ + u32 miimcom; /* MII management command */ + u32 miimadd; /* MII management address */ + u32 miimcon; /* MII management control */ + u32 miimstat; /* MII management status */ + u32 miimind; /* MII management indicator */ + u32 res6; + u32 ifstat; /* Interface status */ + u32 macstnaddr1; /* MAC station address 1 */ + u32 macstnaddr2; /* MAC station address 2 */ + u32 res7[46]; + /* transmit and receive counter */ + u32 tr64; /* Tx and Rx 64 bytes frame */ + u32 tr127; /* Tx and Rx 65 to 127 bytes frame */ + u32 tr255; /* Tx and Rx 128 to 255 bytes frame */ + u32 tr511; /* Tx and Rx 256 to 511 bytes frame */ + u32 tr1k; /* Tx and Rx 512 to 1023 bytes frame */ + u32 trmax; /* Tx and Rx 1024 to 1518 bytes frame */ + u32 trmgv; /* Tx and Rx 1519 to 1522 good VLAN frame */ + /* receive counters */ + u32 rbyt; /* Receive byte counter */ + u32 rpkt; /* Receive packet counter */ + u32 rfcs; /* Receive FCS error */ + u32 rmca; /* Receive multicast packet */ + u32 rbca; /* Receive broadcast packet */ + u32 rxcf; /* Receive control frame */ + u32 rxpf; /* Receive pause frame */ + u32 rxuo; /* Receive unknown OP code */ + u32 raln; /* Receive alignment error */ + u32 rflr; /* Receive frame length error */ + u32 rcde; /* Receive code error */ + u32 rcse; /* Receive carrier sense error */ + u32 rund; /* Receive undersize packet */ + u32 rovr; /* Receive oversize packet */ + u32 rfrg; /* Receive fragments counter */ + u32 rjbr; /* Receive jabber counter */ + u32 rdrp; /* Receive drop counter */ + /* transmit counters */ + u32 tbyt; /* Transmit byte counter */ + u32 tpkt; /* Transmit packet */ + u32 tmca; /* Transmit multicast packet */ + u32 tbca; /* Transmit broadcast packet */ + u32 txpf; /* Transmit pause control frame */ + u32 tdfr; /* Transmit deferral packet */ + u32 tedf; /* Transmit excessive deferral pkt */ + u32 tscl; /* Transmit single collision pkt */ + u32 tmcl; /* Transmit multiple collision pkt */ + u32 tlcl; /* Transmit late collision pkt */ + u32 txcl; /* Transmit excessive collision */ + u32 tncl; /* Transmit total collision */ + u32 res8; + u32 tdrp; /* Transmit drop frame */ + u32 tjbr; /* Transmit jabber frame */ + u32 tfcs; /* Transmit FCS error */ + u32 txcf; /* Transmit control frame */ + u32 tovr; /* Transmit oversize frame */ + u32 tund; /* Transmit undersize frame */ + u32 tfrg; /* Transmit fragments frame */ + /* counter controls */ + u32 car1; /* carry register 1 */ + u32 car2; /* carry register 2 */ + u32 cam1; /* carry register 1 mask */ + u32 cam2; /* carry register 2 mask */ + u32 res9[80]; +}; + + +/* TBI register addresses */ +#define TBI_CR 0x00 +#define TBI_SR 0x01 +#define TBI_ANA 0x04 +#define TBI_ANLPBPA 0x05 +#define TBI_ANEX 0x06 +#define TBI_TBICON 0x11 + +/* TBI MDIO register bit fields*/ +#define TBICON_CLK_SELECT 0x0020 +#define TBIANA_ASYMMETRIC_PAUSE 0x0100 +#define TBIANA_SYMMETRIC_PAUSE 0x0080 +#define TBIANA_HALF_DUPLEX 0x0040 +#define TBIANA_FULL_DUPLEX 0x0020 +#define TBICR_PHY_RESET 0x8000 +#define TBICR_ANEG_ENABLE 0x1000 +#define TBICR_RESTART_ANEG 0x0200 +#define TBICR_FULL_DUPLEX 0x0100 +#define TBICR_SPEED1_SET 0x0040 + +/* IEVENT - interrupt events register */ +#define IEVENT_BABR 0x80000000 /* Babbling receive error */ +#define IEVENT_RXC 0x40000000 /* pause control frame received */ +#define IEVENT_MSRO 0x04000000 /* MIB counter overflow */ +#define IEVENT_GTSC 0x02000000 /* Graceful transmit stop complete */ +#define IEVENT_BABT 0x01000000 /* Babbling transmit error */ +#define IEVENT_TXC 0x00800000 /* control frame transmitted */ +#define IEVENT_TXE 0x00400000 /* Transmit channel error */ +#define IEVENT_LC 0x00040000 /* Late collision occurred */ +#define IEVENT_CRL 0x00020000 /* Collision retry exceed limit */ +#define IEVENT_XFUN 0x00010000 /* Transmit FIFO underrun */ +#define IEVENT_ABRT 0x00008000 /* Transmit packet abort */ +#define IEVENT_MMRD 0x00000400 /* MII management read complete */ +#define IEVENT_MMWR 0x00000200 /* MII management write complete */ +#define IEVENT_GRSC 0x00000100 /* Graceful stop complete */ +#define IEVENT_TDPE 0x00000002 /* Internal data parity error on Tx */ +#define IEVENT_RDPE 0x00000001 /* Internal data parity error on Rx */ + +#define IEVENT_CLEAR_ALL 0xffffffff + +/* IMASK - interrupt mask register */ +#define IMASK_BREN 0x80000000 /* Babbling receive enable */ +#define IMASK_RXCEN 0x40000000 /* receive control enable */ +#define IMASK_MSROEN 0x04000000 /* MIB counter overflow enable */ +#define IMASK_GTSCEN 0x02000000 /* Graceful Tx stop complete enable */ +#define IMASK_BTEN 0x01000000 /* Babbling transmit error enable */ +#define IMASK_TXCEN 0x00800000 /* control frame transmitted enable */ +#define IMASK_TXEEN 0x00400000 /* Transmit channel error enable */ +#define IMASK_LCEN 0x00040000 /* Late collision interrupt enable */ +#define IMASK_CRLEN 0x00020000 /* Collision retry exceed limit */ +#define IMASK_XFUNEN 0x00010000 /* Transmit FIFO underrun enable */ +#define IMASK_ABRTEN 0x00008000 /* Transmit packet abort enable */ +#define IMASK_MMRDEN 0x00000400 /* MII management read complete enable */ +#define IMASK_MMWREN 0x00000200 /* MII management write complete enable */ +#define IMASK_GRSCEN 0x00000100 /* Graceful stop complete interrupt enable */ +#define IMASK_TDPEEN 0x00000002 /* Internal data parity error on Tx enable */ +#define IMASK_RDPEEN 0x00000001 /* Internal data parity error on Rx enable */ + +#define IMASK_MASK_ALL 0x00000000 + +/* ECNTRL - ethernet control register */ +#define ECNTRL_CFG_RO 0x80000000 /* GMIIM, RPM, R100M, SGMIIM bits are RO */ +#define ECNTRL_CLRCNT 0x00004000 /* clear all statistics */ +#define ECNTRL_AUTOZ 0x00002000 /* auto zero MIB counter */ +#define ECNTRL_STEN 0x00001000 /* enable internal counters to update */ +#define ECNTRL_GMIIM 0x00000040 /* 1- GMII or RGMII interface mode */ +#define ECNTRL_TBIM 0x00000020 /* 1- Ten-bit interface mode */ +#define ECNTRL_RPM 0x00000010 /* 1- RGMII reduced-pin mode */ +#define ECNTRL_R100M 0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps + 0- RGMII 10 Mbps, SGMII 10 Mbps */ +#define ECNTRL_SGMIIM 0x00000002 /* 1- SGMII interface mode */ +#define ECNTRL_TBIM 0x00000020 /* 1- TBI Interface mode (for SGMII) */ + +#define ECNTRL_DEFAULT (ECNTRL_TBIM | ECNTRL_R100M | ECNTRL_SGMIIM) + +/* TCTRL - Transmit control register */ +#define TCTRL_THDF 0x00000800 /* Transmit half-duplex flow control */ +#define TCTRL_TTSE 0x00000040 /* Transmit time-stamp enable */ +#define TCTRL_GTS 0x00000020 /* Graceful transmit stop */ +#define TCTRL_RFC_PAUSE 0x00000010 /* Receive flow control pause frame */ + +/* RCTRL - Receive control register */ +#define RCTRL_PAL_MASK 0x001f0000 /* packet alignment padding length */ +#define RCTRL_PAL_SHIFT 16 +#define RCTRL_CFA 0x00008000 /* control frame accept enable */ +#define RCTRL_GHTX 0x00000800 /* group address hash table extend */ +#define RCTRL_RTSE 0x00000040 /* receive 1588 time-stamp enable */ +#define RCTRL_GRS 0x00000020 /* graceful receive stop */ +#define RCTRL_BC_REJ 0x00000010 /* broadcast frame reject */ +#define RCTRL_BC_MPROM 0x00000008 /* all multicast/broadcast frames received */ +#define RCTRL_RSF 0x00000004 /* receive short frame(17~63 bytes) enable */ +#define RCTRL_EMEN 0x00000002 /* Exact match MAC address enable */ +#define RCTRL_UPROM 0x00000001 /* all unicast frame received */ + +/* MACCFG1 - MAC configuration 1 register */ +#define MACCFG1_SOFT_RST 0x80000000 /* place the MAC in reset */ +#define MACCFG1_RST_RXMAC 0x00080000 /* reset receive MAC control block */ +#define MACCFG1_RST_TXMAC 0x00040000 /* reet transmit MAC control block */ +#define MACCFG1_RST_RXFUN 0x00020000 /* reset receive function block */ +#define MACCFG1_RST_TXFUN 0x00010000 /* reset transmit function block */ +#define MACCFG1_LOOPBACK 0x00000100 /* MAC loopback */ +#define MACCFG1_RX_FLOW 0x00000020 /* Receive flow */ +#define MACCFG1_TX_FLOW 0x00000010 /* Transmit flow */ +#define MACCFG1_SYNC_RXEN 0x00000008 /* Frame reception enabled */ +#define MACCFG1_RX_EN 0x00000004 /* Rx enable */ +#define MACCFG1_SYNC_TXEN 0x00000002 /* Frame transmission is enabled */ +#define MACCFG1_TX_EN 0x00000001 /* Tx enable */ +#define MACCFG1_RXTX_EN (MACCFG1_RX_EN | MACCFG1_TX_EN) + +/* MACCFG2 - MAC configuration 2 register */ +#define MACCFG2_PRE_LEN_MASK 0x0000f000 /* preamble length */ +#define MACCFG2_PRE_LEN(x) ((x << 12) & MACCFG2_PRE_LEN_MASK) +#define MACCFG2_IF_MODE_MASK 0x00000300 +#define MACCFG2_IF_MODE_NIBBLE 0x00000100 /* MII, 10/100 Mbps MII/RMII */ +#define MACCFG2_IF_MODE_BYTE 0x00000200 /* GMII/TBI, 1000 GMII/TBI */ +#define MACCFG2_PRE_RX_EN 0x00000080 /* receive preamble enable */ +#define MACCFG2_PRE_TX_EN 0x00000040 /* tx preable enable */ +#define MACCFG2_HUGE_FRAME 0x00000020 /* >= max frame len enable */ +#define MACCFG2_LEN_CHECK 0x00000010 /* MAC check frame's length Rx */ +#define MACCFG2_MAG_EN 0x00000008 /* magic packet enable */ +#define MACCFG2_PAD_CRC 0x00000004 /* pad and append CRC */ +#define MACCFG2_CRC_EN 0x00000002 /* MAC appends a CRC on all frames */ +#define MACCFG2_FULL_DUPLEX 0x00000001 /* Full deplex mode */ + +struct fsl_enet_mac; + +void init_dtsec(struct fsl_enet_mac *mac, void *base, void *phyregs, + int max_rx_len); + +#endif diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 0d00b7dfdb..aa1b4cf1e4 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -166,7 +166,7 @@ #define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */ struct fsl_esdhc_cfg { -#ifdef CONFIG_LS2085A +#ifdef CONFIG_FSL_LAYERSCAPE u64 esdhc_base; #else u32 esdhc_base; diff --git a/include/fsl_fman.h b/include/fsl_fman.h new file mode 100644 index 0000000000..4d04415ba8 --- /dev/null +++ b/include/fsl_fman.h @@ -0,0 +1,463 @@ +/* + * MPC85xx Internal Memory Map + * + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_FMAN_H__ +#define __FSL_FMAN_H__ + +#include <asm/types.h> + +typedef struct fm_bmi_common { + u32 fmbm_init; /* BMI initialization */ + u32 fmbm_cfg1; /* BMI configuration1 */ + u32 fmbm_cfg2; /* BMI configuration2 */ + u32 res0[0x5]; + u32 fmbm_ievr; /* interrupt event register */ + u32 fmbm_ier; /* interrupt enable register */ + u32 fmbm_ifr; /* interrupt force register */ + u32 res1[0x5]; + u32 fmbm_arb[0x8]; /* BMI arbitration */ + u32 res2[0x28]; + u32 fmbm_gde; /* global debug enable */ + u32 fmbm_pp[0x3f]; /* BMI port parameters */ + u32 res3; + u32 fmbm_pfs[0x3f]; /* BMI port FIFO size */ + u32 res4; + u32 fmbm_ppid[0x3f];/* port partition ID */ +} fm_bmi_common_t; + +typedef struct fm_qmi_common { + u32 fmqm_gc; /* general configuration register */ + u32 res0; + u32 fmqm_eie; /* error interrupt event register */ + u32 fmqm_eien; /* error interrupt enable register */ + u32 fmqm_eif; /* error interrupt force register */ + u32 fmqm_ie; /* interrupt event register */ + u32 fmqm_ien; /* interrupt enable register */ + u32 fmqm_if; /* interrupt force register */ + u32 fmqm_gs; /* global status register */ + u32 fmqm_ts; /* task status register */ + u32 fmqm_etfc; /* enqueue total frame counter */ + u32 fmqm_dtfc; /* dequeue total frame counter */ + u32 fmqm_dc0; /* dequeue counter 0 */ + u32 fmqm_dc1; /* dequeue counter 1 */ + u32 fmqm_dc2; /* dequeue counter 2 */ + u32 fmqm_dc3; /* dequeue counter 3 */ + u32 fmqm_dfnoc; /* dequeue FQID not override counter */ + u32 fmqm_dfcc; /* dequeue FQID from context counter */ + u32 fmqm_dffc; /* dequeue FQID from FD counter */ + u32 fmqm_dcc; /* dequeue confirm counter */ + u32 res1[0xc]; + u32 fmqm_dtrc; /* debug trap configuration register */ + u32 fmqm_efddd; /* enqueue frame descriptor dynamic debug */ + u32 res3[0x2]; + u32 res4[0xdc]; /* missing debug regs */ +} fm_qmi_common_t; + +typedef struct fm_bmi { + u8 res[1024]; +} fm_bmi_t; + +typedef struct fm_qmi { + u8 res[1024]; +} fm_qmi_t; + +struct fm_bmi_rx_port { + u32 fmbm_rcfg; /* Rx configuration */ + u32 fmbm_rst; /* Rx status */ + u32 fmbm_rda; /* Rx DMA attributes */ + u32 fmbm_rfp; /* Rx FIFO parameters */ + u32 fmbm_rfed; /* Rx frame end data */ + u32 fmbm_ricp; /* Rx internal context parameters */ + u32 fmbm_rim; /* Rx internal margins */ + u32 fmbm_rebm; /* Rx external buffer margins */ + u32 fmbm_rfne; /* Rx frame next engine */ + u32 fmbm_rfca; /* Rx frame command attributes */ + u32 fmbm_rfpne; /* Rx frame parser next engine */ + u32 fmbm_rpso; /* Rx parse start offset */ + u32 fmbm_rpp; /* Rx policer profile */ + u32 fmbm_rccb; /* Rx coarse classification base */ + u32 res1[0x2]; + u32 fmbm_rprai[0x8]; /* Rx parse results array Initialization */ + u32 fmbm_rfqid; /* Rx frame queue ID */ + u32 fmbm_refqid; /* Rx error frame queue ID */ + u32 fmbm_rfsdm; /* Rx frame status discard mask */ + u32 fmbm_rfsem; /* Rx frame status error mask */ + u32 fmbm_rfene; /* Rx frame enqueue next engine */ + u32 res2[0x23]; + u32 fmbm_ebmpi[0x8]; /* buffer manager pool information */ + u32 fmbm_acnt[0x8]; /* allocate counter */ + u32 res3[0x8]; + u32 fmbm_cgm[0x8]; /* congestion group map */ + u32 fmbm_mpd; /* BMan pool depletion */ + u32 res4[0x1F]; + u32 fmbm_rstc; /* Rx statistics counters */ + u32 fmbm_rfrc; /* Rx frame counters */ + u32 fmbm_rfbc; /* Rx bad frames counter */ + u32 fmbm_rlfc; /* Rx large frames counter */ + u32 fmbm_rffc; /* Rx filter frames counter */ + u32 fmbm_rfdc; /* Rx frame discard counter */ + u32 fmbm_rfldec; /* Rx frames list DMA error counter */ + u32 fmbm_rodc; /* Rx out of buffers discard counter */ + u32 fmbm_rbdc; /* Rx buffers deallocate counter */ + u32 res5[0x17]; + u32 fmbm_rpc; /* Rx performance counters */ + u32 fmbm_rpcp; /* Rx performance count parameters */ + u32 fmbm_rccn; /* Rx cycle counter */ + u32 fmbm_rtuc; /* Rx tasks utilization counter */ + u32 fmbm_rrquc; /* Rx receive queue utilization counter */ + u32 fmbm_rduc; /* Rx DMA utilization counter */ + u32 fmbm_rfuc; /* Rx FIFO utilization counter */ + u32 fmbm_rpac; /* Rx pause activation counter */ + u32 res6[0x18]; + u32 fmbm_rdbg; /* Rx debug configuration */ +}; + +/* FMBM_RCFG - Rx configuration */ +#define FMBM_RCFG_EN 0x80000000 /* port is enabled to receive data */ +#define FMBM_RCFG_FDOVR 0x02000000 /* frame discard override */ +#define FMBM_RCFG_IM 0x01000000 /* independent mode */ + +/* FMBM_RST - Rx status */ +#define FMBM_RST_BSY 0x80000000 /* Rx port is busy */ + +/* FMBM_RFCA - Rx frame command attributes */ +#define FMBM_RFCA_ORDER 0x80000000 +#define FMBM_RFCA_MR_MASK 0x003f0000 +#define FMBM_RFCA_MR(x) ((x << 16) & FMBM_RFCA_MR_MASK) + +/* FMBM_RSTC - Rx statistics */ +#define FMBM_RSTC_EN 0x80000000 /* statistics counters enable */ + +struct fm_bmi_tx_port { + u32 fmbm_tcfg; /* Tx configuration */ + u32 fmbm_tst; /* Tx status */ + u32 fmbm_tda; /* Tx DMA attributes */ + u32 fmbm_tfp; /* Tx FIFO parameters */ + u32 fmbm_tfed; /* Tx frame end data */ + u32 fmbm_ticp; /* Tx internal context parameters */ + u32 fmbm_tfne; /* Tx frame next engine */ + u32 fmbm_tfca; /* Tx frame command attributes */ + u32 fmbm_tcfqid;/* Tx confirmation frame queue ID */ + u32 fmbm_tfeqid;/* Tx error frame queue ID */ + u32 fmbm_tfene; /* Tx frame enqueue next engine */ + u32 fmbm_trlmts;/* Tx rate limiter scale */ + u32 fmbm_trlmt; /* Tx rate limiter */ + u32 res0[0x73]; + u32 fmbm_tstc; /* Tx statistics counters */ + u32 fmbm_tfrc; /* Tx frame counter */ + u32 fmbm_tfdc; /* Tx frames discard counter */ + u32 fmbm_tfledc;/* Tx frame length error discard counter */ + u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */ + u32 fmbm_tbdc; /* Tx buffers deallocate counter */ + u32 res1[0x1a]; + u32 fmbm_tpc; /* Tx performance counters */ + u32 fmbm_tpcp; /* Tx performance count parameters */ + u32 fmbm_tccn; /* Tx cycle counter */ + u32 fmbm_ttuc; /* Tx tasks utilization counter */ + u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */ + u32 fmbm_tduc; /* Tx DMA utilization counter */ + u32 fmbm_tfuc; /* Tx FIFO utilization counter */ + u32 res2[0x19]; + u32 fmbm_tdcfg; /* Tx debug configuration */ +}; + +/* FMBM_TCFG - Tx configuration */ +#define FMBM_TCFG_EN 0x80000000 /* port is enabled to transmit data */ +#define FMBM_TCFG_IM 0x01000000 /* independent mode enable */ + +/* FMBM_TST - Tx status */ +#define FMBM_TST_BSY 0x80000000 /* Tx port is busy */ + +/* FMBM_TFCA - Tx frame command attributes */ +#define FMBM_TFCA_ORDER 0x80000000 +#define FMBM_TFCA_MR_MASK 0x003f0000 +#define FMBM_TFCA_MR(x) ((x << 16) & FMBM_TFCA_MR_MASK) + +/* FMBM_TSTC - Tx statistics counters */ +#define FMBM_TSTC_EN 0x80000000 + +/* FMBM_INIT - BMI initialization register */ +#define FMBM_INIT_START 0x80000000 /* init internal buffers */ + +/* FMBM_CFG1 - BMI configuration 1 */ +#define FMBM_CFG1_FBPS_MASK 0x03ff0000 /* Free buffer pool size */ +#define FMBM_CFG1_FBPS_SHIFT 16 +#define FMBM_CFG1_FBPO_MASK 0x000003ff /* Free buffer pool offset */ + +/* FMBM_IEVR - interrupt event */ +#define FMBM_IEVR_PEC 0x80000000 /* pipeline table ECC err detected */ +#define FMBM_IEVR_LEC 0x40000000 /* linked list RAM ECC error */ +#define FMBM_IEVR_SEC 0x20000000 /* statistics count RAM ECC error */ +#define FMBM_IEVR_CLEAR_ALL (FMBM_IEVR_PEC | FMBM_IEVR_LEC | FMBM_IEVR_SEC) + +/* FMBM_IER - interrupt enable */ +#define FMBM_IER_PECE 0x80000000 /* PEC interrupt enable */ +#define FMBM_IER_LECE 0x40000000 /* LEC interrupt enable */ +#define FMBM_IER_SECE 0x20000000 /* SEC interrupt enable */ + +#define FMBM_IER_DISABLE_ALL 0x00000000 + +/* FMBM_PP - BMI Port Parameters */ +#define FMBM_PP_MXT_MASK 0x3f000000 /* Max # tasks */ +#define FMBM_PP_MXT(x) (((x-1) << 24) & FMBM_PP_MXT_MASK) +#define FMBM_PP_MXD_MASK 0x00000f00 /* Max DMA */ +#define FMBM_PP_MXD(x) (((x-1) << 8) & FMBM_PP_MXD_MASK) + +/* FMBM_PFS - BMI Port FIFO Size */ +#define FMBM_PFS_IFSZ_MASK 0x000003ff /* Internal Fifo Size */ +#define FMBM_PFS_IFSZ(x) (x & FMBM_PFS_IFSZ_MASK) + +/* FMQM_GC - global configuration */ +#define FMQM_GC_ENQ_EN 0x80000000 /* enqueue enable */ +#define FMQM_GC_DEQ_EN 0x40000000 /* dequeue enable */ +#define FMQM_GC_STEN 0x10000000 /* enable global stat counters */ +#define FMQM_GC_ENQ_THR_MASK 0x00003f00 /* max number of enqueue Tnum */ +#define FMQM_GC_ENQ(x) ((x << 8) & FMQM_GC_ENQ_THR_MAS) +#define FMQM_GC_DEQ_THR_MASK 0x0000003f /* max number of dequeue Tnum */ +#define FMQM_GC_DEQ(x) (x & FMQM_GC_DEQ_THR_MASK) + +/* FMQM_EIE - error interrupt event register */ +#define FMQM_EIE_DEE 0x80000000 /* double-bit ECC error */ +#define FMQM_EIE_DFUPE 0x40000000 /* dequeue from unknown PortID */ +#define FMQM_EIE_CLEAR_ALL (FMQM_EIE_DEE | FMQM_EIE_DFUPE) + +/* FMQM_EIEN - error interrupt enable register */ +#define FMQM_EIEN_DEEN 0x80000000 /* double-bit ECC error */ +#define FMQM_EIEN_DFUPEN 0x40000000 /* dequeue from unknown PortID */ +#define FMQM_EIEN_DISABLE_ALL 0x00000000 + +/* FMQM_IE - interrupt event register */ +#define FMQM_IE_SEE 0x80000000 /* single-bit ECC error detected */ +#define FMQM_IE_CLEAR_ALL FMQM_IE_SEE + +/* FMQM_IEN - interrupt enable register */ +#define FMQM_IEN_SEE 0x80000000 /* single-bit ECC err IRQ enable */ +#define FMQM_IEN_DISABLE_ALL 0x00000000 + +/* NIA - next invoked action */ +#define NIA_ENG_RISC 0x00000000 +#define NIA_ENG_MASK 0x007c0000 + +/* action code */ +#define NIA_RISC_AC_CC 0x00000006 +#define NIA_RISC_AC_IM_TX 0x00000008 /* independent mode Tx */ +#define NIA_RISC_AC_IM_RX 0x0000000a /* independent mode Rx */ +#define NIA_RISC_AC_HC 0x0000000c + +typedef struct fm_parser { + u8 res[1024]; +} fm_parser_t; + +typedef struct fm_policer { + u8 res[4*1024]; +} fm_policer_t; + +typedef struct fm_keygen { + u8 res[4*1024]; +} fm_keygen_t; + +typedef struct fm_dma { + u32 fmdmsr; /* status register */ + u32 fmdmmr; /* mode register */ + u32 fmdmtr; /* bus threshold register */ + u32 fmdmhy; /* bus hysteresis register */ + u32 fmdmsetr; /* SOS emergency threshold register */ + u32 fmdmtah; /* transfer bus address high register */ + u32 fmdmtal; /* transfer bus address low register */ + u32 fmdmtcid; /* transfer bus communication ID register */ + u32 fmdmra; /* DMA bus internal ram address register */ + u32 fmdmrd; /* DMA bus internal ram data register */ + u32 res0[0xb]; + u32 fmdmdcr; /* debug counter */ + u32 fmdmemsr; /* emrgency smoother register */ + u32 res1; + u32 fmdmplr[32]; /* FM DMA PID-LIODN # register */ + u32 res[0x3c8]; +} fm_dma_t; + +/* FMDMSR - Fman DMA status register */ +#define FMDMSR_CMDQNE 0x10000000 /* command queue not empty */ +#define FMDMSR_BER 0x08000000 /* bus err event occurred on bus */ +#define FMDMSR_RDB_ECC 0x04000000 /* read buffer ECC error */ +#define FMDMSR_WRB_SECC 0x02000000 /* write buf ECC err sys side */ +#define FMDMSR_WRB_FECC 0x01000000 /* write buf ECC err Fman side */ +#define FMDMSR_DPEXT_SECC 0x00800000 /* DP external ECC err sys side */ +#define FMDMSR_DPEXT_FECC 0x00400000 /* DP external ECC err Fman side */ +#define FMDMSR_DPDAT_SECC 0x00200000 /* DP data ECC err on sys side */ +#define FMDMSR_DPDAT_FECC 0x00100000 /* DP data ECC err on Fman side */ +#define FMDMSR_SPDAT_FECC 0x00080000 /* SP data ECC error Fman side */ + +#define FMDMSR_CLEAR_ALL (FMDMSR_BER | FMDMSR_RDB_ECC \ + | FMDMSR_WRB_SECC | FMDMSR_WRB_FECC \ + | FMDMSR_DPEXT_SECC | FMDMSR_DPEXT_FECC \ + | FMDMSR_DPDAT_SECC | FMDMSR_DPDAT_FECC \ + | FMDMSR_SPDAT_FECC) + +/* FMDMMR - FMan DMA mode register */ +#define FMDMMR_SBER 0x10000000 /* stop the DMA if a bus error */ + +typedef struct fm_fpm { + u32 fpmtnc; /* TNUM control */ + u32 fpmprc; /* Port_ID control */ + u32 res0; + u32 fpmflc; /* flush control */ + u32 fpmdis1; /* dispatch thresholds1 */ + u32 fpmdis2; /* dispatch thresholds2 */ + u32 fmepi; /* error pending interrupts */ + u32 fmrie; /* rams interrupt enable */ + u32 fpmfcevent[0x4];/* FMan controller event 0-3 */ + u32 res1[0x4]; + u32 fpmfcmask[0x4]; /* FMan controller mask 0-3 */ + u32 res2[0x4]; + u32 fpmtsc1; /* timestamp control1 */ + u32 fpmtsc2; /* timestamp control2 */ + u32 fpmtsp; /* time stamp */ + u32 fpmtsf; /* time stamp fraction */ + u32 fpmrcr; /* rams control and event */ + u32 res3[0x3]; + u32 fpmdrd[0x4]; /* data_ram data 0-3 */ + u32 res4[0xc]; + u32 fpmdra; /* data ram access */ + u32 fm_ip_rev_1; /* IP block revision 1 */ + u32 fm_ip_rev_2; /* IP block revision 2 */ + u32 fmrstc; /* reset command */ + u32 fmcld; /* classifier debug control */ + u32 fmnpi; /* normal pending interrupts */ + u32 res5; + u32 fmfpee; /* event and enable */ + u32 fpmcev[0x4]; /* CPU event 0-3 */ + u32 res6[0x4]; + u32 fmfp_ps[0x40]; /* port status */ + u32 res7[0x260]; + u32 fpmts[0x80]; /* task status */ + u32 res8[0xa0]; +} fm_fpm_t; + +/* FMFP_PRC - FPM Port_ID Control Register */ +#define FMFPPRC_PORTID_MASK 0x3f000000 +#define FMFPPRC_PORTID_SHIFT 24 +#define FMFPPRC_ORA_SHIFT 16 +#define FMFPPRC_RISC1 0x00000001 +#define FMFPPRC_RISC2 0x00000002 +#define FMFPPRC_RISC_ALL (FMFPPRC_RISC1 | FMFPPRC_RSIC2) + +/* FPM Flush Control Register */ +#define FMFP_FLC_DISP_LIM_NONE 0x00000000 /* no dispatch limitation */ + +/* FMFP_EE - FPM event and enable register */ +#define FMFPEE_DECC 0x80000000 /* double ECC err on FPM ram */ +#define FMFPEE_STL 0x40000000 /* stall of task ... */ +#define FMFPEE_SECC 0x20000000 /* single ECC error */ +#define FMFPEE_RFM 0x00010000 /* release FMan */ +#define FMFPEE_DECC_EN 0x00008000 /* double ECC interrupt enable */ +#define FMFPEE_STL_EN 0x00004000 /* stall of task interrupt enable */ +#define FMFPEE_SECC_EN 0x00002000 /* single ECC err interrupt enable */ +#define FMFPEE_EHM 0x00000008 /* external halt enable */ +#define FMFPEE_UEC 0x00000004 /* FMan is not halted */ +#define FMFPEE_CER 0x00000002 /* only errornous task stalled */ +#define FMFPEE_DER 0x00000001 /* DMA error is just reported */ + +#define FMFPEE_CLEAR_EVENT (FMFPEE_DECC | FMFPEE_STL | FMFPEE_SECC | \ + FMFPEE_EHM | FMFPEE_UEC | FMFPEE_CER | \ + FMFPEE_DER | FMFPEE_RFM) + +/* FMFP_RCR - FMan Rams Control and Event */ +#define FMFP_RCR_MDEC 0x00008000 /* double ECC error in muram */ +#define FMFP_RCR_IDEC 0x00004000 /* double ECC error in iram */ + +typedef struct fm_imem { + u32 iadd; /* instruction address register */ + u32 idata; /* instruction data register */ + u32 itcfg; /* timing config register */ + u32 iready; /* ready register */ + u8 res[0xff0]; +} fm_imem_t; +#define IRAM_IADD_AIE 0x80000000 /* address auto increase enable */ +#define IRAM_READY 0x80000000 /* ready to use */ + +typedef struct fm_soft_parser { + u8 res[4*1024]; +} fm_soft_parser_t; + +typedef struct fm_dtesc { + u8 res[4*1024]; +} fm_dtsec_t; + +typedef struct fm_mdio { + u8 res0[0x120]; + u32 miimcfg; /* MII management configuration reg */ + u32 miimcom; /* MII management command reg */ + u32 miimadd; /* MII management address reg */ + u32 miimcon; /* MII management control reg */ + u32 miimstat; /* MII management status reg */ + u32 miimind; /* MII management indication reg */ + u8 res1[0x1000 - 0x138]; +} fm_mdio_t; + +typedef struct fm_10gec { + u8 res[4*1024]; +} fm_10gec_t; + +typedef struct fm_10gec_mdio { + u8 res[4*1024]; +} fm_10gec_mdio_t; + +typedef struct fm_memac { + u8 res[4*1024]; +} fm_memac_t; + +typedef struct fm_memac_mdio { + u8 res[4*1024]; +} fm_memac_mdio_t; + +typedef struct fm_1588 { + u8 res[4*1024]; +} fm_1588_t; + +typedef struct ccsr_fman { + u8 muram[0x80000]; + fm_bmi_common_t fm_bmi_common; + fm_qmi_common_t fm_qmi_common; + u8 res0[2048]; + struct { + fm_bmi_t fm_bmi; + fm_qmi_t fm_qmi; + fm_parser_t fm_parser; + u8 res[1024]; + } port[63]; + fm_policer_t fm_policer; + fm_keygen_t fm_keygen; + fm_dma_t fm_dma; + fm_fpm_t fm_fpm; + fm_imem_t fm_imem; + u8 res1[8*1024]; + fm_soft_parser_t fm_soft_parser; + u8 res2[96*1024]; +#ifdef CONFIG_SYS_FMAN_V3 + struct { + fm_memac_t fm_memac; + fm_memac_mdio_t fm_memac_mdio; + } memac[10]; + u8 res4[32*1024]; + fm_memac_mdio_t fm_dedicated_mdio[2]; +#else + struct { + fm_dtsec_t fm_dtesc; + fm_mdio_t fm_mdio; + } mac_1g[8]; /* support up to 8 1g controllers */ + struct { + fm_10gec_t fm_10gec; + fm_10gec_mdio_t fm_10gec_mdio; + } mac_10g[1]; + u8 res4[48*1024]; +#endif + fm_1588_t fm_1588; + u8 res5[4*1024]; +} ccsr_fman_t; + +#endif /*__FSL_FMAN_H__*/ diff --git a/include/fsl_sec.h b/include/fsl_sec.h index abc62da992..2ddced34ab 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -194,11 +194,9 @@ struct jr_regs { struct sg_entry { #if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6) uint32_t addr_lo; /* Memory Address - lo */ - uint16_t addr_hi; /* Memory Address of start of buffer - hi */ - uint16_t reserved_zero; + uint32_t addr_hi; /* Memory Address of start of buffer - hi */ #else - uint16_t reserved_zero; - uint16_t addr_hi; /* Memory Address of start of buffer - hi */ + uint32_t addr_hi; /* Memory Address of start of buffer - hi */ uint32_t addr_lo; /* Memory Address - lo */ #endif diff --git a/include/fsl_tgec.h b/include/fsl_tgec.h new file mode 100644 index 0000000000..92fb777c25 --- /dev/null +++ b/include/fsl_tgec.h @@ -0,0 +1,202 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TGEC_H__ +#define __TGEC_H__ + +#include <phy.h> + +struct tgec { + /* 10GEC general control and status registers */ + u32 tgec_id; /* Controller ID register */ + u32 res0; + u32 command_config; /* Control and configuration register */ + u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */ + u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */ + u32 maxfrm; /* Maximum frame length register */ + u32 pause_quant; /* Pause quanta register */ + u32 res1[4]; + u32 hashtable_ctrl; /* Hash table control register */ + u32 res2[4]; + u32 status; /* MAC status register */ + u32 tx_ipg_length; /* Transmitter inter-packet-gap register */ + u32 mac_addr_2; /* Lower 32 bits of the 2nd 48-bit MAC addr */ + u32 mac_addr_3; /* Upper 16 bits of the 2nd 48-bit MAC addr */ + u32 res3[4]; + u32 imask; /* Interrupt mask register */ + u32 ievent; /* Interrupt event register */ + u32 res4[6]; + /* 10GEC statistics counter registers */ + u32 tx_frame_u; /* Tx frame counter upper */ + u32 tx_frame_l; /* Tx frame counter lower */ + u32 rx_frame_u; /* Rx frame counter upper */ + u32 rx_frame_l; /* Rx frame counter lower */ + u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */ + u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */ + u32 rx_align_err_u; /* Rx alignment error upper */ + u32 rx_align_err_l; /* Rx alignment error lower */ + u32 tx_pause_frame_u; /* Tx valid pause frame upper */ + u32 tx_pause_frame_l; /* Tx valid pause frame lower */ + u32 rx_pause_frame_u; /* Rx valid pause frame upper */ + u32 rx_pause_frame_l; /* Rx valid pause frame upper */ + u32 rx_long_err_u; /* Rx too long frame error upper */ + u32 rx_long_err_l; /* Rx too long frame error lower */ + u32 rx_frame_err_u; /* Rx frame length error upper */ + u32 rx_frame_err_l; /* Rx frame length error lower */ + u32 tx_vlan_u; /* Tx VLAN frame upper */ + u32 tx_vlan_l; /* Tx VLAN frame lower */ + u32 rx_vlan_u; /* Rx VLAN frame upper */ + u32 rx_vlan_l; /* Rx VLAN frame lower */ + u32 tx_oct_u; /* Tx octets upper */ + u32 tx_oct_l; /* Tx octets lower */ + u32 rx_oct_u; /* Rx octets upper */ + u32 rx_oct_l; /* Rx octets lower */ + u32 rx_uni_u; /* Rx unicast frame upper */ + u32 rx_uni_l; /* Rx unicast frame lower */ + u32 rx_multi_u; /* Rx multicast frame upper */ + u32 rx_multi_l; /* Rx multicast frame lower */ + u32 rx_brd_u; /* Rx broadcast frame upper */ + u32 rx_brd_l; /* Rx broadcast frame lower */ + u32 tx_frame_err_u; /* Tx frame error upper */ + u32 tx_frame_err_l; /* Tx frame error lower */ + u32 tx_uni_u; /* Tx unicast frame upper */ + u32 tx_uni_l; /* Tx unicast frame lower */ + u32 tx_multi_u; /* Tx multicast frame upper */ + u32 tx_multi_l; /* Tx multicast frame lower */ + u32 tx_brd_u; /* Tx broadcast frame upper */ + u32 tx_brd_l; /* Tx broadcast frame lower */ + u32 rx_drop_u; /* Rx dropped packets upper */ + u32 rx_drop_l; /* Rx dropped packets lower */ + u32 rx_eoct_u; /* Rx ethernet octets upper */ + u32 rx_eoct_l; /* Rx ethernet octets lower */ + u32 rx_pkt_u; /* Rx packets upper */ + u32 rx_pkt_l; /* Rx packets lower */ + u32 tx_undsz_u; /* Undersized packet upper */ + u32 tx_undsz_l; /* Undersized packet lower */ + u32 rx_64_u; /* Rx 64 oct packet upper */ + u32 rx_64_l; /* Rx 64 oct packet lower */ + u32 rx_127_u; /* Rx 65 to 127 oct packet upper */ + u32 rx_127_l; /* Rx 65 to 127 oct packet lower */ + u32 rx_255_u; /* Rx 128 to 255 oct packet upper */ + u32 rx_255_l; /* Rx 128 to 255 oct packet lower */ + u32 rx_511_u; /* Rx 256 to 511 oct packet upper */ + u32 rx_511_l; /* Rx 256 to 511 oct packet lower */ + u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */ + u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */ + u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */ + u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */ + u32 rx_1519_u; /* Rx 1519 to max oct packet upper */ + u32 rx_1519_l; /* Rx 1519 to max oct packet lower */ + u32 tx_oversz_u; /* oversized packet upper */ + u32 tx_oversz_l; /* oversized packet lower */ + u32 tx_jabber_u; /* Jabber packet upper */ + u32 tx_jabber_l; /* Jabber packet lower */ + u32 tx_frag_u; /* Fragment packet upper */ + u32 tx_frag_l; /* Fragment packet lower */ + u32 rx_err_u; /* Rx frame error upper */ + u32 rx_err_l; /* Rx frame error lower */ + u32 res5[0x39a]; +}; + +/* EC10G_ID - 10-gigabit ethernet MAC controller ID */ +#define EC10G_ID_VER_MASK 0x0000ff00 +#define EC10G_ID_VER_SHIFT 8 +#define EC10G_ID_REV_MASK 0x000000ff + +/* COMMAND_CONFIG - command and configuration register */ +#define TGEC_CMD_CFG_EN_TIMESTAMP 0x00100000 /* enable IEEE1588 */ +#define TGEC_CMD_CFG_TX_ADDR_INS_SEL 0x00080000 /* Tx mac addr w/ second */ +#define TGEC_CMD_CFG_NO_LEN_CHK 0x00020000 /* payload len chk disable */ +#define TGEC_CMD_CFG_SEND_IDLE 0x00010000 /* send XGMII idle seqs */ +#define TGEC_CMD_CFG_RX_ER_DISC 0x00004000 /* Rx err frm discard enb */ +#define TGEC_CMD_CFG_CMD_FRM_EN 0x00002000 /* CMD frame RX enable */ +#define TGEC_CMD_CFG_STAT_CLR 0x00001000 /* clear stats */ +#define TGEC_CMD_CFG_TX_ADDR_INS 0x00000200 /* overwrite src MAC addr */ +#define TGEC_CMD_CFG_PAUSE_IGNORE 0x00000100 /* ignore pause frames */ +#define TGEC_CMD_CFG_PAUSE_FWD 0x00000080 /* fwd pause frames */ +#define TGEC_CMD_CFG_CRC_FWD 0x00000040 /* fwd Rx CRC frames */ +#define TGEC_CMD_CFG_PAD_EN 0x00000020 /* MAC remove Rx padding */ +#define TGEC_CMD_CFG_PROM_EN 0x00000010 /* promiscuous mode enable */ +#define TGEC_CMD_CFG_WAN_MODE 0x00000008 /* WAN mode enable */ +#define TGEC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */ +#define TGEC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */ +#define TGEC_CMD_CFG_RXTX_EN (TGEC_CMD_CFG_RX_EN | TGEC_CMD_CFG_TX_EN) + +/* HASHTABLE_CTRL - Hashtable control register */ +#define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */ +#define HASHTABLE_CTRL_ADDR_MASK 0x000001ff + +/* TX_IPG_LENGTH - Transmit inter-packet gap length register */ +#define TX_IPG_LENGTH_IPG_LEN_MASK 0x000003ff + +/* IMASK - interrupt mask register */ +#define IMASK_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event mask */ +#define IMASK_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion mask */ +#define IMASK_REM_FAULT 0x00004000 /* remote fault mask */ +#define IMASK_LOC_FAULT 0x00002000 /* local fault mask */ +#define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */ +#define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */ +#define IMASK_TX_ER 0x00000200 /* Tx frame error mask */ +#define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */ +#define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */ +#define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */ +#define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */ +#define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */ +#define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */ +#define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */ +#define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */ +#define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */ + +#define IMASK_MASK_ALL 0x00000000 + +/* IEVENT - interrupt event register */ +#define IEVENT_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event */ +#define IEVENT_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion */ +#define IEVENT_REM_FAULT 0x00004000 /* remote fault */ +#define IEVENT_LOC_FAULT 0x00002000 /* local fault */ +#define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */ +#define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ +#define IEVENT_TX_ER 0x00000200 /* Tx frame error */ +#define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */ +#define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */ +#define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */ +#define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */ +#define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */ +#define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */ +#define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */ +#define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */ +#define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */ + +#define IEVENT_CLEAR_ALL 0xffffffff + +struct tgec_mdio_controller { + u32 res0[0xc]; + u32 mdio_stat; /* MDIO configuration and status */ + u32 mdio_ctl; /* MDIO control */ + u32 mdio_data; /* MDIO data */ + u32 mdio_addr; /* MDIO address */ +}; + +#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8) +#define MDIO_STAT_BSY (1 << 0) +#define MDIO_STAT_RD_ER (1 << 1) +#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) +#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) +#define MDIO_CTL_PRE_DIS (1 << 10) +#define MDIO_CTL_SCAN_EN (1 << 11) +#define MDIO_CTL_POST_INC (1 << 14) +#define MDIO_CTL_READ (1 << 15) + +#define MDIO_DATA(x) (x & 0xffff) +#define MDIO_DATA_BSY (1 << 31) + +struct fsl_enet_mac; + +void init_tgec(struct fsl_enet_mac *mac, void *base, void *phyregs, + int max_rx_len); + +#endif diff --git a/include/fsl_validate.h b/include/fsl_validate.h index c4605349a6..92dd98bb61 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -82,14 +82,14 @@ struct fsl_secboot_img_hdr { u32 psign; /* signature offset */ u32 sign_len; /* length of the signature in bytes */ union { - struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */ - u8 *pimg; /* ptr to ESBC client image */ + u32 psgtable; /* ptr to SG table */ + u32 pimg; /* ptr to ESBC client image */ }; union { u32 sg_entries; /* no of entries in SG table */ u32 img_size; /* ESBC client image size in bytes */ }; - ulong img_start; /* ESBC client entry point */ + u32 img_start; /* ESBC client entry point */ u32 sg_flag; /* Scatter gather flag */ u32 uid_flag; u32 fsl_uid_0; @@ -133,7 +133,7 @@ struct srk_table { */ struct fsl_secboot_sg_table { u32 len; /* length of the segment in bytes */ - ulong src_addr; /* ptr to the data segment */ + u32 src_addr; /* ptr to the data segment */ }; #else /* @@ -146,8 +146,8 @@ struct fsl_secboot_sg_table { struct fsl_secboot_sg_table { u32 len; u32 trgt_id; - ulong src_addr; - ulong dst_addr; + u32 src_addr; + u32 dst_addr; }; #endif @@ -162,7 +162,7 @@ struct fsl_secboot_sg_table { */ struct fsl_secboot_img_priv { uint32_t hdr_location; - ulong ie_addr; + u32 ie_addr; u32 key_len; struct fsl_secboot_img_hdr hdr; diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 7b4011f0a3..1b2e4915a0 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -2,6 +2,7 @@ #define _LINUX_BITOPS_H #include <asm/types.h> +#include <linux/compiler.h> #define BIT(nr) (1UL << (nr)) #define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) @@ -139,6 +140,32 @@ static inline unsigned int generic_hweight8(unsigned int w) # define fls generic_fls #endif +static inline unsigned fls_long(unsigned long l) +{ + if (sizeof(l) == 4) + return fls(l); + return fls64(l); +} + +/** + * __ffs64 - find first set bit in a 64 bit word + * @word: The 64 bit word + * + * On 64 bit arches this is a synomyn for __ffs + * The result is not defined if no bits are set, so check that @word + * is non-zero before calling this. + */ +static inline unsigned long __ffs64(u64 word) +{ +#if BITS_PER_LONG == 32 + if (((u32)word) == 0UL) + return __ffs((u32)(word >> 32)) + 32; +#elif BITS_PER_LONG != 64 +#error BITS_PER_LONG not 32 or 64 +#endif + return __ffs((unsigned long)word); +} + /** * __set_bit - Set a bit in memory * @nr: the bit to set diff --git a/include/linux/compat.h b/include/linux/compat.h index 59937de960..e561ee311a 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -130,12 +130,6 @@ static inline void led_trigger_unregister_simple(struct led_trigger *trigger) {} static inline void led_trigger_event(struct led_trigger *trigger, enum led_brightness event) {} -/* include/linux/log2.h */ -static inline int is_power_of_2(unsigned long n) -{ - return (n != 0 && ((n & (n - 1)) == 0)); -} - /* uapi/linux/limits.h */ #define XATTR_LIST_MAX 65536 /* size of extended attribute namelist (64k) */ diff --git a/include/linux/log2.h b/include/linux/log2.h new file mode 100644 index 0000000000..aa1de63090 --- /dev/null +++ b/include/linux/log2.h @@ -0,0 +1,205 @@ +/* Integer base 2 logarithm calculation + * + * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _LINUX_LOG2_H +#define _LINUX_LOG2_H + +#include <linux/types.h> +#include <linux/bitops.h> + +/* + * deal with unrepresentable constant logarithms + */ +extern __attribute__((const, noreturn)) +int ____ilog2_NaN(void); + +/* + * non-constant log of base 2 calculators + * - the arch may override these in asm/bitops.h if they can be implemented + * more efficiently than using fls() and fls64() + * - the arch is not required to handle n==0 if implementing the fallback + */ +#ifndef CONFIG_ARCH_HAS_ILOG2_U32 +static inline __attribute__((const)) +int __ilog2_u32(u32 n) +{ + return fls(n) - 1; +} +#endif + +#ifndef CONFIG_ARCH_HAS_ILOG2_U64 +static inline __attribute__((const)) +int __ilog2_u64(u64 n) +{ + return fls64(n) - 1; +} +#endif + +/* + * Determine whether some value is a power of two, where zero is + * *not* considered a power of two. + */ + +static inline __attribute__((const)) +bool is_power_of_2(unsigned long n) +{ + return (n != 0 && ((n & (n - 1)) == 0)); +} + +/* + * round up to nearest power of two + */ +static inline __attribute__((const)) +unsigned long __roundup_pow_of_two(unsigned long n) +{ + return 1UL << fls_long(n - 1); +} + +/* + * round down to nearest power of two + */ +static inline __attribute__((const)) +unsigned long __rounddown_pow_of_two(unsigned long n) +{ + return 1UL << (fls_long(n) - 1); +} + +/** + * ilog2 - log of base 2 of 32-bit or a 64-bit unsigned value + * @n - parameter + * + * constant-capable log of base 2 calculation + * - this can be used to initialise global variables from constant data, hence + * the massive ternary operator construction + * + * selects the appropriately-sized optimised version depending on sizeof(n) + */ +#define ilog2(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (n) < 1 ? ____ilog2_NaN() : \ + (n) & (1ULL << 63) ? 63 : \ + (n) & (1ULL << 62) ? 62 : \ + (n) & (1ULL << 61) ? 61 : \ + (n) & (1ULL << 60) ? 60 : \ + (n) & (1ULL << 59) ? 59 : \ + (n) & (1ULL << 58) ? 58 : \ + (n) & (1ULL << 57) ? 57 : \ + (n) & (1ULL << 56) ? 56 : \ + (n) & (1ULL << 55) ? 55 : \ + (n) & (1ULL << 54) ? 54 : \ + (n) & (1ULL << 53) ? 53 : \ + (n) & (1ULL << 52) ? 52 : \ + (n) & (1ULL << 51) ? 51 : \ + (n) & (1ULL << 50) ? 50 : \ + (n) & (1ULL << 49) ? 49 : \ + (n) & (1ULL << 48) ? 48 : \ + (n) & (1ULL << 47) ? 47 : \ + (n) & (1ULL << 46) ? 46 : \ + (n) & (1ULL << 45) ? 45 : \ + (n) & (1ULL << 44) ? 44 : \ + (n) & (1ULL << 43) ? 43 : \ + (n) & (1ULL << 42) ? 42 : \ + (n) & (1ULL << 41) ? 41 : \ + (n) & (1ULL << 40) ? 40 : \ + (n) & (1ULL << 39) ? 39 : \ + (n) & (1ULL << 38) ? 38 : \ + (n) & (1ULL << 37) ? 37 : \ + (n) & (1ULL << 36) ? 36 : \ + (n) & (1ULL << 35) ? 35 : \ + (n) & (1ULL << 34) ? 34 : \ + (n) & (1ULL << 33) ? 33 : \ + (n) & (1ULL << 32) ? 32 : \ + (n) & (1ULL << 31) ? 31 : \ + (n) & (1ULL << 30) ? 30 : \ + (n) & (1ULL << 29) ? 29 : \ + (n) & (1ULL << 28) ? 28 : \ + (n) & (1ULL << 27) ? 27 : \ + (n) & (1ULL << 26) ? 26 : \ + (n) & (1ULL << 25) ? 25 : \ + (n) & (1ULL << 24) ? 24 : \ + (n) & (1ULL << 23) ? 23 : \ + (n) & (1ULL << 22) ? 22 : \ + (n) & (1ULL << 21) ? 21 : \ + (n) & (1ULL << 20) ? 20 : \ + (n) & (1ULL << 19) ? 19 : \ + (n) & (1ULL << 18) ? 18 : \ + (n) & (1ULL << 17) ? 17 : \ + (n) & (1ULL << 16) ? 16 : \ + (n) & (1ULL << 15) ? 15 : \ + (n) & (1ULL << 14) ? 14 : \ + (n) & (1ULL << 13) ? 13 : \ + (n) & (1ULL << 12) ? 12 : \ + (n) & (1ULL << 11) ? 11 : \ + (n) & (1ULL << 10) ? 10 : \ + (n) & (1ULL << 9) ? 9 : \ + (n) & (1ULL << 8) ? 8 : \ + (n) & (1ULL << 7) ? 7 : \ + (n) & (1ULL << 6) ? 6 : \ + (n) & (1ULL << 5) ? 5 : \ + (n) & (1ULL << 4) ? 4 : \ + (n) & (1ULL << 3) ? 3 : \ + (n) & (1ULL << 2) ? 2 : \ + (n) & (1ULL << 1) ? 1 : \ + (n) & (1ULL << 0) ? 0 : \ + ____ilog2_NaN() \ + ) : \ + (sizeof(n) <= 4) ? \ + __ilog2_u32(n) : \ + __ilog2_u64(n) \ + ) + +/** + * roundup_pow_of_two - round the given value up to nearest power of two + * @n - parameter + * + * round the given value up to the nearest power of two + * - the result is undefined when n == 0 + * - this can be used to initialise global variables from constant data + */ +#define roundup_pow_of_two(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (n == 1) ? 1 : \ + (1UL << (ilog2((n) - 1) + 1)) \ + ) : \ + __roundup_pow_of_two(n) \ + ) + +/** + * rounddown_pow_of_two - round the given value down to nearest power of two + * @n - parameter + * + * round the given value down to the nearest power of two + * - the result is undefined when n == 0 + * - this can be used to initialise global variables from constant data + */ +#define rounddown_pow_of_two(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (1UL << ilog2(n))) : \ + __rounddown_pow_of_two(n) \ + ) + +/** + * order_base_2 - calculate the (rounded up) base 2 order of the argument + * @n: parameter + * + * The first few values calculated by this routine: + * ob2(0) = 0 + * ob2(1) = 0 + * ob2(2) = 1 + * ob2(3) = 2 + * ob2(4) = 2 + * ob2(5) = 3 + * ... and so on. + */ + +#define order_base_2(n) ilog2(roundup_pow_of_two(n)) + +#endif /* _LINUX_LOG2_H */ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index e3d3fc73fd..c2cd3df1fa 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -272,6 +272,8 @@ struct mtd_info { struct module *owner; #ifndef __UBOOT__ struct device dev; +#else + struct udevice *dev; #endif int usecount; }; diff --git a/include/mpc8260.h b/include/mpc8260.h index 9980c74b51..75f1b0c9df 100644 --- a/include/mpc8260.h +++ b/include/mpc8260.h @@ -892,7 +892,7 @@ #define UPMC 3 #if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG) -extern __inline__ void +static __inline__ void reset_8260_watchdog(volatile immap_t *immr) { immr->im_siu_conf.sc_swsr = 0x556c; diff --git a/include/mtd.h b/include/mtd.h new file mode 100644 index 0000000000..3f8c293b00 --- /dev/null +++ b/include/mtd.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MTD_H_ +#define _MTD_H_ + +#include <linux/mtd/mtd.h> + +/* + * Get mtd_info structure of the dev, which is stored as uclass private. + * + * @dev: The MTD device + * @return: pointer to mtd_info, NULL on error + */ +static inline struct mtd_info *mtd_get_info(struct udevice *dev) +{ + return dev_get_uclass_priv(dev); +} + +#endif /* _MTD_H_ */ diff --git a/include/netdev.h b/include/netdev.h index 3d5a54f2ab..28eab46407 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -25,9 +25,6 @@ int board_eth_init(bd_t *bis); int cpu_eth_init(bd_t *bis); /* Driver initialization prototypes */ -int altera_tse_initialize(u8 dev_num, int mac_base, - int sgdma_rx_base, int sgdma_tx_base, - u32 sgdma_desc_base, u32 sgdma_desc_size); int at91emac_register(bd_t *bis, unsigned long iobase); int au1x00_enet_initialize(bd_t*); int ax88180_initialize(bd_t *bis); diff --git a/include/power/regulator.h b/include/power/regulator.h index 1a51c3f07b..63c0814fe8 100644 --- a/include/power/regulator.h +++ b/include/power/regulator.h @@ -419,4 +419,20 @@ int regulator_get_by_devname(const char *devname, struct udevice **devp); */ int regulator_get_by_platname(const char *platname, struct udevice **devp); +/** + * device_get_supply_regulator: returns the pointer to the supply regulator. + * Search by phandle, found in device's node. + * + * Note: Please pay attention to proper order of device bind sequence. + * The regulator device searched by the phandle, must be binded before + * this function call. + * + * @dev - device with supply phandle + * @supply_name - phandle name of regulator + * @devp - returned pointer to the supply device + * @return 0 on success or negative value of errno. + */ +int device_get_supply_regulator(struct udevice *dev, const char *supply_name, + struct udevice **devp); + #endif /* _INCLUDE_REGULATOR_H_ */ diff --git a/include/power/s2mps11.h b/include/power/s2mps11.h new file mode 100644 index 0000000000..5da47198a4 --- /dev/null +++ b/include/power/s2mps11.h @@ -0,0 +1,109 @@ +#ifndef __S2MPS11__H__ +#define __S2MPS11__H__ + +enum s2mps11_reg { + S2MPS11_REG_ID = 0, + S2MPS11_REG_INT1, + S2MPS11_REG_INT2, + S2MPS11_REG_INT3, + S2MPS11_REG_INT1M, + S2MPS11_REG_INT2M, + S2MPS11_REG_INT3M, + S2MPS11_REG_STATUS1, + S2MPS11_REG_STATUS2, + S2MPS11_REG_OFFSRC, + S2MPS11_REG_PWRONSRC, + S2MPS11_REG_RTC_CTRL, + S2MPS11_REG_CTRL1, + S2MPS11_REG_ETC_TEST, + S2MPS11_REG_RSVD3, + S2MPS11_REG_BU_CHG, + S2MPS11_REG_RAMP, + S2MPS11_REG_RAMP_BUCK, + S2MPS11_REG_LDO1_8, + S2MPS11_REG_LDO9_16, + S2MPS11_REG_LDO17_24, + S2MPS11_REG_LDO25_32, + S2MPS11_REG_LDO33_38, + S2MPS11_REG_LDO1_8_OVC, + S2MPS11_REG_LDO9_16_OVC, + S2MPS11_REG_LDO17_24_OVC, + S2MPS11_REG_LDO25_32_OVC, + S2MPS11_REG_LDO33_38_OVC, + S2MPS11_REG_RESERVED1, + S2MPS11_REG_RESERVED2, + S2MPS11_REG_RESERVED3, + S2MPS11_REG_RESERVED4, + S2MPS11_REG_RESERVED5, + S2MPS11_REG_RESERVED6, + S2MPS11_REG_RESERVED7, + S2MPS11_REG_RESERVED8, + S2MPS11_REG_WDRSTEN_CTRL, + S2MPS11_REG_B1CTRL1, + S2MPS11_REG_B1CTRL2, + S2MPS11_REG_B2CTRL1, + S2MPS11_REG_B2CTRL2, + S2MPS11_REG_B3CTRL1, + S2MPS11_REG_B3CTRL2, + S2MPS11_REG_B4CTRL1, + S2MPS11_REG_B4CTRL2, + S2MPS11_REG_B5CTRL1, + S2MPS11_REG_BUCK5_SW, + S2MPS11_REG_B5CTRL2, + S2MPS11_REG_B5CTRL3, + S2MPS11_REG_B5CTRL4, + S2MPS11_REG_B5CTRL5, + S2MPS11_REG_B6CTRL1, + S2MPS11_REG_B6CTRL2, + S2MPS11_REG_B7CTRL1, + S2MPS11_REG_B7CTRL2, + S2MPS11_REG_B8CTRL1, + S2MPS11_REG_B8CTRL2, + S2MPS11_REG_B9CTRL1, + S2MPS11_REG_B9CTRL2, + S2MPS11_REG_B10CTRL1, + S2MPS11_REG_B10CTRL2, + S2MPS11_REG_L1CTRL, + S2MPS11_REG_L2CTRL, + S2MPS11_REG_L3CTRL, + S2MPS11_REG_L4CTRL, + S2MPS11_REG_L5CTRL, + S2MPS11_REG_L6CTRL, + S2MPS11_REG_L7CTRL, + S2MPS11_REG_L8CTRL, + S2MPS11_REG_L9CTRL, + S2MPS11_REG_L10CTRL, + S2MPS11_REG_L11CTRL, + S2MPS11_REG_L12CTRL, + S2MPS11_REG_L13CTRL, + S2MPS11_REG_L14CTRL, + S2MPS11_REG_L15CTRL, + S2MPS11_REG_L16CTRL, + S2MPS11_REG_L17CTRL, + S2MPS11_REG_L18CTRL, + S2MPS11_REG_L19CTRL, + S2MPS11_REG_L20CTRL, + S2MPS11_REG_L21CTRL, + S2MPS11_REG_L22CTRL, + S2MPS11_REG_L23CTRL, + S2MPS11_REG_L24CTRL, + S2MPS11_REG_L25CTRL, + S2MPS11_REG_L26CTRL, + S2MPS11_REG_L27CTRL, + S2MPS11_REG_L28CTRL, + S2MPS11_REG_L29CTRL, + S2MPS11_REG_L30CTRL, + S2MPS11_REG_L31CTRL, + S2MPS11_REG_L32CTRL, + S2MPS11_REG_L33CTRL, + S2MPS11_REG_L34CTRL, + S2MPS11_REG_L35CTRL, + S2MPS11_REG_L36CTRL, + S2MPS11_REG_L37CTRL, + S2MPS11_REG_L38CTRL, + S2MPS11_REG_COUNT, +}; + +#define S2MPS11_LDO26_ENABLE 0xec + +#endif diff --git a/include/power/sandbox_pmic.h b/include/power/sandbox_pmic.h index 8547674971..7fdbfb9fc6 100644 --- a/include/power/sandbox_pmic.h +++ b/include/power/sandbox_pmic.h @@ -126,6 +126,10 @@ enum { #define SANDBOX_BUCK1_AUTOSET_EXPECTED_UA 200000 #define SANDBOX_BUCK1_AUTOSET_EXPECTED_ENABLE true +/* BUCK2: for testing sandbox ADC's supply */ +#define SANDBOX_BUCK2_INITIAL_EXPECTED_UV 3000000 +#define SANDBOX_BUCK2_SET_UV 3300000 + /* LDO1/2 for testing regulator_list_autoset() */ #define SANDBOX_LDO1_AUTOSET_EXPECTED_UV 1800000 #define SANDBOX_LDO1_AUTOSET_EXPECTED_UA 100000 diff --git a/include/samsung/exynos5-dt-types.h b/include/samsung/exynos5-dt-types.h new file mode 100644 index 0000000000..479e2e793d --- /dev/null +++ b/include/samsung/exynos5-dt-types.h @@ -0,0 +1,27 @@ +#ifndef _EXYNOS5_DT_H_ +#define _EXYNOS5_DT_H_ + +enum { + EXYNOS5_BOARD_GENERIC, + + EXYNOS5_BOARD_ODROID_XU3, + EXYNOS5_BOARD_ODROID_XU3_REV01, + EXYNOS5_BOARD_ODROID_XU3_REV02, + EXYNOS5_BOARD_ODROID_XU4_REV01, + EXYNOS5_BOARD_ODROID_UNKNOWN, + + EXYNOS5_BOARD_COUNT, +}; + +struct odroid_rev_info { + int board_type; + int board_rev; + int adc_val; + const char *name; +}; + +bool board_is_generic(void); +bool board_is_odroidxu3(void); +bool board_is_odroidxu4(void); + +#endif diff --git a/include/sandbox-adc.h b/include/sandbox-adc.h new file mode 100644 index 0000000000..79ff01c6ab --- /dev/null +++ b/include/sandbox-adc.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SANDBOX_ADC_H_ +#define _SANDBOX_ADC_H_ + +#define SANDBOX_ADC_DEVNAME "adc@0" +#define SANDBOX_ADC_DATA_MASK 0xffff /* 16-bits resolution */ +#define SANDBOX_ADC_CHANNELS 4 +#define SANDBOX_ADC_CHANNEL0_DATA 0x0 +#define SANDBOX_ADC_CHANNEL1_DATA 0x1000 +#define SANDBOX_ADC_CHANNEL2_DATA 0x2000 +#define SANDBOX_ADC_CHANNEL3_DATA 0x3000 + +enum sandbox_adc_mode { + SANDBOX_ADC_MODE_SINGLE_CHANNEL = 0, + SANDBOX_ADC_MODE_MULTI_CHANNEL, +}; + +enum sandbox_adc_status { + SANDBOX_ADC_INACTIVE = 0, + SANDBOX_ADC_ACTIVE, +}; + +#define SANDBOX_ADC_VSS_VALUE 0 + +#endif diff --git a/include/spi_flash.h b/include/spi_flash.h index 4312d3d691..0ae0062d12 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -54,6 +54,9 @@ struct spi_slave; * @write_cmd: Write cmd - page and quad program. * @dummy_byte: Dummy cycles for read operation. * @memory_map: Address of read-only SPI flash access + * @flash_lock: lock a region of the SPI Flash + * @flash_unlock: unlock a region of the SPI Flash + * @flash_is_locked: check if a region of the SPI Flash is completely locked * @read: Flash read ops: Read len bytes at offset into buf * Supported cmds: Fast Array Read * @write: Flash write ops: Write len bytes from buf into offset @@ -87,6 +90,10 @@ struct spi_flash { u8 dummy_byte; void *memory_map; + + int (*flash_lock)(struct spi_flash *flash, u32 ofs, size_t len); + int (*flash_unlock)(struct spi_flash *flash, u32 ofs, size_t len); + int (*flash_is_locked)(struct spi_flash *flash, u32 ofs, size_t len); #ifndef CONFIG_DM_SPI_FLASH /* * These are not strictly needed for driver model, but keep them here @@ -227,6 +234,18 @@ static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, } #endif +static inline int spi_flash_protect(struct spi_flash *flash, u32 ofs, u32 len, + bool prot) +{ + if (!flash->flash_lock) + return -EOPNOTSUPP; + + if (prot) + return flash->flash_lock(flash, ofs, len); + else + return flash->flash_unlock(flash, ofs, len); +} + void spi_boot(void) __noreturn; void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst); diff --git a/include/stdio_dev.h b/include/stdio_dev.h index 95d6246f59..13f76be7c2 100644 --- a/include/stdio_dev.h +++ b/include/stdio_dev.h @@ -16,8 +16,6 @@ #define DEV_FLAGS_INPUT 0x00000001 /* Device can be used as input console */ #define DEV_FLAGS_OUTPUT 0x00000002 /* Device can be used as output console */ -#define DEV_FLAGS_SYSTEM 0x80000000 /* Device is a system device */ -#define DEV_EXT_VIDEO 0x00000001 /* Video extensions supported */ /* Device information */ struct stdio_dev { |