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-rw-r--r--include/configs/A3000.h27
-rw-r--r--include/configs/ADCIOP.h29
-rw-r--r--include/configs/ADNPESC1.h88
-rw-r--r--include/configs/ADS860.h18
-rw-r--r--include/configs/AMX860.h47
-rw-r--r--include/configs/AP1000.h40
-rw-r--r--include/configs/APC405.h45
-rw-r--r--include/configs/AR405.h38
-rw-r--r--include/configs/ASH405.h86
-rw-r--r--include/configs/Adder.h29
-rw-r--r--include/configs/AdderUSB.h51
-rw-r--r--include/configs/Alaska8220.h60
-rw-r--r--include/configs/AmigaOneG3SE.h56
-rw-r--r--include/configs/B2.h26
-rw-r--r--include/configs/BAB7xx.h32
-rw-r--r--include/configs/BC3450.h143
-rw-r--r--include/configs/BMW.h37
-rw-r--r--include/configs/CANBT.h29
-rw-r--r--include/configs/CATcenter.h46
-rw-r--r--include/configs/CCM.h32
-rw-r--r--include/configs/CMS700.h93
-rw-r--r--include/configs/CPC45.h51
-rw-r--r--include/configs/CPCI2DP.h35
-rw-r--r--include/configs/CPCI405.h53
-rw-r--r--include/configs/CPCI4052.h64
-rw-r--r--include/configs/CPCI405AB.h62
-rw-r--r--include/configs/CPCI405DT.h63
-rw-r--r--include/configs/CPCI440.h49
-rw-r--r--include/configs/CPCI750.h53
-rw-r--r--include/configs/CPCIISER4.h41
-rw-r--r--include/configs/CPU86.h42
-rw-r--r--include/configs/CPU87.h50
-rw-r--r--include/configs/CRAYL1.h65
-rw-r--r--include/configs/CU824.h30
-rw-r--r--include/configs/DASA_SIM.h35
-rw-r--r--include/configs/DB64360.h39
-rw-r--r--include/configs/DB64460.h39
-rw-r--r--include/configs/DK1C20.h85
-rw-r--r--include/configs/DK1S10.h82
-rw-r--r--include/configs/DP405.h38
-rw-r--r--include/configs/DU405.h38
-rw-r--r--include/configs/EB+MCF-EV123.h63
-rw-r--r--include/configs/ELPPC.h25
-rw-r--r--include/configs/ELPT860.h27
-rw-r--r--include/configs/EP1C20.h49
-rw-r--r--include/configs/EP1S10.h48
-rw-r--r--include/configs/EP1S40.h48
-rw-r--r--include/configs/EP88x.h28
-rw-r--r--include/configs/ERIC.h33
-rw-r--r--include/configs/ESTEEM192E.h17
-rw-r--r--include/configs/ETX094.h22
-rw-r--r--include/configs/EVB64260.h23
-rw-r--r--include/configs/EXBITGEN.h21
-rw-r--r--include/configs/FADS823.h34
-rw-r--r--include/configs/FADS850SAR.h22
-rw-r--r--include/configs/FLAGADM.h34
-rw-r--r--include/configs/FPS850L.h91
-rw-r--r--include/configs/FPS860L.h85
-rw-r--r--include/configs/G2000.h44
-rw-r--r--include/configs/GEN860T.h63
-rw-r--r--include/configs/GENIETV.h21
-rw-r--r--include/configs/GTH.h26
-rw-r--r--include/configs/HH405.h97
-rw-r--r--include/configs/HIDDEN_DRAGON.h31
-rw-r--r--include/configs/HMI10.h52
-rw-r--r--include/configs/HUB405.h80
-rw-r--r--include/configs/IAD210.h29
-rw-r--r--include/configs/ICU862.h40
-rw-r--r--include/configs/IDS8247.h42
-rw-r--r--include/configs/IP860.h32
-rw-r--r--include/configs/IPHASE4539.h25
-rw-r--r--include/configs/ISPAN.h36
-rw-r--r--include/configs/IVML24.h27
-rw-r--r--include/configs/IVMS8.h26
-rw-r--r--include/configs/IceCube.h78
-rw-r--r--include/configs/JSE.h47
-rw-r--r--include/configs/KAREF.h57
-rw-r--r--include/configs/KUP4K.h45
-rw-r--r--include/configs/KUP4X.h49
-rw-r--r--include/configs/LANTEC.h100
-rw-r--r--include/configs/M5235EVB.h261
-rw-r--r--include/configs/M5249EVB.h194
-rw-r--r--include/configs/M5253EVBE.h212
-rw-r--r--include/configs/M5271EVB.h127
-rw-r--r--include/configs/M5272C3.h125
-rw-r--r--include/configs/M5282EVB.h165
-rw-r--r--include/configs/M5329EVB.h267
-rw-r--r--include/configs/M54455EVB.h391
-rw-r--r--include/configs/MBX.h28
-rw-r--r--include/configs/MBX860T.h2
-rw-r--r--include/configs/METROBOX.h59
-rw-r--r--include/configs/MHPC.h35
-rw-r--r--include/configs/MIP405.h70
-rw-r--r--include/configs/ML2.h45
-rw-r--r--include/configs/MOUSSE.h25
-rw-r--r--include/configs/MPC8260ADS.h105
-rw-r--r--include/configs/MPC8266ADS.h97
-rw-r--r--include/configs/MPC8313ERDB.h569
-rw-r--r--include/configs/MPC8323ERDB.h583
-rw-r--r--include/configs/MPC832XEMDS.h68
-rw-r--r--include/configs/MPC8349EMDS.h81
-rw-r--r--include/configs/MPC8349ITX.h85
-rw-r--r--include/configs/MPC8360EMDS.h71
-rw-r--r--include/configs/MPC8540ADS.h77
-rw-r--r--include/configs/MPC8540EVAL.h60
-rw-r--r--include/configs/MPC8541CDS.h61
-rw-r--r--include/configs/MPC8544DS.h212
-rw-r--r--include/configs/MPC8548CDS.h397
-rw-r--r--include/configs/MPC8555CDS.h61
-rw-r--r--include/configs/MPC8560ADS.h117
-rw-r--r--include/configs/MPC8568MDS.h128
-rw-r--r--include/configs/MPC8641HPCN.h185
-rw-r--r--include/configs/MUSENKI.h17
-rw-r--r--include/configs/MVBLUE.h43
-rw-r--r--include/configs/MVS1.h43
-rw-r--r--include/configs/NC650.h39
-rw-r--r--include/configs/NETPHONE.h36
-rw-r--r--include/configs/NETTA.h49
-rw-r--r--include/configs/NETTA2.h37
-rw-r--r--include/configs/NETVIA.h34
-rw-r--r--include/configs/NSCU.h35
-rw-r--r--include/configs/NX823.h27
-rw-r--r--include/configs/OCRTC.h36
-rw-r--r--include/configs/ORSG.h36
-rw-r--r--include/configs/OXC.h21
-rw-r--r--include/configs/P3G4.h40
-rw-r--r--include/configs/PATI.h37
-rw-r--r--include/configs/PCI405.h38
-rw-r--r--include/configs/PCI5441.h42
-rw-r--r--include/configs/PCIPPC2.h41
-rw-r--r--include/configs/PCIPPC6.h43
-rw-r--r--include/configs/PIP405.h69
-rw-r--r--include/configs/PK1C20.h55
-rw-r--r--include/configs/PLU405.h108
-rw-r--r--include/configs/PM520.h77
-rw-r--r--include/configs/PM826.h58
-rw-r--r--include/configs/PM828.h58
-rw-r--r--include/configs/PM854.h79
-rw-r--r--include/configs/PM856.h76
-rw-r--r--include/configs/PMC405.h46
-rw-r--r--include/configs/PN62.h36
-rw-r--r--include/configs/PPChameleonEVB.h50
-rw-r--r--include/configs/QS823.h44
-rw-r--r--include/configs/QS850.h44
-rw-r--r--include/configs/QS860T.h34
-rw-r--r--include/configs/R360MPI.h45
-rw-r--r--include/configs/RBC823.h75
-rw-r--r--include/configs/RPXClassic.h25
-rw-r--r--include/configs/RPXlite.h21
-rw-r--r--include/configs/RPXlite_DW.h52
-rw-r--r--include/configs/RPXsuper.h39
-rw-r--r--include/configs/RRvision.h37
-rw-r--r--include/configs/Rattler.h43
-rw-r--r--include/configs/SBC8540.h55
-rw-r--r--include/configs/SCM.h33
-rw-r--r--include/configs/SL8245.h19
-rw-r--r--include/configs/SM850.h27
-rw-r--r--include/configs/SMN42.h206
-rw-r--r--include/configs/SPD823TS.h28
-rw-r--r--include/configs/SX1.h24
-rw-r--r--include/configs/SXNI855T.h30
-rw-r--r--include/configs/Sandpoint8240.h38
-rw-r--r--include/configs/Sandpoint8245.h33
-rw-r--r--include/configs/TASREG.h34
-rw-r--r--include/configs/TB5200.h100
-rw-r--r--include/configs/TOP5200.h79
-rw-r--r--include/configs/TOP860.h47
-rw-r--r--include/configs/TQM5200.h163
-rw-r--r--include/configs/TQM823L.h53
-rw-r--r--include/configs/TQM823M.h42
-rw-r--r--include/configs/TQM8260.h36
-rw-r--r--include/configs/TQM8272.h57
-rw-r--r--include/configs/TQM834x.h69
-rw-r--r--include/configs/TQM850L.h41
-rw-r--r--include/configs/TQM850M.h41
-rw-r--r--include/configs/TQM855L.h42
-rw-r--r--include/configs/TQM855M.h44
-rw-r--r--include/configs/TQM85xx.h62
-rw-r--r--include/configs/TQM860L.h46
-rw-r--r--include/configs/TQM860M.h44
-rw-r--r--include/configs/TQM862L.h42
-rw-r--r--include/configs/TQM862M.h42
-rw-r--r--include/configs/TQM866M.h42
-rw-r--r--include/configs/TQM885D.h46
-rw-r--r--include/configs/Total5200.h66
-rw-r--r--include/configs/VCMA9.h54
-rw-r--r--include/configs/VOH405.h88
-rw-r--r--include/configs/VOM405.h49
-rw-r--r--include/configs/VoVPN-GW.h53
-rw-r--r--include/configs/W7OLMC.h36
-rw-r--r--include/configs/W7OLMG.h40
-rw-r--r--include/configs/WUH405.h84
-rw-r--r--include/configs/XPEDITE1K.h53
-rw-r--r--include/configs/Yukon8220.h60
-rw-r--r--include/configs/ZPC1900.h51
-rw-r--r--include/configs/ZUMA.h35
-rw-r--r--include/configs/acadia.h205
-rw-r--r--include/configs/ads5121.h401
-rw-r--r--include/configs/adsvix.h26
-rw-r--r--include/configs/aev.h79
-rw-r--r--include/configs/alpr.h60
-rw-r--r--include/configs/armadillo.h17
-rw-r--r--include/configs/assabet.h22
-rw-r--r--include/configs/at91rm9200dk.h42
-rw-r--r--include/configs/atc.h38
-rw-r--r--include/configs/atstk1002.h67
-rw-r--r--include/configs/bamboo.h178
-rw-r--r--include/configs/barco.h37
-rw-r--r--include/configs/bf533-ezkit.h32
-rw-r--r--include/configs/bf533-stamp.h58
-rw-r--r--include/configs/bf537-stamp.h84
-rw-r--r--include/configs/bf561-ezkit.h38
-rw-r--r--include/configs/bubinga.h58
-rw-r--r--include/configs/c2mon.h33
-rw-r--r--include/configs/canmb.h49
-rw-r--r--include/configs/cerf250.h19
-rw-r--r--include/configs/cm4008.h21
-rw-r--r--include/configs/cm41xx.h21
-rw-r--r--include/configs/cm5200.h338
-rw-r--r--include/configs/cmc_pu2.h51
-rw-r--r--include/configs/cmi_mpc5xx.h41
-rw-r--r--include/configs/cobra5272.h53
-rw-r--r--include/configs/cogent_mpc8260.h30
-rw-r--r--include/configs/cogent_mpc8xx.h27
-rw-r--r--include/configs/cpci5200.h61
-rw-r--r--include/configs/cradle.h17
-rw-r--r--include/configs/csb226.h32
-rw-r--r--include/configs/csb272.h48
-rw-r--r--include/configs/csb472.h47
-rw-r--r--include/configs/csb637.h40
-rw-r--r--include/configs/davinci_dvevm.h214
-rw-r--r--include/configs/davinci_schmoogie.h157
-rw-r--r--include/configs/davinci_sonata.h209
-rw-r--r--include/configs/dbau1x00.h58
-rw-r--r--include/configs/debris.h48
-rw-r--r--include/configs/delta.h51
-rw-r--r--include/configs/dnp1110.h19
-rw-r--r--include/configs/eXalion.h32
-rw-r--r--include/configs/ebony.h62
-rw-r--r--include/configs/ep7312.h21
-rw-r--r--include/configs/ep8248.h49
-rw-r--r--include/configs/ep8260.h82
-rw-r--r--include/configs/ep82xxm.h62
-rw-r--r--include/configs/evb4510.h21
-rw-r--r--include/configs/gcplus.h22
-rw-r--r--include/configs/gth2.h35
-rw-r--r--include/configs/gw8260.h48
-rw-r--r--include/configs/hcu4.h348
-rw-r--r--include/configs/hcu5.h391
-rw-r--r--include/configs/hermes.h21
-rw-r--r--include/configs/hmi1001.h54
-rw-r--r--include/configs/hymod.h74
-rw-r--r--include/configs/idmr.h71
-rw-r--r--include/configs/impa7.h21
-rw-r--r--include/configs/incaip.h32
-rw-r--r--include/configs/inka4x0.h52
-rw-r--r--include/configs/innokom.h32
-rw-r--r--include/configs/integratorap.h21
-rw-r--r--include/configs/integratorcp.h27
-rw-r--r--include/configs/ixdp425.h24
-rw-r--r--include/configs/ixdpg425.h31
-rw-r--r--include/configs/jupiter.h43
-rw-r--r--include/configs/katmai.h77
-rw-r--r--include/configs/kb9202.h34
-rw-r--r--include/configs/kvme080.h50
-rw-r--r--include/configs/lart.h19
-rw-r--r--include/configs/logodl.h24
-rw-r--r--include/configs/lpc2292sodimm.h52
-rw-r--r--include/configs/lpd7a400.h25
-rw-r--r--include/configs/lpd7a404.h25
-rw-r--r--include/configs/luan.h57
-rw-r--r--include/configs/lubbock.h22
-rw-r--r--include/configs/lwmon.h55
-rw-r--r--include/configs/lwmon5.h505
-rw-r--r--include/configs/mcc200.h74
-rw-r--r--include/configs/mecp5200.h48
-rw-r--r--include/configs/ml300.h27
-rw-r--r--include/configs/ml401.h145
-rw-r--r--include/configs/modnet50.h21
-rw-r--r--include/configs/motionpro.h197
-rw-r--r--include/configs/mp2usb.h80
-rw-r--r--include/configs/mpc7448hpc2.h58
-rw-r--r--include/configs/mx1ads.h29
-rw-r--r--include/configs/mx1fs2.h38
-rw-r--r--include/configs/netstar.h57
-rw-r--r--include/configs/ns9750dev.h49
-rw-r--r--include/configs/o2dnt.h59
-rw-r--r--include/configs/ocotea.h62
-rw-r--r--include/configs/omap1510inn.h23
-rw-r--r--include/configs/omap1610h2.h23
-rw-r--r--include/configs/omap1610inn.h23
-rw-r--r--include/configs/omap2420h4.h29
-rw-r--r--include/configs/omap5912osk.h23
-rw-r--r--include/configs/omap730p2.h20
-rw-r--r--include/configs/p3mx.h55
-rw-r--r--include/configs/p3p440.h60
-rw-r--r--include/configs/pb1x00.h40
-rw-r--r--include/configs/pcs440ep.h263
-rw-r--r--include/configs/pcu_e.h32
-rw-r--r--include/configs/pdnb3.h42
-rw-r--r--include/configs/pf5200.h60
-rw-r--r--include/configs/pleb2.h21
-rw-r--r--include/configs/ppmc7xx.h291
-rw-r--r--include/configs/ppmc8260.h48
-rw-r--r--include/configs/purple.h19
-rw-r--r--include/configs/pxa255_idp.h23
-rw-r--r--include/configs/quantum.h36
-rw-r--r--include/configs/r5200.h55
-rw-r--r--include/configs/rmu.h35
-rw-r--r--include/configs/rsdproto.h30
-rw-r--r--include/configs/sacsng.h76
-rw-r--r--include/configs/sbc2410x.h47
-rw-r--r--include/configs/sbc405.h40
-rw-r--r--include/configs/sbc8240.h39
-rw-r--r--include/configs/sbc8260.h70
-rw-r--r--include/configs/sbc8349.h76
-rw-r--r--include/configs/sbc8560.h53
-rw-r--r--include/configs/sbc8641d.h606
-rw-r--r--include/configs/sc3.h65
-rw-r--r--include/configs/sc520_cdp.h40
-rw-r--r--include/configs/sc520_spunk.h26
-rw-r--r--include/configs/scb9328.h33
-rw-r--r--include/configs/sequoia.h114
-rw-r--r--include/configs/shannon.h23
-rw-r--r--include/configs/smdk2400.h38
-rw-r--r--include/configs/smdk2410.h38
-rw-r--r--include/configs/smmaco4.h77
-rw-r--r--include/configs/sorcery.h62
-rw-r--r--include/configs/spc1920.h48
-rw-r--r--include/configs/spieval.h119
-rw-r--r--include/configs/stxgp3.h72
-rw-r--r--include/configs/stxssa.h232
-rw-r--r--include/configs/stxxtc.h39
-rw-r--r--include/configs/suzaku.h17
-rw-r--r--include/configs/svm_sc8xx.h32
-rw-r--r--include/configs/taihu.h476
-rw-r--r--include/configs/taishan.h63
-rw-r--r--include/configs/tb0229.h28
-rw-r--r--include/configs/trab.h81
-rw-r--r--include/configs/trizepsiv.h325
-rw-r--r--include/configs/uc100.h54
-rw-r--r--include/configs/uc101.h61
-rw-r--r--include/configs/utx8245.h42
-rw-r--r--include/configs/v37.h29
-rw-r--r--include/configs/v38b.h59
-rw-r--r--include/configs/versatile.h25
-rw-r--r--include/configs/virtlab2.h50
-rw-r--r--include/configs/voiceblue.h57
-rw-r--r--include/configs/walnut.h58
-rw-r--r--include/configs/wepep250.h30
-rw-r--r--include/configs/xaeniax.h32
-rw-r--r--include/configs/xm250.h28
-rw-r--r--include/configs/xsengine.h22
-rw-r--r--include/configs/xupv2p.h64
-rw-r--r--include/configs/yosemite.h78
-rw-r--r--include/configs/yucca.h71
-rw-r--r--include/configs/zeus.h382
-rw-r--r--include/configs/zylonite.h33
358 files changed, 18140 insertions, 6977 deletions
diff --git a/include/configs/A3000.h b/include/configs/A3000.h
index ca9592c23bc..0a9a1ff90c8 100644
--- a/include/configs/A3000.h
+++ b/include/configs/A3000.h
@@ -52,23 +52,20 @@
#define CONFIG_BOOTDELAY 5
-#if 0
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_BSP | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_FLASH | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_NET | \
- CFG_CMD_PCI )
-#endif
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
/*
@@ -309,7 +306,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h
index 821efe5d48b..46329918ef1 100644
--- a/include/configs/ADCIOP.h
+++ b/include/configs/ADCIOP.h
@@ -59,21 +59,32 @@
#define CONFIG_IPADDR 10.0.18.222
#define CONFIG_SERVERIP 10.0.18.190
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_ASKENV )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ASKENV
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -185,7 +196,7 @@
*/
#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h
index 2efca1056e9..77938b140da 100644
--- a/include/configs/ADNPESC1.h
+++ b/include/configs/ADNPESC1.h
@@ -401,15 +401,8 @@
#define CONFIG_RTC_DS1306 1 /* Dallas 1306 real time clock */
#define CFG_SPI_RTC_DEVID 0 /* as 1st SPI device */
-#define __SPI_CMD_OFF 0 /* allow default commands: */
- /* CFG_CMD_SPI */
- /* CFG_CMD_DATE */
-
#else
#undef CONFIG_NIOS_SPI /* NO SPI support */
-#define __SPI_CMD_OFF ( CFG_CMD_SPI \
- | CFG_CMD_DATE \
- )
#endif
/*------------------------------------------------------------------------
@@ -570,45 +563,55 @@
#define CONFIG_POST CFG_POST_RTC
#define CFG_NIOS_POST_WORD_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_CMD_ASKENV | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_BMP | \
- CFG_CMD_CACHE | \
- CFG_CMD_DOC | \
- CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_KGDB | \
- CFG_CMD_NAND | \
- CFG_CMD_NFS | \
- CFG_CMD_MMC | \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_SCSI | \
- CFG_CMD_VFD | \
- CFG_CMD_USB | \
- CFG_CMD_XIMG | \
- __SPI_CMD_OFF ) )
-
-
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_ASKENV
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_CACHE
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PCI
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_XIMG
+
+#if (CFG_NIOS_CPU_SPI_NUMS != 1)
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_DATE
+#endif
/*------------------------------------------------------------------------
* KGDB
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 9600
#endif
@@ -651,7 +654,6 @@
#undef CFG_LOAD_ADDR /* force error break */
#endif
-
/* MEM test area */
#if (CFG_SDRAM_SIZE != 0)
diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h
index df20965640e..2ee8c61cea4 100644
--- a/include/configs/ADS860.h
+++ b/include/configs/ADS860.h
@@ -37,13 +37,19 @@
#define CONFIG_DRAM_50MHZ 1
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_DHCP \
- | CFG_CMD_IMMAP \
- | CFG_CMD_PCMCIA \
- | CFG_CMD_PING \
- )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_PING
+
+/* This is picked up again in fads.h */
+#define FADS_COMMANDS_ALREADY_DEFINED
#include "fads.h"
diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h
index 14d56bfd97d..6f640380739 100644
--- a/include/configs/AMX860.h
+++ b/include/configs/AMX860.h
@@ -61,7 +61,25 @@
#undef CONFIG_BOOTARGS
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
+
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -70,29 +88,22 @@
#endif
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -196,7 +207,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h
index ba4b1a2bc8c..d25aa74a452 100644
--- a/include/configs/AP1000.h
+++ b/include/configs/AP1000.h
@@ -66,18 +66,28 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_IRQ | \
- CFG_CMD_MVENV | \
- CFG_CMD_PCI | \
- CFG_CMD_PING \
- )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MVENV
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -89,7 +99,7 @@
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -188,7 +198,7 @@
*/
#define CFG_DCACHE_SIZE 16384
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -228,7 +238,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/APC405.h b/include/configs/APC405.h
index 3df99a008b9..f6495e4841a 100644
--- a/include/configs/APC405.h
+++ b/include/configs/APC405.h
@@ -67,27 +67,38 @@
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
@@ -106,7 +117,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -266,7 +277,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
index 1cd0280e217..0f301ec0c6a 100644
--- a/include/configs/AR405.h
+++ b/include/configs/AR405.h
@@ -71,17 +71,29 @@
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_BSP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -92,7 +104,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -207,7 +219,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index d03c05bf349..9adbba95441 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -53,25 +53,41 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
+
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_NAND | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -91,7 +107,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -132,40 +148,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
@@ -270,7 +264,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/Adder.h b/include/configs/Adder.h
index 0e6b50f8b0e..4304ecca7de 100644
--- a/include/configs/Adder.h
+++ b/include/configs/Adder.h
@@ -52,15 +52,26 @@
#define CFG_8xx_CPUCLK_MAX 133000000
#endif /* CONFIG_MPC852T */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_DHCP \
- | CFG_CMD_IMMAP \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- )
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */
diff --git a/include/configs/AdderUSB.h b/include/configs/AdderUSB.h
new file mode 100644
index 00000000000..a4f7f9a28fb
--- /dev/null
+++ b/include/configs/AdderUSB.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2006 CodeHermit.
+ * Bryan O'Donoghue <bodonoghue@codehermit.ie>
+ *
+ * Provides support for USB console on the Analogue & Micro Adder87x
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ADDERUSB__
+#define __ADDERUSB__
+
+/* Include the board port */
+#include "Adder.h"
+
+#define CONFIG_USB_DEVICE /* Include UDC driver */
+#define CONFIG_USB_TTY /* Bind the TTY driver to UDC */
+#define CFG_USB_EXTC_CLK 0x02 /* Oscillator on EXTC_CLK 2 */
+#define CFG_USB_BRG_CLK 0x04 /* or use Baud rate generator 0x04 */
+#define CFG_CONSOLE_IS_IN_ENV /* Console is in env */
+
+/* If you have a USB-IF assigned VendorID then you may wish to define
+ * your own vendor specific values either in BoardName.h or directly in
+ * usbd_vendor_info.h
+ */
+
+/*
+#define CONFIG_USBD_MANUFACTURER "CodeHermit.ie"
+#define CONFIG_USBD_PRODUCT_NAME "Das U-Boot"
+#define CONFIG_USBD_VENDORID 0xFFFF
+#define CONFIG_USBD_PRODUCTID_GSERIAL 0xFFFF
+#define CONFIG_USBD_PRODUCTID_CDCACM 0xFFFE
+*/
+
+#endif /* __ADDERUSB_H__ */
diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h
index c08b2c39f88..3f2f6140f63 100644
--- a/include/configs/Alaska8220.h
+++ b/include/configs/Alaska8220.h
@@ -39,12 +39,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -70,31 +64,40 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BOOTD | \
- CFG_CMD_CACHE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#define CONFIG_NET_MULTI
#define CONFIG_MII
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Autobooting
*/
@@ -282,7 +285,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -298,6 +301,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h
index ea50f41504c..d914dccfbb4 100644
--- a/include/configs/AmigaOneG3SE.h
+++ b/include/configs/AmigaOneG3SE.h
@@ -56,38 +56,46 @@
#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=4096"
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_AMIGA_PARTITION
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_NET | \
- CFG_CMD_IDE | \
- CFG_CMD_FDC | \
- CFG_CMD_CACHE | \
- CFG_CMD_CONSOLE| \
- CFG_CMD_USB | \
- CFG_CMD_BSP | \
- CFG_CMD_PCI )
-
-/* CFG_CMD_MII | \ */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FDC
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CONSOLE|
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_PCI
+
#define CONFIG_PCI 1
/* #define CONFIG_PCI_SCAN_SHOW 1 */
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
+#define atoi(x) simple_strtoul(x,NULL,10)
/*
* Miscellaneous configurable options
@@ -247,7 +255,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -348,8 +356,6 @@
#define CONFIG_3COM
/* #define CONFIG_BOOTP_RANDOM_DELAY */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
/*
* USB configuration
diff --git a/include/configs/B2.h b/include/configs/B2.h
index e55858d34bc..f1411db66c3 100644
--- a/include/configs/B2.h
+++ b/include/configs/B2.h
@@ -72,16 +72,26 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C )
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5
#define CONFIG_ETHADDR 00:50:c2:1e:af:fb
diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h
index 46bdfa2ee62..c11e9c911d3 100644
--- a/include/configs/BAB7xx.h
+++ b/include/configs/BAB7xx.h
@@ -66,14 +66,30 @@
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 |\
- CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE |\
- CFG_CMD_FDC | CFG_CMD_ELF)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_FDC
+#define CONFIG_CMD_ELF
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -86,7 +102,7 @@
*/
#define CONFIG_CONS_INDEX 1
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -436,7 +452,7 @@ extern unsigned long bab7xx_get_gclk_freq (void);
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
index 5b54f30e08d..5c2bfc991f5 100644
--- a/include/configs/BC3450.h
+++ b/include/configs/BC3450.h
@@ -61,11 +61,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -106,12 +101,6 @@
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
-#ifdef CONFIG_PCI
-# define ADD_PCI_CMD CFG_CMD_PCI
-#else
-# define ADD_PCI_CMD 0
-#endif
-
/*
* Video console
*/
@@ -126,12 +115,6 @@
# define CONFIG_SPLASH_SCREEN
# define CFG_CONSOLE_IS_IN_ENV
-#ifdef CONFIG_VIDEO
-# define ADD_BMP_CMD CFG_CMD_BMP
-#else
-# define ADD_BMP_CMD 0
-#endif
-
/*
* Partitions
*/
@@ -144,10 +127,7 @@
*/
#ifdef CONFIG_BC3450_USB
# define CONFIG_USB_OHCI
-# define ADD_USB_CMD CFG_CMD_USB
# define CONFIG_USB_STORAGE
-#else /* !CONFIG_BC3450_USB */
-# define ADD_USB_CMD 0
#endif /* CONFIG_BC3450_USB */
/*
@@ -158,66 +138,69 @@
CFG_POST_I2C)
#ifdef CONFIG_POST
-# define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#else
-# define CFG_CMD_POST_DIAG 0
#endif /* CONFIG_POST */
-/*
- * IDE
- */
-#ifdef CONFIG_BC3450_IDE
-# define ADD_IDE_CMD CFG_CMD_IDE
-#else
-# define ADD_IDE_CMD 0
-#endif /* CONFIG_BC3450_IDE */
/*
- * Filesystem support
+ * BOOTP options
*/
-#if defined (CONFIG_BC3450_IDE) || defined (CONFIG_BC3450_USB)
-#ifdef CONFIG_FAT
-# define ADD_FAT_CMD CFG_CMD_FAT
-#else
-# define ADD_FAT_CMD 0
-#endif /* CONFIG_FAT */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#ifdef CONFIG_EXT2
-# define ADD_EXT2_CMD CFG_CMD_EXT2
-#else
-# define ADD_EXT2_CMD 0
-#endif /* CONFIG_EXT2 */
-#endif /* CONFIG_BC3450_IDE / _USB */
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- ADD_BMP_CMD | \
- ADD_IDE_CMD | \
- ADD_FAT_CMD | \
- ADD_EXT2_CMD | \
- ADD_PCI_CMD | \
- ADD_USB_CMD | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP | \
- CFG_CMD_BSP)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_BSP
+
+#ifdef CONFIG_VIDEO
+ #define CONFIG_CMD_BMP
+#endif
+
+#ifdef CONFIG_BC3450_IDE
+ #define CONFIG_CMD_IDE
+#endif
+
+#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
+ #ifdef CONFIG_FAT
+ #define CONFIG_CMD_FAT
+ #endif
+
+ #ifdef CONFIG_EXT2
+ #define CONFIG_CMD_EXT2
+ #endif
+#endif
+
+#ifdef CONFIG_BC3450_USB
+ #define CONFIG_CMD_USB
+#endif
+
+#ifdef CONFIG_PCI
+ #define CONFIG_CMD_PCI
+#endif
+
+#ifdef CONFIG_POST
+ #define CONFIG_CMD_DIAG
+#endif
+
#define CONFIG_TIMESTAMP /* display image timestamps */
@@ -282,17 +265,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet
- * hasn't been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#if defined(CFG_IPBSPEED_133)
-# define CFG_PCISPEED_66 /* define for 66MHz speed */
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
+# define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@@ -450,7 +433,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -469,9 +452,13 @@
#define CFG_HZ 1000 /* dec freq: 1ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -488,7 +475,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
# define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
# define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/BMW.h b/include/configs/BMW.h
index 3bd43d83693..bb7856f675d 100644
--- a/include/configs/BMW.h
+++ b/include/configs/BMW.h
@@ -64,28 +64,35 @@
#define CFG_DOC_SUPPORT_2000 1
#define CFG_DOC_SUPPORT_MILLENNIUM 1
#define CFG_DOC_SHORT_TIMEOUT 1
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DOC | \
- CFG_CMD_ELF | \
- 0 )
-/* CFG_CMD_DOC required legacy NAND support */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_ELF
+
+
+/* CONFIG_CMD_DOC required legacy NAND support */
#define CFG_NAND_LEGACY
#if 0
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | \
- CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE)
-
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
#endif
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
-
/*
* Miscellaneous configurable options
*/
@@ -293,7 +300,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h
index e0262a8f674..ae32f6b14ac 100644
--- a/include/configs/CANBT.h
+++ b/include/configs/CANBT.h
@@ -56,13 +56,26 @@
#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | \
- CFG_CMD_IRQ | \
- CFG_CMD_EEPROM ) & \
- ~CFG_CMD_NET)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_EEPROM
+
+#undef CONFIG_CMD_NET
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -73,7 +86,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -173,7 +186,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index 7ec4599ebb5..0321650f3d2 100644
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -119,24 +119,36 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_NAND | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
@@ -155,7 +167,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -387,6 +399,8 @@
#define CFG_ENV_ADDR_REDUND 0xFFFFA000
#define CFG_ENV_SIZE_REDUND 0x2000
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CFG_NVRAM_SIZE 242 /* NVRAM size */
@@ -413,7 +427,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CCM.h b/include/configs/CCM.h
index e8994ffef79..9f06957d2ff 100644
--- a/include/configs/CCM.h
+++ b/include/configs/CCM.h
@@ -94,27 +94,35 @@
#define CONFIG_MAC_PARTITION /* nod used yet */
#define CONFIG_DOS_PARTITION
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BSP | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_EEPROM | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/*----------------------------------------------------------------------*/
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index 1cca2859f4b..21cd9c1f261 100644
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -60,28 +60,35 @@
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_BSP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_NAND | \
- CFG_CMD_I2C | \
- CFG_CMD_DATE | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -100,7 +107,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -148,36 +155,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
@@ -289,7 +278,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
index b882f7a9bfe..aea85233f96 100644
--- a/include/configs/CPC45.h
+++ b/include/configs/CPC45.h
@@ -54,27 +54,36 @@
#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FAT | \
- CFG_CMD_FLASH | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
*/
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
/*
@@ -325,7 +334,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index 56fd9a6d356..a3717b9052f 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -54,16 +54,29 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
+#undef CONFIG_CMD_NET
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -80,7 +93,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -216,7 +229,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index 047e2f1eef9..1b948f6382a 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -55,32 +55,43 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_EEPROM
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ELF | \
- CFG_CMD_MII | \
- CFG_CMD_EEPROM )
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -96,7 +107,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -260,7 +271,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index d756f447f7f..fb71c5fb040 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -37,6 +37,7 @@
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
+#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
@@ -56,28 +57,44 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
#if 0 /* test-only */
#define CONFIG_NETCONSOLE
@@ -97,11 +114,6 @@
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -117,7 +129,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -311,7 +323,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 852d94a410a..49943195b72 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -57,38 +57,48 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SUPPORT_VFAT
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-#define CFG_NAND_LEGACY
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -105,7 +115,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -284,7 +294,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index 2260327c3f8..29f92924478 100644
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -56,28 +56,44 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
#if 0 /* test-only */
#define CONFIG_NETCONSOLE
@@ -95,11 +111,6 @@
#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -115,7 +126,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -314,7 +325,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h
index 90d3a8d8fa3..318ada1a4fb 100644
--- a/include/configs/CPCI440.h
+++ b/include/configs/CPCI440.h
@@ -33,6 +33,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_CPCI440 1 /* Board is ebony */
#define CONFIG_440GP 1 /* Specifc GP support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
@@ -171,29 +172,27 @@
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#if 0 /* test-only */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_IRQ | \
- CFG_CMD_I2C | \
- CFG_CMD_KGDB | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF )
-#else
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM )
-/* test-only: support fehlt bisher... */
-/* CFG_CMD_IDE | \*/
-/* CFG_CMD_PCI | \*/
-#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -204,7 +203,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -268,7 +267,7 @@
*/
#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -290,7 +289,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
index bc23fc02788..48e29a20876 100644
--- a/include/configs/CPCI750.h
+++ b/include/configs/CPCI750.h
@@ -133,29 +133,36 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
-
-
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C \
- | CFG_CMD_CACHE \
- | CFG_CMD_EEPROM \
- | CFG_CMD_PCI \
- | CFG_CMD_ELF \
- | CFG_CMD_DATE \
- | CFG_CMD_NET \
- | CFG_CMD_PING \
- | CFG_CMD_IDE \
- | CFG_CMD_FAT \
- | CFG_CMD_EXT2 \
- )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+
+#define CONFIG_DOS_PARTITION
#define CONFIG_USE_CPCIDVI
@@ -179,7 +186,7 @@
#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -585,7 +592,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h
index 93d49f3862d..c7b623a1d6d 100644
--- a/include/configs/CPCIISER4.h
+++ b/include/configs/CPCIISER4.h
@@ -54,15 +54,36 @@
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -73,7 +94,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -189,7 +210,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index 16a9ea5dd71..c589f288789 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -68,9 +68,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -163,27 +161,37 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -348,7 +356,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index ce969ecdd18..b087ebaa0bc 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -69,9 +69,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -167,27 +165,31 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
#ifdef CONFIG_PCI
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DOC | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_PCI)
-#else /* ! PCI */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DOC | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C )
-#endif /* CONFIG_PCI */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+ #define CONFIG_CMD_PCI
+#endif
+
#define CFG_NAND_LEGACY
@@ -196,7 +198,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -369,7 +371,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h
index 63d7a924043..a965c125f3f 100644
--- a/include/configs/CRAYL1.h
+++ b/include/configs/CRAYL1.h
@@ -75,38 +75,42 @@
#define CONFIG_AUTOSCRIPT 1
-#define CONFIG_COMMANDS (\
- CFG_CMD_BDI|\
- CFG_CMD_IMI|\
- CFG_CMD_FLASH|\
- CFG_CMD_MEMORY|\
- CFG_CMD_NET|\
- CFG_CMD_ENV|\
- CFG_CMD_CONSOLE|\
- CFG_CMD_ASKENV|\
- CFG_CMD_ECHO|\
- CFG_CMD_IMMAP|\
- CFG_CMD_REGINFO|\
- CFG_CMD_DHCP|\
- CFG_CMD_DATE|\
- CFG_CMD_RUN|\
- CFG_CMD_I2C|\
- CFG_CMD_EEPROM|\
- CFG_CMD_DIAG|\
- CFG_CMD_AUTOSCRIPT|\
- CFG_CMD_SETGETDCR)
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_SETGETDCR
+
/*
- * optional BOOTP / DHCP fields
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK (\
- CONFIG_BOOTP_VENDOREX|\
- CONFIG_BOOTP_SUBNETMASK|\
- CONFIG_BOOTP_GATEWAY|\
- CONFIG_BOOTP_DNS|\
- CONFIG_BOOTP_HOSTNAME|\
- CONFIG_BOOTP_BOOTFILESIZE|\
- CONFIG_BOOTP_BOOTPATH)
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_VENDOREX
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_BOOTFILESIZE
+
/*
* how many time to fail & restart a net-TFTP before giving up & resetting
@@ -123,9 +127,6 @@
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/CU824.h b/include/configs/CU824.h
index acc84847178..68e816a7443 100644
--- a/include/configs/CU824.h
+++ b/include/configs/CU824.h
@@ -55,21 +55,29 @@
#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- 0 /* CFG_CMD_DATE */ | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+/*
+ * Command line configuration.
*/
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
/*
@@ -278,7 +286,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h
index 997e1baa9a7..627ea14826b 100644
--- a/include/configs/DASA_SIM.h
+++ b/include/configs/DASA_SIM.h
@@ -57,32 +57,35 @@
#define CONFIG_IPADDR 10.0.18.222
#define CONFIG_SERVERIP 10.0.18.190
-#if 0
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_IRQ | \
- CFG_CMD_BSP | \
- CFG_CMD_ASKENV | \
- CFG_CMD_ELF )
-#else
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BSP )
-#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+
#if 0 /* Does not appear to be used?! If it is used, needs to be fixed */
#define CONFIG_SOFT_I2C /* Software I2C support enabled */
#endif
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -184,7 +187,7 @@
*/
#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h
index bd7aff12cc1..db2e96c227d 100644
--- a/include/configs/DB64360.h
+++ b/include/configs/DB64360.h
@@ -215,8 +215,16 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
/*
* JFFS2 partitions
*
@@ -239,17 +247,20 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
#define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)"
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C \
- | CFG_CMD_EEPROM \
- | CFG_CMD_CACHE \
- | CFG_CMD_JFFS2 \
- | CFG_CMD_PCI \
- | CFG_CMD_NET )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+
/*
* Miscellaneous configurable options
@@ -261,7 +272,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -558,7 +569,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h
index 4b72e9b9e40..b5d3f773f38 100644
--- a/include/configs/DB64460.h
+++ b/include/configs/DB64460.h
@@ -153,8 +153,16 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
/*
* JFFS2 partitions
*
@@ -177,17 +185,20 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
#define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)"
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C \
- | CFG_CMD_EEPROM \
- | CFG_CMD_CACHE \
- | CFG_CMD_JFFS2 \
- | CFG_CMD_PCI \
- | CFG_CMD_NET )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+
/*
* Miscellaneous configurable options
@@ -199,7 +210,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -496,7 +507,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h
index b58846d8316..0ddf0e3aeb9 100644
--- a/include/configs/DK1C20.h
+++ b/include/configs/DK1C20.h
@@ -446,46 +446,55 @@
#define CONFIG_NIOS_ASMI /* Enable ASMI */
#define CFG_NIOS_ASMIBASE CFG_NIOS_CPU_ASMI0 /* ASMI base address */
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_CMD_ASKENV | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_CACHE | \
- CFG_CMD_DATE | \
- CFG_CMD_DOC | \
- CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_KGDB | \
- CFG_CMD_NAND | \
- CFG_CMD_NFS | \
- CFG_CMD_MMC | \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_REISER | \
- CFG_CMD_SCSI | \
- CFG_CMD_SPI | \
- CFG_CMD_VFD | \
- CFG_CMD_USB | \
- CFG_CMD_XIMG ) )
-
-
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_ASKENV
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_BSP
+#undef CONFIG_CMD_CACHE
+#undef CONFIG_CMD_DATE
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PCI
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_XIMG
+
/*------------------------------------------------------------------------
* COMPACT FLASH
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(CONFIG_CMD_IDE)
#define CONFIG_IDE_PREINIT /* Implement id_preinit */
#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */
#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */
@@ -503,12 +512,12 @@
#define CFG_CF_POWER 0x009209c0 /* CF Power FET PIO base*/
#define CFG_CF_ATASEL 0x009209d0 /* CF ATASEL PIO base */
-#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */
+#endif
/*------------------------------------------------------------------------
* KGDB
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 9600
#endif
diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h
index 3e3803cd235..0032fd3db71 100644
--- a/include/configs/DK1S10.h
+++ b/include/configs/DK1S10.h
@@ -454,47 +454,55 @@
#endif /* CFG_NIOS_CPU_PIO_NUMS */
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_CMD_ASKENV | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_CACHE | \
- CFG_CMD_DATE | \
- CFG_CMD_DOC | \
- CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_KGDB | \
- CFG_CMD_NAND | \
- CFG_CMD_NFS | \
- CFG_CMD_MMC | \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_SCSI | \
- CFG_CMD_SPI | \
- CFG_CMD_VFD | \
- CFG_CMD_USB | \
- CFG_CMD_XIMG ) )
-
-
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_ASKENV
+#undef COND_CMD_BEDBUG
+#undef COND_CMD_BMP
+#undef COND_CMD_BSP
+#undef COND_CMD_CACHE
+#undef COND_CMD_DATE
+#undef COND_CMD_DOC
+#undef COND_CMD_DTT
+#undef COND_CMD_EEPROM
+#undef COND_CMD_ELF
+#undef COND_CMD_FAT
+#undef COND_CMD_FDC
+#undef COND_CMD_FDOS
+#undef COND_CMD_HWFLOW
+#undef COND_CMD_IDE
+#undef COND_CMD_I2C
+#undef COND_CMD_JFFS2
+#undef COND_CMD_KGDB
+#undef COND_CMD_NAND
+#undef COND_CMD_NFS
+#undef COND_CMD_MMC
+#undef COND_CMD_MII
+#undef COND_CMD_PCI
+#undef COND_CMD_PCMCIA
+#undef COND_CMD_SCSI
+#undef COND_CMD_SPI
+#undef COND_CMD_VFD
+#undef COND_CMD_USB
+#undef COND_CMD_XIMG
+
/*------------------------------------------------------------------------
* KGDB
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 9600
#endif
diff --git a/include/configs/DP405.h b/include/configs/DP405.h
index 2ae794dc26c..2eadbea35d6 100644
--- a/include/configs/DP405.h
+++ b/include/configs/DP405.h
@@ -55,17 +55,29 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BSP | \
- CFG_CMD_DHCP | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -87,7 +99,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -235,7 +247,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/DU405.h b/include/configs/DU405.h
index 5489a539360..5c595f57d26 100644
--- a/include/configs/DU405.h
+++ b/include/configs/DU405.h
@@ -58,21 +58,33 @@
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_ELF | \
- CFG_CMD_MII | \
- CFG_CMD_DATE | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/
@@ -85,7 +97,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -225,7 +237,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index 720b335b099..dae5295dd1b 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -40,9 +40,8 @@
#define CONFIG_MISC_INIT_R
-#define FEC_ENET
-#define CONFIG_ETHADDR 00:CF:52:82:EB:01
-
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 9600
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
@@ -68,17 +67,61 @@
#define CFG_ENV_IS_IN_FLASH 1
#endif
-/*#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB))
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_LOADB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:CF:52:82:EB:01
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* CONFIG_MCFFEC */
#define CONFIG_BOOTDELAY 5
#define CFG_PROMPT "\nEV123 U-Boot> "
#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -110,9 +153,6 @@
*/
#define CFG_MBAR 0x40000000
-#define CFG_DISCOVER_PHY
-/* #define CFG_ENET_BD_BASE 0x380000 */
-
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
@@ -139,6 +179,7 @@
#define CFG_FLASH_BASE 0xFFE00000
#define CFG_INT_FLASH_BASE 0xF0000000
+#define CFG_INT_FLASH_ENABLE 0x21
/* If M5282 port is fully implemented the monitor base will be behind
* the vector table. */
diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h
index 2c99b4b1628..bb771887243 100644
--- a/include/configs/ELPPC.h
+++ b/include/configs/ELPPC.h
@@ -66,12 +66,25 @@
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_JFFS2
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -84,7 +97,7 @@
*/
#define CONFIG_CONS_INDEX 1
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -317,7 +330,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h
index e73bcec4485..f927a2c9cca 100644
--- a/include/configs/ELPT860.h
+++ b/include/configs/ELPT860.h
@@ -81,7 +81,15 @@
""
#define CONFIG_BOOTCOMMAND "run ramboot"
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
@@ -91,12 +99,15 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+
/*
* Miscellaneous configurable options
@@ -104,7 +115,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -224,7 +235,7 @@
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h
index 5507f352b90..cfa6335927a 100644
--- a/include/configs/EP1C20.h
+++ b/include/configs/EP1C20.h
@@ -160,25 +160,36 @@
#define CONFIG_IPADDR 192.168.2.21
#define CONFIG_SERVERIP 192.168.2.16
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IRQ | \
- CFG_CMD_LOADS | \
- CFG_CMD_LOADB | \
- CFG_CMD_MEMORY | \
- CFG_CMD_MISC | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CFG_CMD_RUN | \
- CFG_CMD_SAVES )
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
/*------------------------------------------------------------------------
* MISC
diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h
index 6eca9f23dc7..7c526f759e7 100644
--- a/include/configs/EP1S10.h
+++ b/include/configs/EP1S10.h
@@ -154,25 +154,35 @@
#define CONFIG_IPADDR 192.168.2.21
#define CONFIG_SERVERIP 192.168.2.16
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IRQ | \
- CFG_CMD_LOADS | \
- CFG_CMD_LOADB | \
- CFG_CMD_MEMORY | \
- CFG_CMD_MISC | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CFG_CMD_RUN | \
- CFG_CMD_SAVES )
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVES
+
/*------------------------------------------------------------------------
* MISC
diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h
index 976e79acb6f..1fe8f68c2e6 100644
--- a/include/configs/EP1S40.h
+++ b/include/configs/EP1S40.h
@@ -154,25 +154,35 @@
#define CONFIG_IPADDR 192.168.2.21
#define CONFIG_SERVERIP 192.168.2.16
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IRQ | \
- CFG_CMD_LOADS | \
- CFG_CMD_LOADB | \
- CFG_CMD_MEMORY | \
- CFG_CMD_MISC | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CFG_CMD_RUN | \
- CFG_CMD_SAVES )
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVES
+
/*------------------------------------------------------------------------
* MISC
diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h
index 738763b86ff..89e0eebeead 100644
--- a/include/configs/EP88x.h
+++ b/include/configs/EP88x.h
@@ -50,15 +50,25 @@
#define CFG_8xx_CPUCLK_MIN 40000000
#define CFG_8xx_CPUCLK_MAX 133000000
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_DHCP \
- | CFG_CMD_IMMAP \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- )
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm fe060000" /* Autoboot command */
diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h
index c203aea9245..5d48d2bbb68 100644
--- a/include/configs/ERIC.h
+++ b/include/configs/ERIC.h
@@ -96,23 +96,26 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH)
/*
- * #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | \
- * CFG_CMD_KGDB | CFG_CMD_I2C | CFG_CMD_EEPROM | \
- * CFG_CMD_ENV | CFG_CMD_FLASH)
+ * BOOTP options
*/
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-/* CFG_CMD_ENV est definie */
-/* ((CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_KGDB) & ~(CFG_CMD_ENV))
+
+/*
+ * Command line configuration.
*/
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -121,7 +124,7 @@
*/
#undef CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -325,7 +328,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -365,7 +368,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h
index b176c6f37e9..66e1203b7dd 100644
--- a/include/configs/ESTEEM192E.h
+++ b/include/configs/ESTEEM192E.h
@@ -70,10 +70,21 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "BOOT: " /* Monitor Command Prompt */
diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h
index d55eb7d192e..ed439b1922b 100644
--- a/include/configs/ETX094.h
+++ b/include/configs/ETX094.h
@@ -82,17 +82,29 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -179,7 +191,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h
index 78e57168854..1c44a0c6d73 100644
--- a/include/configs/EVB64260.h
+++ b/include/configs/EVB64260.h
@@ -103,21 +103,30 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ASKENV)
+#define CONFIG_CMD_ASKENV
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -391,7 +400,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h
index d85be424a2a..a3f38bb3a32 100644
--- a/include/configs/EXBITGEN.h
+++ b/include/configs/EXBITGEN.h
@@ -82,10 +82,21 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -94,7 +105,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -206,7 +217,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h
index 1b562d60635..f810af2ceca 100644
--- a/include/configs/FADS823.h
+++ b/include/configs/FADS823.h
@@ -46,7 +46,6 @@
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-/*Now included by CFG_CMD_PCMCIA */
/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */
/* Video related */
@@ -105,17 +104,39 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT ":>" /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -185,12 +206,13 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h
index 2a986f07680..a09c0e0393f 100644
--- a/include/configs/FADS850SAR.h
+++ b/include/configs/FADS850SAR.h
@@ -61,15 +61,28 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
/*
* Miscellaneous configurable options
*/
#undef CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT ":>" /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -143,12 +156,13 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h
index 8babee140f9..431844c7f3d 100644
--- a/include/configs/FLAGADM.h
+++ b/include/configs/FLAGADM.h
@@ -62,21 +62,39 @@
/*#define CONFIG_WATCHDOG*/ /* watchdog enabled */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
-#define CONFIG_COMMANDS (CFG_CMD_BDI | CFG_CMD_IMI | CFG_CMD_CACHE | \
- CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_LOADS | \
- CFG_CMD_ENV | CFG_CMD_REGINFO | CFG_CMD_IMMAP | CFG_CMD_NET)
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_NET
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "EEG> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -152,7 +170,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h
index 0dd21bc618c..3b0ddb4ec60 100644
--- a/include/configs/FPS850L.h
+++ b/include/configs/FPS850L.h
@@ -39,45 +39,90 @@
#undef CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 19200
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "bootm 40020000" /* autoboot command */
+#define CONFIG_BAUDRATE 115200
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk/ppc_8xx\0" \
+ "bootfile=/tftpboot/fps850L/uImage\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
+
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~( \
- CFG_CMD_CONSOLE | \
- CFG_CMD_BDI | \
- CFG_CMD_LOADS | \
- CFG_CMD_LOADB | \
- CFG_CMD_CACHE ) )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -160,7 +205,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h
index 423d74ea07a..6fec07540cf 100644
--- a/include/configs/FPS860L.h
+++ b/include/configs/FPS860L.h
@@ -40,44 +40,89 @@
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 115200
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "bootm 40040000" /* autoboot command */
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk/ppc_8xx\0" \
+ "bootfile=/tftpboot/fps850L/uImage\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -160,7 +205,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/G2000.h b/include/configs/G2000.h
index db42fd06fe5..9c713c6c26f 100644
--- a/include/configs/G2000.h
+++ b/include/configs/G2000.h
@@ -88,20 +88,32 @@
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
#endif
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -120,7 +132,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -324,7 +336,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index 6613f90a770..bfbf3a839cf 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -132,9 +132,12 @@
/*
* BOOTP options
*/
-#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE \
- )
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
/*
* The GEN860T network interface uses the on-chip 10/100 FEC with
@@ -222,35 +225,30 @@
CFG_POST_UART | \
CFG_POST_SPR )
-#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
-#else
-#define CFG_CMD_POST_DIAG 0
-#endif
/*
- * List of available monitor commands. Use the system default list
- * plus add some of the "non-standard" commands back in.
- * See ./cmd_confdefs.h
- */
-#define BASE_CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_FPGA | \
- CFG_CMD_MII | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_POST_DIAG )
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_BEDBUG
#if !defined(CONFIG_SC)
-#define CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC )
-#else
-#define CONFIG_COMMANDS BASE_CONFIG_COMMANDS
+ #define CONFIG_CMD_DOC
+#endif
+
+#ifdef CONFIG_POST
+#define CONFIG_CMD_DIAG
#endif
/*
@@ -279,11 +277,6 @@
#define CFG_FPGA_PROG_FEEDBACK
-/************************************************************************
- * This must be included AFTER the definition of any CONFIG_COMMANDS
- */
-#include <cmd_confdefs.h>
-
#define CFG_NAND_LEGACY
/*
@@ -306,7 +299,7 @@
/*
* Set buffer size for console I/O
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024
#else
#define CFG_CBSIZE 256
@@ -471,7 +464,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */
#endif
diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h
index 8c01d97fa33..785355a8e66 100644
--- a/include/configs/GENIETV.h
+++ b/include/configs/GENIETV.h
@@ -105,15 +105,28 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT ":>" /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -193,7 +206,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/GTH.h b/include/configs/GTH.h
index 03b96594979..79f5714e6f0 100644
--- a/include/configs/GTH.h
+++ b/include/configs/GTH.h
@@ -97,18 +97,32 @@
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE)
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_PROMPT "=>" /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -190,7 +204,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index dc40ebc861d..8967b3fc601 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -98,26 +98,40 @@
#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
#define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */
-#define ADD_BMP_CMD CFG_CMD_BMP
-#else
-#define ADD_BMP_CMD 0
#endif /* CONFIG_VIDEO */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_EXT2 | \
- CFG_CMD_ELF | \
- CFG_CMD_NAND | \
- CFG_CMD_I2C | \
- CFG_CMD_DATE | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- ADD_BMP_CMD | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -127,11 +141,6 @@
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -148,7 +157,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -198,36 +207,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
@@ -377,7 +368,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h
index 68647407733..26dd954c18a 100644
--- a/include/configs/HIDDEN_DRAGON.h
+++ b/include/configs/HIDDEN_DRAGON.h
@@ -52,16 +52,27 @@
#define CONFIG_BAUDRATE 9600
#define CONFIG_DRAM_SPEED 100 /* MHz */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_NET | \
- CFG_CMD_PCI | \
- CFG_CMD_PING )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
/*
* Miscellaneous configurable options
@@ -363,7 +374,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h
index 7cce876924e..02ae5d005df 100644
--- a/include/configs/HMI10.h
+++ b/include/configs/HMI10.h
@@ -117,7 +117,15 @@
#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -125,31 +133,25 @@
#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
#ifdef CONFIG_SPLASH_SCREEN
-# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BMP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#else
-# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+ #define CONFIG_CMD_BMP
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -164,7 +166,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -247,7 +249,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index f84e356216b..1ff71081302 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -60,18 +60,30 @@
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_NAND | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -88,7 +100,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -135,38 +147,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
@@ -271,7 +263,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h
index 35d84aedf8a..bd0894c29ab 100644
--- a/include/configs/IAD210.h
+++ b/include/configs/IAD210.h
@@ -84,7 +84,15 @@
/* #define CONFIG_STATUS_LED 1*/ /* Status LED enabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
# undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
# define CONFIG_FEC_ENET 1 /* use FEC ethernet */
@@ -123,20 +131,23 @@
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -217,7 +228,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h
index cd17935893f..da54cef534f 100644
--- a/include/configs/ICU862.h
+++ b/include/configs/ICU862.h
@@ -81,7 +81,15 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
@@ -123,25 +131,28 @@
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -223,12 +234,13 @@
#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */
#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index 29eb874dbf0..85d2bb3f513 100644
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -128,9 +128,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -159,24 +157,34 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_NFS | \
- CFG_CMD_NAND | \
- CFG_CMD_I2C | \
- CFG_CMD_SNTP )
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -234,7 +242,7 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
#define CFG_NAND_LEGACY
#define CFG_NAND0_BASE 0xE1000000
@@ -295,7 +303,7 @@
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0)))
-#endif /* CFG_CMD_NAND */
+#endif /* CONFIG_CMD_NAND */
/*-----------------------------------------------------------------------
* Hard Reset Configuration Words
@@ -355,7 +363,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -474,7 +482,7 @@
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
ORxG_SCY_6_CLK )
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
/* Bank 1 - NAND Flash
*/
#define CFG_NAND_BASE CFG_NAND0_BASE
diff --git a/include/configs/IP860.h b/include/configs/IP860.h
index 0e20e567634..bd961d8426a 100644
--- a/include/configs/IP860.h
+++ b/include/configs/IP860.h
@@ -88,28 +88,32 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-
-/*----------------------------------------------------------------------*/
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/*----------------------------------------------------------------------*/
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -202,7 +206,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h
index c1565fc037c..6fee4558dee 100644
--- a/include/configs/IPHASE4539.h
+++ b/include/configs/IPHASE4539.h
@@ -67,8 +67,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -95,7 +94,14 @@
#define CONFIG_8260_CLKIN 66666666 /* in Hz */
#define CONFIG_BAUDRATE 19200
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
/*
* select i2c support configuration
@@ -124,17 +130,18 @@
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#endif /* CONFIG_SOFT_I2C */
-#define CONFIG_COMMANDS CONFIG_CMD_DFL
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/ram rw"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -149,7 +156,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -257,7 +264,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h
index 706bdb94f57..965b515f0e6 100644
--- a/include/configs/ISPAN.h
+++ b/include/configs/ISPAN.h
@@ -58,8 +58,7 @@
* for FCC).
*
* If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
- * be defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */
#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */
@@ -106,17 +105,28 @@
#define CONFIG_8260_CLKIN 65536000 /* in Hz */
#define CONFIG_BAUDRATE 38400
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \
- | CFG_CMD_ASKENV \
- | CFG_CMD_DHCP \
- | CFG_CMD_IMMAP \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- | CFG_CMD_REGINFO \
- )
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */
diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h
index a0cb1dd484b..1142f2afac1 100644
--- a/include/configs/IVML24.h
+++ b/include/configs/IVML24.h
@@ -72,24 +72,33 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-#define CONFIG_BOOTP_MASK \
- ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-/*----------------------------------------------------------------------*/
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -182,7 +191,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h
index 46b4d535462..bd19dad1ff4 100644
--- a/include/configs/IVMS8.h
+++ b/include/configs/IVMS8.h
@@ -72,24 +72,32 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE)
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-#define CONFIG_BOOTP_MASK \
- ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-/*----------------------------------------------------------------------*/
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -179,7 +187,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 598811240a7..4c16d22959c 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -37,11 +37,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -69,7 +64,6 @@
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
-#define ADD_PCI_CMD CFG_CMD_PCI
#endif
#define CFG_XLB_PIPELINING 1
@@ -80,11 +74,8 @@
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
-#else /* MPC5100 */
-
+#else
#define CONFIG_MII 1
-#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
-
#endif
/* Partitions */
@@ -93,31 +84,44 @@
#define CONFIG_ISO_PARTITION
/* USB */
-#if 1
-#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
-#endif
+#define CFG_OHCI_BE_CONTROLLER
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE MPC5XXX_USB
+#define CFG_USB_OHCI_SLOT_NAME "mpc5200"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP | \
- ADD_PCI_CMD | \
- ADD_USB_CMD )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CFG_LOWBOOT 1
@@ -167,19 +171,16 @@
* IPB Bus clocking configuration.
*/
#if defined(CONFIG_LITE5200B)
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#else
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
#endif /* CONFIG_MPC5200 */
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
@@ -312,7 +313,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -328,6 +329,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/JSE.h b/include/configs/JSE.h
index ccd1f19903b..ea3b0b4a325 100644
--- a/include/configs/JSE.h
+++ b/include/configs/JSE.h
@@ -49,6 +49,7 @@
/* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
#define CONFIG_SYSTEMACE 1
#define CFG_SYSTEMACE_BASE 0xf0000000
+#define CFG_SYSTEMACE_WIDTH 8
#define CONFIG_DOS_PARTITION 1
/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
@@ -134,20 +135,32 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_FLASH | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_PCI | \
- CFG_CMD_PING )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
/* watchdog disabled */
#undef CONFIG_WATCHDOG
@@ -166,7 +179,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -271,7 +284,7 @@
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -297,7 +310,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h
index 2ad6f06985a..3644e43885e 100644
--- a/include/configs/KAREF.h
+++ b/include/configs/KAREF.h
@@ -38,6 +38,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
#define CONFIG_440GX 1 /* Specifc GX support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
@@ -177,23 +178,34 @@
#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
-/*-----------------------------------------------------------------------
- * Console/Commands/Parser
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_I2C | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_PING | \
- CFG_CMD_DIAG | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_ELF | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+
/* Include NetConsole support */
#define CONFIG_NETCONSOLE
@@ -202,10 +214,6 @@
#define CONFIG_AUTO_COMPLETE 1
#define CFG_ALT_MEMTEST 1 /* use real memory test */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
@@ -216,7 +224,7 @@
/*-----------------------------------------------------------------------
* Console Buffer
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -262,7 +270,6 @@
#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
#define CFG_PCI_TARGET_INIT /* let board init pci target*/
#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
@@ -279,7 +286,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
#endif
@@ -291,7 +298,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
#endif
diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h
index 9b950fc5d16..f6c31ea8497 100644
--- a/include/configs/KUP4K.h
+++ b/include/configs/KUP4K.h
@@ -89,7 +89,15 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -156,32 +164,31 @@
#define CONFIG_POST (CFG_POST_CPU | \
CFG_POST_RTC | \
CFG_POST_I2C)
-
-#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
-#else
-#define CFG_CMD_POST_DIAG 0
-#endif
#endif
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#ifdef CONFIG_POST
+ #define CONFIG_CMD_DIAG
+#endif
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -269,7 +276,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h
index cd38b0f2c2f..e558aa481b3 100644
--- a/include/configs/KUP4X.h
+++ b/include/configs/KUP4X.h
@@ -99,7 +99,15 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -167,34 +175,33 @@
#define CONFIG_POST (CFG_POST_CPU | \
CFG_POST_RTC | \
CFG_POST_I2C)
-
-#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
-#else
-#define CFG_CMD_POST_DIAG 0
-#endif
#endif
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_SNTP | \
- CFG_CMD_USB )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_POST
+ #define CONFIG_CMD_DIAG
+#endif
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -281,7 +288,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h
index e44f1cc627a..46edd08a91f 100644
--- a/include/configs/LANTEC.h
+++ b/include/configs/LANTEC.h
@@ -74,64 +74,68 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_CMD_MINIMAL 0
-#define CONFIG_CMD_TINY (CFG_CMD_FLASH | \
- CFG_CMD_MEMORY | \
- CFG_CMD_LOADS | \
- CFG_CMD_LOADB)
-#define CONFIG_CMD_NORMAL (CONFIG_CMD_DFL & ~CFG_CMD_BOOTD & ~CFG_CMD_REISER)
-#define CONFIG_CMD_GDB (CONFIG_CMD_NORMAL | CFG_CMD_KGDB)
-#define CONFIG_CMD_FULL (CFG_CMD_ALL & ~CFG_CMD_BEDBUG \
- & ~CFG_CMD_BMP \
- & ~CFG_CMD_BSP \
- & ~CFG_CMD_DISPLAY \
- & ~CFG_CMD_DOC \
- & ~CFG_CMD_DTT \
- & ~CFG_CMD_EEPROM \
- & ~CFG_CMD_ELF \
- & ~CFG_CMD_EXT2 \
- & ~CFG_CMD_FDC \
- & ~CFG_CMD_FDOS \
- & ~CFG_CMD_HWFLOW \
- & ~CFG_CMD_I2C \
- & ~CFG_CMD_IDE \
- & ~CFG_CMD_IRQ \
- & ~CFG_CMD_JFFS2 \
- & ~CFG_CMD_KGDB \
- & ~CFG_CMD_MII \
- & ~CFG_CMD_MMC \
- & ~CFG_CMD_NAND \
- & ~CFG_CMD_PCI \
- & ~CFG_CMD_PCMCIA \
- & ~CFG_CMD_REISER \
- & ~CFG_CMD_SCSI \
- & ~CFG_CMD_SPI \
- & ~CFG_CMD_UNIVERSE\
- & ~CFG_CMD_USB \
- & ~CFG_CMD_VFD \
- & ~CFG_CMD_XIMG )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-#if CONFIG_LANTEC >= 2
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_BSP
+#undef CONFIG_CMD_DISPLAY
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_MFSL
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_PCI
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_UNIVERSE
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_XIMG
+
+#if !(CONFIG_LANTEC >= 2)
+ #undef CONFIG_CMD_DATE
+ #undef CONFIG_CMD_NET
#endif
+
#if CONFIG_LANTEC >= 2
-# define CONFIG_COMMANDS CONFIG_CMD_FULL
-#else
-# define CONFIG_COMMANDS (CONFIG_CMD_FULL & ~CFG_CMD_DATE & ~CFG_CMD_NET)
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -203,7 +207,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
new file mode 100644
index 00000000000..7f544c839fd
--- /dev/null
+++ b/include/configs/M5235EVB.h
@@ -0,0 +1,261 @@
+/*
+ * Configuation settings for the Freescale MCF5329 FireEngine board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5235EVB_H
+#define _M5235EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF523x /* define processor family */
+#define CONFIG_M5235 /* define processor type */
+
+#undef DEBUG
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x00000300
+#define CFG_IMMR CFG_MBAR
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#define CONFIG_BOOTFILE "u-boot.bin"
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* FEC_ENET */
+
+#define CONFIG_HOSTNAME M5235EVB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off ffe00000 ffe3ffff;" \
+ "era ffe00000 ffe3ffff;" \
+ "cp.b ${loadaddr} ffe00000 ${filesize};"\
+ "save\0" \
+ ""
+
+#define CONFIG_PRAM 512 /* 512 KB */
+#define CFG_PROMPT "-> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#if defined(CONFIG_KGDB)
+# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE+0x20000)
+
+#define CFG_HZ 1000
+#define CFG_CLK 75000000
+#define CFG_CPU_CLK CFG_CLK * 2
+
+#define CFG_MBAR 0x40000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x20000000
+#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL 0x21
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE - 0x10)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+
+#define CFG_BOOTPARAMS_LEN 64*1024
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
+#ifdef NORFLASH_PS32BIT
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
+#else
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#endif
+# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+#endif
+
+#define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_IS_EMBEDDED 1
+#ifdef NORFLASH_PS32BIT
+# define CFG_ENV_OFFSET (0x8000)
+# define CFG_ENV_SIZE 0x4000
+# define CFG_ENV_SECT_SIZE 0x4000
+#else
+# define CFG_ENV_OFFSET (0x4000)
+# define CFG_ENV_SIZE 0x2000
+# define CFG_ENV_SECT_SIZE 0x2000
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ * CS6 - Available
+ * CS7 - Available
+ */
+#ifdef NORFLASH_PS32BIT
+# define CFG_CS0_BASE 0xFFC0
+# define CFG_CS0_MASK 0x003f0001
+# define CFG_CS0_CTRL 0x1D00
+#else
+# define CFG_CS0_BASE 0xFFE0
+# define CFG_CS0_MASK 0x001f0001
+# define CFG_CS0_CTRL 0x1D80
+#endif
+
+#endif /* _M5329EVB_H */
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
new file mode 100644
index 00000000000..de7ea42930f
--- /dev/null
+++ b/include/configs/M5249EVB.h
@@ -0,0 +1,194 @@
+/*
+ * Configuation settings for the esd TASREG board.
+ *
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5249EVB_H
+#define _M5249EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF52x2 /* define processor family */
+#define CONFIG_M5249 /* define processor type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 19200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+
+#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
+
+/*
+ * BOOTP options
+ */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_BOOTPATH
+#undef CONFIG_BOOTP_GATEWAY
+#undef CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET
+
+#define CFG_PROMPT "=> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
+#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+
+#define CFG_LOAD_ADDR 0x200000 /* default load address */
+
+#define CFG_MEMTEST_START 0x400
+#define CFG_MEMTEST_END 0x380000
+
+#define CFG_HZ 1000
+
+/*
+ * Clock configuration: enable only one of the following options
+ */
+
+#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */
+#define CFG_FAST_CLK 1 /* MCF5249 can run at 140MHz */
+#define CFG_CLK 132025600 /* MCF5249 can run at 140MHz */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_MBAR 0x10000000 /* Register Base Addrs */
+#define CFG_MBAR2 0x80000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x20000000
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_FLASH_BASE (CFG_CSAR0 << 16)
+
+#if 0 /* test-only */
+#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
+#endif
+
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+
+#define CFG_MONITOR_LEN 0x20000
+#define CFG_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */
+#define CFG_BOOTPARAMS_LEN 64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+# define CFG_FLASH_CHECKSUM
+# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define CFG_CSAR0 0xffe0
+#define CFG_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */
+/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
+#define CFG_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
+
+/* CS1 - FPGA, address 0xe0000000 */
+#define CFG_CSAR1 0xe000
+#define CFG_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */
+#define CFG_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
+#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
+#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */
+#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */
+#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */
+#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
+#define CFG_GPIO1_LED 0x00400000 /* user led */
+
+#endif /* M5249 */
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
new file mode 100644
index 00000000000..48170e7a35a
--- /dev/null
+++ b/include/configs/M5253EVBE.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _M5253EVBE_H
+#define _M5253EVBE_H
+
+#define CONFIG_MCF52x2 /* define processor family */
+#define CONFIG_M5253 /* define processor type */
+#define CONFIG_M5253EVBE /* define board type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 19200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG /* disable watchdog */
+
+#define CONFIG_BOOTDELAY 5
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_IS_IN_FLASH 1
+#else
+#define CFG_ENV_ADDR 0xffe04000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_IS_IN_FLASH 1
+#endif
+
+/*
+ * BOOTP options
+ */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_BOOTPATH
+#undef CONFIG_BOOTP_GATEWAY
+#undef CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+
+/* ATA */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_IDE_RESET 1
+#define CONFIG_IDE_PREINIT 1
+#define CONFIG_ATAPI
+#undef CONFIG_LBA48
+
+#define CFG_IDE_MAXBUS 1
+#define CFG_IDE_MAXDEVICE 2
+
+#define CFG_ATA_BASE_ADDR (CFG_MBAR2 + 0x800)
+#define CFG_ATA_IDE0_OFFSET 0
+
+#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
+#define CFG_ATA_STRIDE 4 /* Interval between registers */
+#define _IO_BASE 0
+
+#define CFG_PROMPT "=> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR 0x00100000
+
+#define CFG_MEMTEST_START 0x400
+#define CFG_MEMTEST_END 0x380000
+
+#define CFG_HZ 1000
+
+#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */
+#define CFG_FAST_CLK
+#ifdef CFG_FAST_CLK
+# define CFG_PLLCR 0x1243E054
+# define CFG_CLK 140000000
+#else
+# define CFG_PLLCR 0x135a4140
+# define CFG_CLK 70000000
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_MBAR 0x10000000 /* Register Base Addrs */
+#define CFG_MBAR2 0x80000000 /* Module Base Addrs 2 */
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x20000000
+#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_MONITOR_BASE 0x20000
+#else
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#endif
+
+#define CFG_MONITOR_LEN 0x40000
+#define CFG_MALLOC_LEN (256 << 10)
+#define CFG_BOOTPARAMS_LEN (64*1024)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/* FLASH organization */
+#define CFG_FLASH_BASE 0xffe00000
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
+#define CFG_FLASH_ERASE_TOUT 1000
+
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#define CFG_FLASH_SIZE 0x200000
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+
+/* Cache Configuration */
+#define CFG_CACHELINE_SIZE 16
+
+/* Port configuration */
+#define CFG_FECI2C 0xF0
+
+#define CFG_CSAR0 0xFFE0
+#define CFG_CSMR0 0x001F0021
+#define CFG_CSCR0 0x1D80
+
+#define CFG_CSAR1 0
+#define CFG_CSMR1 0
+#define CFG_CSCR1 0
+
+#define CFG_CSAR2 0
+#define CFG_CSMR2 0
+#define CFG_CSCR2 0
+
+#define CFG_CSAR3 0
+#define CFG_CSMR3 0
+#define CFG_CSCR3 0
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
+#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
+#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */
+#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */
+#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */
+#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
+#define CFG_GPIO1_LED 0x00400000 /* user led */
+
+#endif /* _M5253EVB_H */
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index f0fc0134341..798ec0c7a4c 100644
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -31,7 +31,6 @@
#ifndef _M5271EVB_H
#define _M5271EVB_H
-#define DEBUG
#undef DEBUG
/*
@@ -41,46 +40,119 @@
#define CONFIG_M5271 /* define processor type */
#define CONFIG_M5271EVB /* define board type */
-#define CONFIG_IPADDR 192.168.30.1
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_ETHADDR 00:06:3b:01:41:55
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG /* disable watchdog */
-#define CONFIG_BOOTDELAY 5
-
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CFG_ENV_OFFSET 0x4000
-#define CFG_ENV_SECT_SIZE 0x2000
-#define CFG_ENV_IS_IN_FLASH 1
#else
#define CFG_ENV_ADDR 0xffe04000
+#endif
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
-#endif
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_NET ) & ~(CFG_CMD_LOADS | CFG_CMD_LOADB))
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x00000300
+#define CFG_IMMR CFG_MBAR
+
+#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#define CONFIG_BOOTFILE "u-boot.bin"
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_RETRY_COUNT 5
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* FEC_ENET */
+
+#define CONFIG_HOSTNAME M5235EVB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off ffe00000 ffe2ffff;" \
+ "era ffe00000 ffe2ffff;" \
+ "cp.b ${loadaddr} 0 ${filesize};" \
+ "save\0" \
+ ""
#define CFG_PROMPT "=> "
-#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00100000
@@ -98,16 +170,11 @@
#define CFG_MBAR 0x40000000 /* Register Base Addrs */
-/* Enable FEC ethernet */
-#define FEC_ENET
-#define CONFIG_NET_RETRY_COUNT 5
-#define CFG_ENET_BD_BASE 0x480000
-
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
-#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -118,7 +185,7 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#ifdef CONFIG_MONITOR_IS_IN_RAM
@@ -136,11 +203,11 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/* FLASH organization */
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 1000
#define CFG_FLASH_CFI 1
@@ -153,4 +220,4 @@
/* Port configuration */
#define CFG_FECI2C 0xF0
-#endif /* _M5271EVB_H */
+#endif /* _M5271EVB_H */
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 5fd6a95c4d1..2b8734b4c6d 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -33,18 +33,20 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_MCF52x2 /* define processor family */
-#define CONFIG_M5272 /* define processor type */
+#define CONFIG_MCF52x2 /* define processor family */
+#define CONFIG_M5272 /* define processor type */
-#define FEC_ENET
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-#define CONFIG_WATCHDOG
+#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
-#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
+#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -60,30 +62,90 @@
#define CFG_ENV_IS_IN_FLASH 1
#endif
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) | \
- CFG_CMD_MII)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* CONFIG_MCFFEC */
+
+#define CONFIG_HOSTNAME M5272C3
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off ffe00000 ffe3ffff;" \
+ "era ffe00000 ffe3ffff;" \
+ "cp.b ${loadaddr} ffe00000 ${filesize};"\
+ "save\0" \
+ ""
#define CFG_PROMPT "-> "
-#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x20000
-
#define CFG_MEMTEST_START 0x400
#define CFG_MEMTEST_END 0x380000
-
#define CFG_HZ 1000
#define CFG_CLK 66000000
@@ -92,20 +154,15 @@
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
-
#define CFG_MBAR 0x10000000 /* Register Base Addrs */
-
#define CFG_SCR 0x0003;
#define CFG_SPR 0xffff;
-#define CFG_DISCOVER_PHY
-#define CFG_ENET_BD_BASE 0x380000
-
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
-#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -116,7 +173,7 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
+#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#ifdef CONFIG_MONITOR_IS_IN_RAM
@@ -134,13 +191,13 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 1000
/*-----------------------------------------------------------------------
@@ -153,25 +210,18 @@
*/
#define CFG_BR0_PRELIM 0xFFE00201
#define CFG_OR0_PRELIM 0xFFE00014
-
#define CFG_BR1_PRELIM 0
#define CFG_OR1_PRELIM 0
-
#define CFG_BR2_PRELIM 0x30000001
#define CFG_OR2_PRELIM 0xFFF80000
-
#define CFG_BR3_PRELIM 0
#define CFG_OR3_PRELIM 0
-
#define CFG_BR4_PRELIM 0
#define CFG_OR4_PRELIM 0
-
#define CFG_BR5_PRELIM 0
#define CFG_OR5_PRELIM 0
-
#define CFG_BR6_PRELIM 0
#define CFG_OR6_PRELIM 0
-
#define CFG_BR7_PRELIM 0x00000701
#define CFG_OR7_PRELIM 0xFFC0007C
@@ -181,9 +231,8 @@
#define CFG_PACNT 0x00000000
#define CFG_PADDR 0x0000
#define CFG_PADAT 0x0000
-#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */
+#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */
#define CFG_PBDDR 0x0000
#define CFG_PBDAT 0x0000
#define CFG_PDCNT 0x00000000
-
-#endif /* _M5272C3_H */
+#endif /* _M5272C3_H */
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index cbb3e3bb9f9..3c17c1ea146 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -33,15 +33,17 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_MCF52x2 /* define processor family */
-#define CONFIG_M5282 /* define processor type */
+#define CONFIG_MCF52x2 /* define processor family */
+#define CONFIG_M5282 /* define processor type */
-#define FEC_ENET
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
+#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -50,24 +52,81 @@
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* CONFIG_MCFFEC */
+
+#define CONFIG_HOSTNAME M5272C3
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off ffe00000 ffe3ffff;" \
+ "era ffe00000 ffe3ffff;" \
+ "cp.b ${loadaddr} ffe00000 ${filesize};"\
+ "save\0" \
+ ""
#define CFG_PROMPT "-> "
-#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x20000
@@ -77,6 +136,10 @@
#define CFG_HZ 1000000
#define CFG_CLK 64000000
+/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
+
+#define CFG_MFD 0x02 /* PLL Multiplication Factor Devider */
+#define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */
/*
* Low Level Configuration Settings
@@ -85,15 +148,12 @@
*/
#define CFG_MBAR 0x40000000
-#undef CFG_DISCOVER_PHY
-#define CFG_ENET_BD_BASE 0x380000
-
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CFG_INIT_RAM_ADDR 0x20000000
-#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
-#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_RAM_ADDR 0x20000000
+#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -103,49 +163,88 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
+#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#define CFG_INT_FLASH_BASE 0xf0000000
+#define CFG_INT_FLASH_ENABLE 0x21
/* If M5282 port is fully implemented the monitor base will be behind
* the vector table. */
-/* #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) */
-#define CFG_MONITOR_BASE 0x20000
+#if (TEXT_BASE != CFG_INT_FLASH_BASE)
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#else
+#define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
+#endif
#define CFG_MONITOR_LEN 0x20000
#define CFG_MALLOC_LEN (256 << 10)
#define CFG_BOOTPARAMS_LEN 64*1024
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_SECT 35
-#define CFG_MAX_FLASH_BANKS 1
-#define CFG_FLASH_ERASE_TOUT 10000000
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+# define CFG_FLASH_CHECKSUM
+# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
-
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
-
-
+#define CFG_CS0_BASE CFG_FLASH_BASE
+#define CFG_CS0_SIZE 2*1024*1024
+#define CFG_CS0_WIDTH 16
+#define CFG_CS0_RO 0
+#define CFG_CS0_WS 6
+/*
+#define CFG_CS3_BASE 0xE0000000
+#define CFG_CS3_SIZE 1*1024*1024
+#define CFG_CS3_WIDTH 16
+#define CFG_CS3_RO 0
+#define CFG_CS3_WS 6
+*/
/*-----------------------------------------------------------------------
* Port configuration
*/
+#define CFG_PACNT 0x0000000 /* Port A D[31:24] */
+#define CFG_PADDR 0x0000000
+#define CFG_PADAT 0x0000000
+
+#define CFG_PBCNT 0x0000000 /* Port B D[23:16] */
+#define CFG_PBDDR 0x0000000
+#define CFG_PBDAT 0x0000000
+
+#define CFG_PCCNT 0x0000000 /* Port C D[15:08] */
+#define CFG_PCDDR 0x0000000
+#define CFG_PCDAT 0x0000000
+
+#define CFG_PDCNT 0x0000000 /* Port D D[07:00] */
+#define CFG_PCDDR 0x0000000
+#define CFG_PCDAT 0x0000000
+#define CFG_PEHLPAR 0xC0
+#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
+#define CFG_DDRUA 0x05
+#define CFG_PJPAR 0xFF;
-#endif /* _CONFIG_M5282EVB_H */
+#endif /* _CONFIG_M5282EVB_H */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
new file mode 100644
index 00000000000..d3b160505be
--- /dev/null
+++ b/include/configs/M5329EVB.h
@@ -0,0 +1,267 @@
+/*
+ * Configuation settings for the Freescale MCF5329 FireEngine board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5329EVB_H
+#define _M5329EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF532x /* define processor family */
+#define CONFIG_M5329 /* define processor type */
+
+#undef DEBUG
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#ifdef NANDFLASH_SIZE
+# define CONFIG_CMD_NAND
+#endif
+
+#define CFG_UNIFY_CACHE
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x58000
+#define CFG_IMMR CFG_MBAR
+
+#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* FEC_ENET */
+
+#define CONFIG_HOSTNAME M5329EVB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=40010000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off 0 2ffff;" \
+ "era 0 2ffff;" \
+ "cp.b ${loadaddr} 0 ${filesize};" \
+ "save\0" \
+ ""
+
+#define CONFIG_PRAM 512 /* 512 KB */
+#define CFG_PROMPT "-> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x40010000
+
+#define CFG_HZ 1000
+#define CFG_CLK 80000000
+#define CFG_CPU_CLK CFG_CLK * 3
+
+#define CFG_MBAR 0xFC000000
+
+#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x80000000
+#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL 0x221
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x40000000
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SDRAM_CFG1 0x53722730
+#define CFG_SDRAM_CFG2 0x56670000
+#define CFG_SDRAM_CTRL 0xE1092000
+#define CFG_SDRAM_EMOD 0x40010000
+#define CFG_SDRAM_MODE 0x018D0000
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+
+#define CFG_BOOTPARAMS_LEN 64*1024
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+#endif
+
+#ifdef NANDFLASH_SIZE
+# define CFG_MAX_NAND_DEVICE 1
+# define CFG_NAND_BASE (CFG_CS2_BASE << 16)
+# define CFG_NAND_SIZE 1
+# define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+# define NAND_MAX_CHIPS 1
+# define NAND_ALLOW_ERASE_ALL 1
+# define CONFIG_JFFS2_NAND 1
+# define CONFIG_JFFS2_DEV "nand0"
+# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1)
+# define CONFIG_JFFS2_PART_OFFSET 0x00000000
+#endif
+
+#define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_IS_EMBEDDED 1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - NAND Flash 16, 32, or 64MB
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CFG_CS0_BASE 0
+#define CFG_CS0_MASK 0x007f0001
+#define CFG_CS0_CTRL 0x00001fa0
+
+#define CFG_CS1_BASE 0x1000
+#define CFG_CS1_MASK 0x001f0001
+#define CFG_CS1_CTRL 0x002A3780
+
+#ifdef NANDFLASH_SIZE
+#define CFG_CS2_BASE 0x2000
+#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
+#define CFG_CS2_CTRL 0x00001f60
+#endif
+
+#endif /* _M5329EVB_H */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
new file mode 100644
index 00000000000..6f4859c2380
--- /dev/null
+++ b/include/configs/M54455EVB.h
@@ -0,0 +1,391 @@
+/*
+ * Configuation settings for the Freescale MCF54455 EVB board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _JAMICA54455_H
+#define _JAMICA54455_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF5445x /* define processor family */
+#define CONFIG_M54455 /* define processor type */
+#define CONFIG_M54455EVB /* M54455EVB board */
+
+#undef DEBUG
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+/* Network configuration */
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CONFIG_CF_DOMII
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC1_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+# define CONFIG_HAS_ETH1
+
+# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
+# define CONFIG_ETHPRIME "FEC0"
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+#define CONFIG_HOSTNAME M54455EVB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
+ "loadaddr=40010000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off 0 2ffff;" \
+ "era 0 2ffff;" \
+ "cp.b ${loadaddr} 0 ${filesize};" \
+ "save\0" \
+ ""
+
+/* ATA configuration */
+#define CONFIG_ISO_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_IDE_RESET 1
+#define CONFIG_IDE_PREINIT 1
+#define CONFIG_ATAPI
+#undef CONFIG_LBA48
+
+#define CFG_IDE_MAXBUS 1
+#define CFG_IDE_MAXDEVICE 2
+
+#define CFG_ATA_BASE_ADDR 0x90000000
+#define CFG_ATA_IDE0_OFFSET 0
+
+#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
+#define CFG_ATA_STRIDE 4 /* Interval between registers */
+#define _IO_BASE 0
+
+/* Realtime clock */
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CFG_RTC_OSCILLATOR (32 * CFG_HZ)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x58000
+#define CFG_IMMR CFG_MBAR
+
+/* PCI */
+#define CONFIG_PCI 1
+
+#define CFG_PCI_MEM_BUS 0xA0000000
+#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
+#define CFG_PCI_MEM_SIZE 0x10000000
+
+#define CFG_PCI_IO_BUS 0xB1000000
+#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS
+#define CFG_PCI_IO_SIZE 0x01000000
+
+#define CFG_PCI_CFG_BUS 0xB0000000
+#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
+#define CFG_PCI_CFG_SIZE 0x01000000
+
+/* FPGA - Spartan 2 */
+/* experiment
+#define CONFIG_FPGA CFG_SPARTAN3
+#define CONFIG_FPGA_COUNT 1
+#define CFG_FPGA_PROG_FEEDBACK
+#define CFG_FPGA_CHECK_CTRLC
+*/
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_PRAM 512 /* 512 KB */
+
+#define CFG_PROMPT "-> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000)
+
+#define CFG_HZ 1000
+
+#define CFG_MBAR 0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x80000000
+#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL 0x221
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x40000000
+#define CFG_SDRAM_BASE1 0x48000000
+#define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */
+#define CFG_SDRAM_CFG1 0x65311610
+#define CFG_SDRAM_CFG2 0x59670000
+#define CFG_SDRAM_CTRL 0xEA0B2000
+#define CFG_SDRAM_EMOD 0x40010000
+#define CFG_SDRAM_MODE 0x00010033
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#define CFG_BOOTPARAMS_LEN 64*1024
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OVERWRITE 1
+#undef CFG_ENV_IS_EMBEDDED
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CFG_ATMEL_BOOT
+# define CFG_FLASH_BASE 0
+# define CFG_FLASH0_BASE CFG_CS0_BASE
+# define CFG_FLASH1_BASE CFG_CS1_BASE
+#else
+# define CFG_FLASH_BASE CFG_FLASH0_BASE
+# define CFG_FLASH0_BASE CFG_CS1_BASE
+# define CFG_FLASH1_BASE CFG_CS0_BASE
+#endif
+
+/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
+/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
+ keep reset. */
+#undef CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+# define CFG_FLASH_CHECKSUM
+# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE }
+
+#else
+
+# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+
+# define CFG_ATMEL_REGION 4
+# define CFG_ATMEL_TOTALSECT 11
+# define CFG_ATMEL_SECT {1, 2, 1, 7}
+# define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
+# define CFG_INTEL_SECT 137
+
+/* max number of sectors on one chip */
+# define CFG_MAX_FLASH_SECT (CFG_ATMEL_TOTALSECT + CFG_INTEL_SECT)
+# define CFG_FLASH_ERASE_TOUT 2000 /* Atmel needs longer timeout */
+# define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+# define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
+# define CFG_FLASH_UNLOCK_TOUT 100 /* Timeout for Flash Clear Lock Bits (in ms) */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+# define CFG_FLASH_CHECKSUM
+
+#endif
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CFG_ATMEL_BOOT
+# define CONFIG_JFFS2_DEV "nor0"
+# define CONFIG_JFFS2_PART_SIZE 0x01000000
+# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE
+#else
+# define CONFIG_JFFS2_DEV "nor0"
+# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
+# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - CPLD
+ * CS3 - FPGA
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+#ifdef CFG_ATMEL_BOOT
+ /* Atmel Flash */
+#define CFG_CS0_BASE 0
+#define CFG_CS0_MASK 0x00070001
+#define CFG_CS0_CTRL 0x00001140
+/* Intel Flash */
+#define CFG_CS1_BASE 0x04000000
+#define CFG_CS1_MASK 0x01FF0001
+#define CFG_CS1_CTRL 0x003F3D60
+
+#define CFG_ATMEL_BASE CFG_CS0_BASE
+#else
+/* Intel Flash */
+#define CFG_CS0_BASE 0
+#define CFG_CS0_MASK 0x01FF0001
+#define CFG_CS0_CTRL 0x003F3D60
+ /* Atmel Flash */
+#define CFG_CS1_BASE 0x04000000
+#define CFG_CS1_MASK 0x00070001
+#define CFG_CS1_CTRL 0x00001140
+
+#define CFG_ATMEL_BASE CFG_CS1_BASE
+#endif
+
+/* CPLD */
+#define CFG_CS2_BASE 0x08000000
+#define CFG_CS2_MASK 0x00070001
+#define CFG_CS2_CTRL 0x003f1140
+
+/* FPGA */
+#define CFG_CS3_BASE 0x09000000
+#define CFG_CS3_MASK 0x00070001
+#define CFG_CS3_CTRL 0x00000020
+
+#endif /* _JAMICA54455_H */
diff --git a/include/configs/MBX.h b/include/configs/MBX.h
index d6e3fb8de9b..d9f2addb565 100644
--- a/include/configs/MBX.h
+++ b/include/configs/MBX.h
@@ -71,13 +71,27 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_COMMANDS ( CFG_CMD_NET | CONFIG_CMD_DFL | CFG_CMD_SDRAM | \
- CFG_CMD_PCMCIA | CFG_CMD_IDE )
-#define CONFIG_DOS_PARTITION
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_IDE
+
+
+#define CONFIG_DOS_PARTITION
/*
* Miscellaneous configurable options
@@ -88,7 +102,7 @@
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -187,7 +201,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/MBX860T.h b/include/configs/MBX860T.h
index 0ca0970075c..69d195dc028 100644
--- a/include/configs/MBX860T.h
+++ b/include/configs/MBX860T.h
@@ -151,7 +151,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h
index 465a4ecb8b9..8d7ec5926bc 100644
--- a/include/configs/METROBOX.h
+++ b/include/configs/METROBOX.h
@@ -104,6 +104,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_METROBOX 1 /* Board is Metrobox */
#define CONFIG_440GX 1 /* Specifc GX support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
@@ -241,26 +242,33 @@
#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
-/*-----------------------------------------------------------------------
- * Console/Commands/Parser
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_I2C | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_PING | \
- CFG_CMD_DIAG | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_ELF | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT)
-
-/* tbs 09-March-2005 Removed to be able to use 2nd serial */
-/* CFG_CMD_KGDB | \ */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
/* Include NetConsole support */
@@ -271,10 +279,6 @@
#define CONFIG_AUTO_COMPLETE 1
#define CFG_ALT_MEMTEST 1 /* use real memory test */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "MetroBox=> " /* Monitor Command Prompt */
@@ -285,7 +289,7 @@
/*-----------------------------------------------------------------------
* Console Buffer
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -331,7 +335,6 @@
#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
#define CFG_PCI_TARGET_INIT /* let board init pci target*/
#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
@@ -348,7 +351,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
#endif
@@ -360,7 +363,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
#endif
diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h
index 53684ca6b57..dde77427113 100644
--- a/include/configs/MHPC.h
+++ b/include/configs/MHPC.h
@@ -115,25 +115,36 @@
#define CONFIG_BR0_WORKAROUND 1
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_REGINFO )
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_REGINFO
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -225,7 +236,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 7e57a0fae14..5b526a0993f 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -50,41 +50,43 @@
***********************************************************/
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-/***********************************************************
- * Command definitions
- ***********************************************************/
-#define MIP405_COMMON_CMDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_CACHE | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_IRQ | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SAVES | \
- CFG_CMD_BSP )
-#if defined(CONFIG_MIP405T)
-#define CONFIG_COMMANDS \
- MIP405_COMMON_CMDS
-#else
-#define CONFIG_COMMANDS \
- (MIP405_COMMON_CMDS | \
- CFG_CMD_USB | \
- CFG_CMD_DOC )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_BSP
+
+#if !defined(CONFIG_MIP405T)
+ #define CONFIG_CMD_USB
+ #define CONFIG_CMD_DOC
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
@@ -165,7 +167,7 @@
**********************************************************/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -260,7 +262,7 @@
*/
#define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -426,7 +428,7 @@
/************************************************************
* Debug support
************************************************************/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/ML2.h b/include/configs/ML2.h
index d8805ea5a70..f488275f239 100644
--- a/include/configs/ML2.h
+++ b/include/configs/ML2.h
@@ -76,20 +76,31 @@
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & \
- ~( CFG_CMD_NET | \
- CFG_CMD_RTC | \
- CFG_CMD_PCI | \
- CFG_CMD_I2C \
- ) ) | \
- CFG_CMD_IRQ | \
- CFG_CMD_KGDB | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF | \
- CFG_CMD_JFFS2 )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_KGDB
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_JFFS2
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_RTC
+#undef CONFIG_CMD_PCI
+#undef CONFIG_CMD_I2C
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -102,7 +113,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -195,7 +206,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -236,7 +247,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h
index 6ad2feb28e7..9370c24c500 100644
--- a/include/configs/MOUSSE.h
+++ b/include/configs/MOUSSE.h
@@ -58,14 +58,31 @@
#endif
#define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138"
#define CONFIG_BOOTDELAY 3
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL|CFG_CMD_ASKENV|CFG_CMD_DATE)
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+
+
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ETH_ADDR "00:10:18:10:00:06"
#define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
+
#include "../board/mousse/mousse.h"
/*
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index 6195bca85ba..713518d0da2 100644
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -101,8 +101,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -198,59 +197,69 @@
#define CONFIG_BAUDRATE 115200
-#define CFG_EXCLUDE CFG_CMD_BEDBUG | \
- CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DISPLAY | \
- CFG_CMD_DOC | \
- CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FAT | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
- CFG_CMD_KGDB | \
- CFG_CMD_MMC | \
- CFG_CMD_NAND | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_REISER | \
- CFG_CMD_SCSI | \
- CFG_CMD_SPI | \
- CFG_CMD_SNTP | \
- CFG_CMD_UNIVERSE | \
- CFG_CMD_USB | \
- CFG_CMD_VFD | \
- CFG_CMD_XIMG
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_BSP
+#undef CONFIG_CMD_DATE
+#undef CONFIG_CMD_DISPLAY
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_MFSL
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_SNTP
+#undef CONFIG_CMD_UNIVERSE
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_XIMG
#if CONFIG_ADSTYPE == CFG_8272ADS
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_CMD_SDRAM | \
- CFG_CMD_I2C | \
- CFG_EXCLUDE ) )
+ #undef CONFIG_CMD_SDRAM
+ #undef CONFIG_CMD_I2C
+
#elif CONFIG_ADSTYPE >= CFG_PQ2FADS
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_CMD_SDRAM | \
- CFG_CMD_I2C | \
- CFG_CMD_PCI | \
- CFG_EXCLUDE ) )
+ #undef CONFIG_CMD_SDRAM
+ #undef CONFIG_CMD_I2C
+ #undef CONFIG_CMD_PCI
+
#else
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CMD_CFG_PCI | \
- CFG_EXCLUDE ) )
+ #undef CONFIG_CMD_PCI
+
#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/mtdblock2"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -268,7 +277,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -384,7 +393,7 @@
#endif /* CFG_RAMBOOT */
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -397,9 +406,9 @@
#define CFG_BCR 0x100C0000
#define CFG_SIUMCR 0x0A200000
#define CFG_SCCR SCCR_DFBRG01
-#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00001801
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801)
#define CFG_OR0_PRELIM 0xFF800876
-#define CFG_BR1_PRELIM CFG_BCSR | 0x00001801
+#define CFG_BR1_PRELIM (CFG_BCSR | 0x00001801)
#define CFG_OR1_PRELIM 0xFFFF8010
/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index 4953b7053be..14b041e3aec 100644
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -83,8 +83,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -141,40 +140,43 @@
*/
#define SPD_EEPROM_ADDRESS 0x50
-
#define CONFIG_8260_CLKIN 66000000 /* in Hz */
#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_COMMANDS ( CFG_CMD_ALL & ~( \
- CFG_CMD_BEDBUG | \
- CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DISPLAY | \
- CFG_CMD_DOC | \
- CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_KGDB | \
- CFG_CMD_MMC | \
- CFG_CMD_NAND | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_REISER | \
- CFG_CMD_SCSI | \
- CFG_CMD_SPI | \
- CFG_CMD_SNTP | \
- CFG_CMD_VFD | \
- CFG_CMD_UNIVERSE | \
- CFG_CMD_USB | \
- CFG_CMD_XIMG ) )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_BSP
+#undef CONFIG_CMD_DATE
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DISPLAY
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_MFSL
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_SNTP
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_UNIVERSE
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_XIMG
/* Define a command string that is automatically executed when no character
* is read on the console interface withing "Boot Delay" after reset.
@@ -202,21 +204,19 @@
"bootm"
#endif /* CONFIG_BOOT_ROOT_NFS */
-/* Add support for a few extra bootp options like:
- * - File size
- * - DNS
+/*
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE | \
- CONFIG_BOOTP_DNS)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -231,7 +231,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -283,7 +283,6 @@
#define SDRAM_SPD_ADDR 0x50
-
/*-----------------------------------------------------------------------
* BR2,BR3 - Base Register
* Ref: Section 10.3.1 on page 10-14
@@ -381,7 +380,6 @@
#error "INVALID SDRAM CONFIGURATION"
#endif
-
#define RS232EN_1 0x02000002
#define RS232EN_2 0x01000001
#define FETHIEN 0x08000008
@@ -393,7 +391,6 @@
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */
/* 0x0EB2B645 */
#define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\
@@ -450,13 +447,11 @@
# define CFG_ENV_SIZE 0x200
#endif /* CFG_RAMBOOT */
-
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-
/*-----------------------------------------------------------------------
* HIDx - Hardware Implementation-dependent Registers 2-11
*-----------------------------------------------------------------------
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
new file mode 100644
index 00000000000..6568fe13b85
--- /dev/null
+++ b/include/configs/MPC8313ERDB.h
@@ -0,0 +1,569 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * mpc8313epb board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1
+#define CONFIG_MPC83XX 1
+#define CONFIG_MPC831X 1
+#define CONFIG_MPC8313 1
+#define CONFIG_MPC8313ERDB 1
+
+#define CONFIG_PCI
+#define CONFIG_83XX_GENERIC_PCI
+
+#ifdef CFG_66MHZ
+#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
+#elif defined(CFG_33MHZ)
+#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
+#else
+#error Unknown oscillator frequency.
+#endif
+
+#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+
+#define CFG_IMMR 0xE0000000
+
+#define CFG_MEMTEST_START 0x00001000
+#define CFG_MEMTEST_END 0x07f00000
+
+/* Early revs of this board will lock up hard when attempting
+ * to access the PMC registers, unless a JTAG debugger is
+ * connected, or some resistor modifications are made.
+ */
+#define CFG_8313ERDB_BROKEN_PMC 1
+
+#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
+#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * seem to have the SPD connected to I2C.
+ */
+#define CFG_DDR_SIZE 128 /* MB */
+#define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \
+ | 0x00040000 /* TODO */ \
+ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
+ /* 0x80840102 */
+
+#define CFG_DDR_TIMING_3 0x00000000
+#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+ | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
+ | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
+ | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
+ | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
+ | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
+ | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
+ | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+ /* 0x00220802 */
+#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
+ | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+ | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
+ | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
+ | (13 << TIMING_CFG1_REFREC_SHIFT ) \
+ | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
+ | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
+ | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+ /* 0x3935d322 */
+#define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+ | (31 << TIMING_CFG2_CPO_SHIFT ) \
+ | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
+ | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
+ | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
+ | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
+ | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+ /* 0x0f9048ca */ /* P9-45,may need tuning */
+#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+ | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+ /* 0x03200064 */
+#if defined(CONFIG_DDR_2T_TIMING)
+#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_2T_EN \
+ | SDRAM_CFG_DBW_32 )
+#else
+#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_32_BE )
+ /* 0x43080000 */
+#endif
+#define CFG_SDRAM_CFG2 0x00401000;
+/* set burst length to 8 for 32-bit data path */
+#define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
+ | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
+ /* 0x44400232 */
+#define CFG_DDR_MODE_2 0x8000C000;
+
+#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+ /*0x02000000*/
+#define CFG_DDRCDR_VALUE ( DDRCDR_EN \
+ | DDRCDR_PZ_NOMZ \
+ | DDRCDR_NZ_NOMZ \
+ | DDRCDR_M_ODR )
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI /* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
+#define CFG_FLASH_SIZE 8 /* flash size in MB */
+#define CFG_FLASH_EMPTY_INFO /* display empty sectors */
+#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
+
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \
+ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+ BR_V) /* valid */
+#define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_9 \
+ | OR_GPCM_EHTR \
+ | OR_GPCM_EAD )
+ /* 0xFF006FF7 TODO SLOW 16 MB flash size */
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
+#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 135 /* sectors per device */
+
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */
+#define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \
+ | (0xFF << LBCR_BMT_SHIFT) \
+ | 0xF ) /* 0x0004ff0f */
+
+#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */
+
+/* drivers/nand/nand.c */
+#define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */
+#define CFG_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CFG_BR1_PRELIM ( CFG_NAND_BASE \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V ) /* valid */
+#define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR )
+ /* 0xFFFF8396 */
+#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
+#define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
+
+#define CFG_VSC7385_BASE 0xF0000000
+
+#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
+#define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
+#define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
+#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */
+#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */
+
+/* local bus read write buffer mapping */
+#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */
+#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */
+#define CFG_LBLAWBAR3_PRELIM 0xFA000000
+#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,8313@0"
+#define OF_SOC "soc8313@e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500"
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
+#define CFG_I2C2_OFFSET 0x3100
+
+/* TSEC */
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
+#define CONFIG_NET_MULTI
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_MMIO_BASE 0x90000000
+#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xE2000000
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET /* TSEC ethernet support */
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_GMII 1 /* MII PHY management */
+#define CONFIG_TSEC1 1
+
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define TSEC1_PHY_ADDR 0x1c
+#define TSEC2_PHY_ADDR 4
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC1"
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CFG_I2C_RTC_ADDR 0x68
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
+ #define CFG_ENV_SIZE 0x2000
+
+/* Address and size of Redundant Environment Sector */
+#else
+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+ #define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PCI
+
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMDLINE_EDITING 1
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 16384
+#define CFG_CACHELINE_SIZE 32
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+
+#ifdef CFG_66MHZ
+
+/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
+/* 0x62040000 */
+#define CFG_HRCW_LOW (\
+ 0x20000000 /* reserved, must be set */ |\
+ HRCWL_DDRCM |\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_2X1 |\
+ HRCWL_CSB_TO_CLKIN_2X1 |\
+ HRCWL_CORE_TO_CSB_2X1)
+
+#elif defined(CFG_33MHZ)
+
+/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
+/* 0x65040000 */
+#define CFG_HRCW_LOW (\
+ 0x20000000 /* reserved, must be set */ |\
+ HRCWL_DDRCM |\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_2X1 |\
+ HRCWL_CSB_TO_CLKIN_5X1 |\
+ HRCWL_CORE_TO_CSB_2X1)
+
+#endif
+
+/* 0xa0606c00 */
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_RL_EXT_LEGACY |\
+ HRCWH_TSEC1M_IN_RGMII |\
+ HRCWH_TSEC2M_IN_RGMII |\
+ HRCWH_BIG_ENDIAN |\
+ HRCWH_LALE_NORMAL)
+
+/* System IO Config */
+#define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
+#define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */
+
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+
+#define CFG_HID2 HID2_HBE
+
+/* DDR @ 0x00000000 */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10)
+#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI2 not supported on 8313 */
+#define CFG_IBAT3L (0)
+#define CFG_IBAT3U (0)
+#define CFG_IBAT4L (0)
+#define CFG_IBAT4U (0)
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CFG_IBAT6L (0xF0000000 | BATL_PP_10)
+#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT7L (0)
+#define CFG_IBAT7U (0)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+#define CFG_DBAT4L CFG_IBAT4L
+#define CFG_DBAT4U CFG_IBAT4U
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ETHADDR 00:E0:0C:00:95:01
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02
+
+#define CONFIG_IPADDR 10.0.0.2
+#define CONFIG_SERVERIP 10.0.0.1
+#define CONFIG_GATEWAYIP 10.0.0.1
+#define CONFIG_NETMASK 255.0.0.0
+#define CONFIG_NETDEV eth1
+
+#define CONFIG_HOSTNAME mpc8313erdb
+#define CONFIG_ROOTPATH /nfs/root/path
+#define CONFIG_BOOTFILE uImage
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
+#define CONFIG_FDTFILE mpc8313erdb.dtb
+
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
+#define CONFIG_BAUDRATE 115200
+
+#define XMK_STR(x) #x
+#define MK_STR(x) XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
+ "ethprime=TSEC1\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
+ "console=ttyS0\0" \
+ "setbootargs=setenv bootargs " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+ "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv rootdev /dev/nfs;" \
+ "run setbootargs;" \
+ "run setipargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv rootdev /dev/ram;" \
+ "run setbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#undef MK_STR
+#undef XMK_STR
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
new file mode 100644
index 00000000000..376973b94da
--- /dev/null
+++ b/include/configs/MPC8323ERDB.h
@@ -0,0 +1,583 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 family */
+#define CONFIG_QE 1 /* Has QE */
+#define CONFIG_MPC83XX 1 /* MPC83xx family */
+#define CONFIG_MPC832X 1 /* MPC832x CPU specific */
+
+#define CONFIG_PCI 1
+#define CONFIG_83XX_GENERIC_PCI 1
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
+#endif
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_2X1 |\
+ HRCWL_VCO_1X2 |\
+ HRCWL_CSB_TO_CLKIN_2X1 |\
+ HRCWL_CORE_TO_CSB_2_5X1 |\
+ HRCWL_CE_PLL_VCO_DIV_2 |\
+ HRCWL_CE_PLL_DIV_1X1 |\
+ HRCWL_CE_TO_PLL_1X3)
+
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_BIG_ENDIAN |\
+ HRCWH_LALE_NORMAL)
+
+/*
+ * System IO Config
+ */
+#define CFG_SICRL 0x00000000
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+
+/*
+ * IMMR new address
+ */
+#define CFG_IMMR 0xE0000000
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
+
+#undef CONFIG_SPD_EEPROM
+#if defined(CONFIG_SPD_EEPROM)
+/* Determine DDR configuration from I2C interface
+ */
+#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
+#else
+/* Manually set up DDR parameters
+ */
+#define CFG_DDR_SIZE 64 /* MB */
+#define CFG_DDR_CS0_CONFIG 0x80840101
+#define CFG_DDR_TIMING_0 0x00220802
+#define CFG_DDR_TIMING_1 0x3935d322
+#define CFG_DDR_TIMING_2 0x0f9048ca
+#define CFG_DDR_TIMING_3 0x00000000
+#define CFG_DDR_CLK_CNTL 0x02000000
+#define CFG_DDR_MODE 0x44400232
+#define CFG_DDR_MODE2 0x8000c000
+#define CFG_DDR_INTERVAL 0x03200064
+#define CFG_DDR_CS0_BNDS 0x00000003
+#define CFG_DDR_SDRAM_CFG 0x43080000
+#define CFG_DDR_SDRAM_CFG2 0x00401000
+#endif
+
+/*
+ * Memory test
+ */
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00030000 /* memtest region */
+#define CFG_MEMTEST_END 0x03f00000
+
+/*
+ * The reserved memory
+ */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
+#define CFG_LBC_LBCR 0x00000000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI /* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
+
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
+#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
+
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
+ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+ BR_V) /* valid */
+#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+
+/*
+ * SDRAM on the Local Bus
+ */
+#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */
+
+#ifdef CFG_LB_SDRAM
+#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+
+#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE
+#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
+
+/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ * port size = 32-bits = BR2[19:20] = 11
+ * no parity checking = BR2[21:22] = 00
+ * SDRAM for MSEL = BR2[24:26] = 011
+ * Valid = BR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ * 64MB mask for AM, OR2[0:7] = 1111 1100
+ * XAM, OR2[17:18] = 11
+ * 9 columns OR2[19-21] = 010
+ * 13 rows OR2[23-25] = 100
+ * EAD set for extra time OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM 0xfc006901
+
+#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON 0x0063b723
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_NORMAL)
+
+#endif
+
+/*
+ * Windows to access PIB via local bus
+ */
+#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
+#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,8323@0"
+#define OF_SOC "soc8323@e0000000"
+#define OF_QE "qe@e0100000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500"
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_MMIO_BASE 0x90000000
+#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_IO_BASE 0xd0000000
+#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE 0x04000000 /* 64M */
+
+#ifdef CONFIG_PCI
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+
+#endif /* CONFIG_PCI */
+
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME "Freescale GETH"
+
+#define CONFIG_UEC_ETH1 /* ETH3 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CFG_UEC1_UCC_NUM 2 /* UCC3 */
+#define CFG_UEC1_RX_CLK QE_CLK9
+#define CFG_UEC1_TX_CLK QE_CLK10
+#define CFG_UEC1_ETH_TYPE FAST_ETH
+#define CFG_UEC1_PHY_ADDR 4
+#define CFG_UEC1_INTERFACE_MODE ENET_100_MII
+#endif
+
+#define CONFIG_UEC_ETH2 /* ETH4 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
+#define CFG_UEC2_RX_CLK QE_CLK16
+#define CFG_UEC2_TX_CLK QE_CLK3
+#define CFG_UEC2_ETH_TYPE FAST_ETH
+#define CFG_UEC2_PHY_ADDR 0
+#define CFG_UEC2_INTERFACE_MODE ENET_100_MII
+#endif
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+ #define CFG_ENV_SIZE 0x2000
+#else
+ #define CFG_NO_FLASH 1 /* Flash is not usable now */
+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+ #define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ASKENV
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
+#endif
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CFG_HID2 HID2_HBE
+
+/*
+ * Cache Config
+ */
+#define CFG_DCACHE_SIZE 16384
+#define CFG_CACHELINE_SIZE 32
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
+#endif
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+
+/* IMMRBAR & PCI IO: cache-inhibit and guarded */
+#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CFG_IBAT2L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT2U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_DBAT2L (CFG_FLASH_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U CFG_IBAT2U
+
+#define CFG_IBAT3L (0)
+#define CFG_IBAT3U (0)
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10)
+#define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT4L CFG_IBAT4L
+#define CFG_DBAT4U CFG_IBAT4U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CFG_IBAT5L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT5U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CFG_IBAT6L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT6U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#else
+#define CFG_IBAT5L (0)
+#define CFG_IBAT5U (0)
+#define CFG_IBAT6L (0)
+#define CFG_IBAT6U (0)
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#endif
+
+/* Nothing in BAT7 */
+#define CFG_IBAT7L (0)
+#define CFG_IBAT7U (0)
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ETHADDR 00:04:9f:ef:03:01
+#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
+#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02
+
+#define CONFIG_IPADDR 10.0.0.2
+#define CONFIG_SERVERIP 10.0.0.1
+#define CONFIG_GATEWAYIP 10.0.0.1
+#define CONFIG_NETMASK 255.0.0.0
+#define CONFIG_NETDEV eth1
+
+#define CONFIG_HOSTNAME mpc8323erdb
+#define CONFIG_ROOTPATH /nfsroot
+#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
+#define CONFIG_BOOTFILE uImage
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
+#define CONFIG_FDTFILE mpc832x_rdb.dtb
+
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
+#define CONFIG_BAUDRATE 115200
+
+#define XMK_STR(x) #x
+#define MK_STR(x) XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftp $loadaddr $uboot;" \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
+ "ramdiskaddr=1000000\0" \
+ "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
+ "console=ttyS0\0" \
+ "setbootargs=setenv bootargs " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+ "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv rootdev /dev/nfs;" \
+ "run setbootargs;" \
+ "run setipargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv rootdev /dev/ram;" \
+ "run setbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#undef MK_STR
+#undef XMK_STR
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index cecb2258ffe..c9c6d88cf01 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -30,6 +30,8 @@
#define CONFIG_MPC83XX 1 /* MPC83xx family */
#define CONFIG_MPC832X 1 /* MPC832x CPU specific */
#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
+#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
+#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
/*
* System Clock Setup
@@ -87,6 +89,7 @@
#define CFG_SICRL 0x00000000
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
/*
* IMMR new address
@@ -315,12 +318,9 @@
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8323@0"
#define OF_SOC "soc8323@e0000000"
#define OF_QE "qe@e0100000"
@@ -423,41 +423,33 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#if defined(CFG_RAMBOOT)
-#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#endif
-#else
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ASKENV
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C )
+ #define CONFIG_CMD_PCI
#endif
+
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -468,7 +460,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -498,7 +490,7 @@
*/
#define CFG_DCACHE_SIZE 16384
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
#endif
@@ -575,7 +567,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 0460be9e569..92555bac422 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -339,12 +339,9 @@
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8349@0"
#define OF_SOC "soc8349@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
@@ -432,14 +429,16 @@
#endif
#define CONFIG_GMII 1 /* MII PHY management */
-#define CONFIG_MPC83XX_TSEC1 1
-#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC83XX_TSEC2 1
-#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
@@ -475,44 +474,35 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#if defined(CFG_RAMBOOT)
-#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C \
- | CFG_CMD_DATE) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_DATE) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#endif
-#else
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_DATE \
- )
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII \
- | CFG_CMD_DATE \
- )
+ #define CONFIG_CMD_PCI
#endif
+
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -523,7 +513,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -544,7 +534,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -695,7 +685,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -708,6 +698,7 @@
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_ETHADDR 00:04:9f:ef:23:33
#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH0
#define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21
#endif
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 37bbfb336d2..54cab528bde 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -154,6 +154,9 @@
#define CFG_MEMTEST_START 0x1000 /* memtest region */
#define CFG_MEMTEST_END 0x2000
+#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
#ifdef CONFIG_HARD_I2C
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
#endif
@@ -286,18 +289,16 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_CONSOLE ttyS0
#define CONFIG_BAUDRATE 115200
#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500)
#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600)
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8349@0"
#define OF_SOC "soc8349@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
@@ -369,24 +370,27 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_NET_MULTI
#define CONFIG_MII
-#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */
+#define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */
-#define CONFIG_MPC83XX_TSEC1
+#define CONFIG_TSEC1
-#ifdef CONFIG_MPC83XX_TSEC1
-#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME "TSEC0"
#define CFG_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
#define TSEC1_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
#endif
-#ifdef CONFIG_MPC83XX_TSEC2
+#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
-#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC2_NAME "TSEC1"
#define CFG_TSEC2_OFFSET 0x25000
#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
#define TSEC2_PHY_ADDR 4
#define TSEC2_PHYIDX 0
+#define TSEC2_FLAGS TSEC_GIGABIT
#endif
#define CONFIG_ETHPRIME "Freescale TSEC"
@@ -405,6 +409,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH /* Flash is not usable now */
+ #undef CFG_FLASH_CFI_DRIVER
#define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
@@ -413,40 +418,41 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
-/* CONFIG_COMMANDS */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
#ifdef CONFIG_COMPACT_FLASH
-#define CONFIG_COMMANDS_CF (CFG_CMD_IDE | CFG_CMD_FAT)
-#else
-#define CONFIG_COMMANDS_CF 0
+ #define CONFIG_CMD_IDE
+ #define CONFIG_CMD_FAT
#endif
#ifdef CONFIG_PCI
-#define CONFIG_COMMANDS_PCI CFG_CMD_PCI
-#else
-#define CONFIG_COMMANDS_PCI 0
+ #define CONFIG_CMD_PCI
#endif
#ifdef CONFIG_HARD_I2C
-#define CONFIG_COMMANDS_I2C CFG_CMD_I2C
-#else
-#define CONFIG_COMMANDS_I2C 0
+ #define CONFIG_CMD_I2C
#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CONFIG_COMMANDS_CF | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CONFIG_COMMANDS_I2C | \
- CONFIG_COMMANDS_PCI | \
- CFG_CMD_SDRAM | \
- CFG_CMD_DATE | \
- CFG_CMD_CACHE | \
- CFG_CMD_IRQ)
-#include <cmd_confdefs.h>
-
/* Watchdog */
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
@@ -466,7 +472,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -489,7 +495,7 @@ boards, we say we have two, but don't display a message if we find only one. */
*/
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */
#endif
@@ -614,7 +620,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -625,11 +631,11 @@ boards, we say we have two, but don't display a message if we find only one. */
*/
#define CONFIG_ENV_OVERWRITE
-#ifdef CONFIG_MPC83XX_TSEC1
+#ifdef CONFIG_TSEC1
#define CONFIG_ETHADDR 00:E0:0C:00:8C:01
#endif
-#ifdef CONFIG_MPC83XX_TSEC2
+#ifdef CONFIG_TSEC2
#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
#endif
@@ -667,9 +673,10 @@ boards, we say we have two, but don't display a message if we find only one. */
" ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
- " console=ttyS0," MK_STR(CONFIG_BAUDRATE)
+ " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=" MK_STR(CONFIG_CONSOLE) "\0" \
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 79937dcd8f9..41f062ce72e 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -32,6 +32,8 @@
#define CONFIG_MPC83XX 1 /* MPC83XX family */
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
+#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
+#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
/*
* System Clock Setup
@@ -88,6 +90,7 @@
#define CFG_SICRL 0x40000000
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
/*
* IMMR new address
@@ -309,13 +312,13 @@
/*
* CS4 on Local Bus, to PIB
*/
-#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */
+#define CFG_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */
#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
* CS5 on Local Bus, to PIB
*/
-#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */
+#define CFG_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */
#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
@@ -348,10 +351,6 @@
#define CONFIG_OF_HAS_BD_T 1
#define CONFIG_OF_HAS_UBOOT_ENV 1
-
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8360@0"
#define OF_SOC "soc8360@e0000000"
#define OF_QE "qe@e0100000"
@@ -457,41 +456,33 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#if defined(CFG_RAMBOOT)
-#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#endif
-#else
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ASKENV
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C )
+ #define CONFIG_CMD_PCI
#endif
+
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -502,7 +493,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -532,7 +523,7 @@
*/
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
#endif
@@ -610,7 +601,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 5aeea586800..be603ac117b 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -301,9 +301,6 @@
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8540@0"
#define OF_SOC "soc8540@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -366,14 +363,16 @@
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#if CONFIG_HAS_FEC
@@ -381,6 +380,7 @@
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
+#define FEC_FLAGS 0
#endif
/* Options are: TSEC[0-1], FEC */
@@ -407,37 +407,33 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
#if defined(CFG_RAMBOOT)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #else
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #else
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #endif
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -448,7 +444,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -469,7 +465,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -481,7 +477,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -493,6 +489,7 @@
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
@@ -520,7 +517,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
- "ramdiskaddr=600000\0" \
+ "ramdiskaddr=1000000\0" \
"ramdiskfile=your.ramdisk.u-boot\0" \
"fdtaddr=400000\0" \
"fdtfile=your.fdt.dtb\0"
@@ -540,7 +537,7 @@
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr"
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 418a3a38e68..e376c11656b 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -212,11 +212,14 @@
#elif defined(CONFIG_TSEC_ENET)
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC1 1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_MPC85XX_FEC 1
+#define CONFIG_HAS_ETH2
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define TSEC1_PHY_ADDR 7
#define TSEC2_PHY_ADDR 4
@@ -224,6 +227,10 @@
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define FEC_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define FEC_FLAGS 0
+
/* Options are: TSEC[0-1], FEC */
#define CONFIG_ETHPRIME "TSEC0"
@@ -259,26 +266,33 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
-#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \
- | CFG_CMD_PCI | CFG_CMD_I2C ) & \
- ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
-#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \
- | CFG_CMD_I2C ) & \
- ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
-#endif
-#else
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \
- | CFG_CMD_PING | CFG_CMD_I2C )
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C )
+ #define CONFIG_CMD_PCI
#endif
+
+#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -288,7 +302,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -308,7 +322,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -320,7 +334,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index fb360d282cd..4e061bd9ff2 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -312,9 +312,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8541@0"
#define OF_SOC "soc8541@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -350,6 +347,13 @@ extern unsigned long get_clock_freq(void);
#define CFG_PCI2_IO_PHYS 0xe2100000
#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
#if defined(CONFIG_PCI)
@@ -373,17 +377,16 @@ extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPC85XX_FEC
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
-#define FEC_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
-#define FEC_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
@@ -401,19 +404,28 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
+ #define CONFIG_CMD_PCI
#endif
-#include <cmd_confdefs.h>
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -423,7 +435,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -443,7 +455,7 @@ extern unsigned long get_clock_freq(void);
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -455,7 +467,7 @@ extern unsigned long get_clock_freq(void);
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -466,6 +478,7 @@ extern unsigned long get_clock_freq(void);
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 4c3430897da..f580ccadee5 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -34,14 +34,14 @@
#define CONFIG_MPC8544 1
#define CONFIG_MPC8544DS 1
-#undef CONFIG_PCI /* Enable PCI/PCIE */
-#undef CONFIG_PCI1 /* PCI controller 1 */
-#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
-#undef CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
-#undef CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
-#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCI1 1 /* PCI controller 1 */
+#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_DLL
@@ -52,6 +52,7 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_DDR_ECC_CMD
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
/*
* When initializing flash, if we cannot find the manufacturer ID,
@@ -70,7 +71,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
@@ -86,13 +87,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000
#define CFG_ALT_MEMTEST
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -180,6 +181,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */
#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
+#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
@@ -251,9 +253,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8544@0"
#define OF_SOC "soc8544@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -281,7 +280,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe1000000
-#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */
/* PCI view of System Memory */
#define CFG_PCI_MEMORY_BUS 0x00000000
@@ -293,27 +292,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE
#define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCIE2_IO_BASE 0x00000000
-#define CFG_PCIE2_IO_PHYS 0xe2000000
-#define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCIE2_IO_PHYS 0xe1010000
+#define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 2,tgtid 2, Base address a000 */
#define CFG_PCIE1_MEM_BASE 0xa0000000
#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
-#define CFG_PCIE1_MEM_SIZE 0x08000000 /* 128M */
-#define CFG_PCIE1_MEM_BASE2 0xa8000000
-#define CFG_PCIE1_MEM_PHYS2 CFG_PCIE1_MEM_BASE2
-#define CFG_PCIE1_MEM_SIZE2 0x04000000 /* 64M */
-#define CFG_PCIE1_IO_BASE 0x00000000 /* reuse mem LAW */
-#define CFG_PCIE1_IO_PHYS 0xaf000000
-#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCIE1_IO_BASE 0x00000000
+#define CFG_PCIE1_IO_PHYS 0xe1020000
+#define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 3, direct to uli, tgtid 3, Base address b000 */
#define CFG_PCIE3_MEM_BASE 0xb0000000
#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE
-#define CFG_PCIE3_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */
#define CFG_PCIE3_IO_BASE 0x00000000
-#define CFG_PCIE3_IO_PHYS 0xe3000000
+#define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
#define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCIE3_MEM_BASE2 0xb0200000
+#define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2
+#define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
#if defined(CONFIG_PCI)
@@ -344,7 +343,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SATA_ULI5288
#define CFG_SCSI_MAX_SCSI_ID 4
#define CFG_SCSI_MAX_LUN 1
-#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
#endif /* SCSCI */
@@ -354,27 +353,28 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC1"
-#define CONFIG_MPC85XX_TSEC3 1
-#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC3"
-#undef CONFIG_MPC85XX_FEC
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
#define TSEC1_PHY_ADDR 0
#define TSEC3_PHY_ADDR 1
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
#define TSEC1_PHYIDX 0
#define TSEC3_PHYIDX 0
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
#endif /* CONFIG_TSEC_ENET */
/*
@@ -392,21 +392,32 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII \
- | CFG_CMD_BEDBUG \
- | CFG_CMD_NET)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
+ #define CONFIG_CMD_PCI
+ #define CONFIG_CMD_BEDBUG
+ #define CONFIG_CMD_NET
+ #define CONFIG_CMD_SCSI
+ #define CONFIG_CMD_EXT2
#endif
-#include <cmd_confdefs.h>
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -416,7 +427,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -431,12 +442,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
+#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -448,7 +459,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -459,6 +470,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
@@ -472,7 +484,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_HOSTNAME 8544ds_unknown
#define CONFIG_ROOTPATH /nfs/mpc85xx
-#define CONFIG_BOOTFILE 8544ds_tmt/uImage.uboot
+#define CONFIG_BOOTFILE 8544ds/uImage.uboot
+#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
#define CONFIG_SERVERIP 192.168.0.1
#define CONFIG_GATEWAYIP 192.168.0.1
@@ -481,7 +494,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CONFIG_BAUDRATE 115200
@@ -489,10 +502,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define PCIE_ENV \
"pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
- "pcie1regs=setenv a e000a; run pciereg\0" \
- "pcie2regs=setenv a e0009; run pciereg\0" \
- "pcie3regs=setenv a e000b; run pciereg\0" \
- "pcieerr=md ${a}020 1; md ${a}e00;" \
+ "pcieerr=md ${a}020 1; md ${a}e00 e;" \
"pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1;" \
"pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \
@@ -501,12 +511,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
"pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \
"pci w $b.0 130 ffffffff\0" \
"pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
- "pcie1err=setenv a e000a; run pcieerr\0" \
- "pcie2err=setenv a e0009; run pcieerr\0" \
- "pcie3err=setenv a e000b; run pcieerr\0" \
- "pcie1errc=setenv a e000a; run pcieerrc\0" \
- "pcie2errc=setenv a e0009; run pcieerrc\0" \
- "pcie3errc=setenv a e000b; run pcieerrc\0"
+ "pcie1regs=setenv a e000a; run pciereg\0" \
+ "pcie2regs=setenv a e0009; run pciereg\0" \
+ "pcie3regs=setenv a e000b; run pciereg\0" \
+ "pcie1cfg=setenv b 3; run pciecfg\0" \
+ "pcie2cfg=setenv b 5; run pciecfg\0" \
+ "pcie3cfg=setenv b 0; run pciecfg\0" \
+ "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
+ "pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \
+ "pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \
+ "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \
+ "pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \
+ "pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0"
#else
#define PCIE_ENV ""
#endif
@@ -514,14 +530,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#if defined(CONFIG_PCI1)
#define PCI_ENV \
"pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
- "echo e;md ${a}e00 9\0" \
+ "echo e;md ${a}e00 9\0" \
"pci1regs=setenv a e0008; run pcireg\0" \
"pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1\0" \
- "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
- "pci w.w $b.0 56 ffff\0" \
- "pci1err=setenv a e0008; run pcierr\0" \
- "pci1errc=setenv a e0008; run pcierrc\0"
+ "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
+ "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \
+ "pci1err=setenv a e0008; setenv b 7; run pcierr\0" \
+ "pci1errc=setenv a e0008; setenv b 7; run pcierrc\0"
#else
#define PCI_ENV ""
#endif
@@ -541,25 +557,39 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define ENET_ENV ""
#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
- "ramdiskfile=8544ds_tmt/ramdisk.uboot\0" \
- "fdtaddr=400000\0" \
- "fdtfile=8544ds_tmt/mpc8544ds.dtb\0" \
- "eoi=mw e00400b0 0\0" \
- "iack=md e00400a0 1\0" \
+ "ramdiskfile=8544ds/ramdisk.uboot\0" \
+ "dtbaddr=c00000\0" \
+ "dtbfile=8544ds/mpc8544ds.dtb\0" \
+ "bdev=sda3\0" \
+ "eoi=mw e00400b0 0\0" \
+ "iack=md e00400a0 1\0" \
"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
"md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
- "ddrregs=setenv a e0002; run ddrreg\0" \
+ "ddrregs=setenv a e0002; run ddrreg\0" \
"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
- "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
- "guregs=setenv a e00e0; run gureg\0" \
+ "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
+ "guregs=setenv a e00e0; run gureg\0" \
"ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
- "ecmregs=setenv a e0001; run ecmreg\0" \
- PCIE_ENV \
- PCI_ENV \
+ "ecmregs=setenv a e0001; run ecmreg\0" \
+ "lawregs=md e0000c08 4b\0" \
+ "lbcregs=md e0005000 36\0" \
+ "dma0regs=md e0021100 12\0" \
+ "dma1regs=md e0021180 12\0" \
+ "dma2regs=md e0021200 12\0" \
+ "dma3regs=md e0021280 12\0" \
+ PCIE_ENV \
+ PCI_ENV \
ENET_ENV
@@ -569,23 +599,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr $ramdiskaddr $dtbaddr"
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/sda3 rw " \
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 680009d6006..60837151893 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -11,7 +11,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -36,8 +36,14 @@
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
-#define CONFIG_PCI
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_PCI /* enable any pci type devices */
+#define CONFIG_PCI1 /* PCI controller 1 */
+#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#undef CONFIG_RIO
+#undef CONFIG_PCI2
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
@@ -46,6 +52,7 @@
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
/*
@@ -65,16 +72,16 @@ extern unsigned long get_clock_freq(void);
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
-
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
@@ -85,10 +92,14 @@ extern unsigned long get_clock_freq(void);
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
+#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
+
/*
* DDR Setup
*/
@@ -106,7 +117,6 @@ extern unsigned long get_clock_freq(void);
#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Local Bus Definitions
*/
@@ -124,9 +134,9 @@ extern unsigned long get_clock_freq(void);
* Use GPCM = BRx[24:26] = 000
* Valid = BRx[31] = 1
*
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
- * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
*
* OR0, OR1:
* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
@@ -137,11 +147,12 @@ extern unsigned long get_clock_freq(void);
* TRLX = use relaxed timing = ORx[29] = 1
* EAD = use external address latch delay = OR[31] = 1
*
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
*/
-#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */
+#define CFG_BOOT_BLOCK 0xff000000 /* boot TLB block */
+#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */
#define CFG_BR0_PRELIM 0xff801001
#define CFG_BR1_PRELIM 0xff001001
@@ -156,7 +167,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
@@ -166,7 +177,12 @@ extern unsigned long get_clock_freq(void);
/*
* SDRAM on the Local Bus
*/
-#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
+#define CFG_LBC_CACHE_SIZE 64
+#define CFG_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */
+#define CFG_LBC_NONCACHE_SIZE 64
+
+#define CFG_LBC_SDRAM_BASE CFG_LBC_CACHE_BASE /* Localbus SDRAM */
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
@@ -180,14 +196,14 @@ extern unsigned long get_clock_freq(void);
* SDRAM for MSEL = BR2[24:26] = 011
* Valid = BR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
*
* FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
* FIXME: the top 17 bits of BR2.
*/
-#define CFG_BR2_PRELIM 0xf0001861
+#define CFG_BR2_PRELIM 0xf0001861
/*
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
@@ -196,19 +212,19 @@ extern unsigned long get_clock_freq(void);
* 64MB mask for AM, OR2[0:7] = 1111 1100
* XAM, OR2[17:18] = 11
* 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
+ * 13 rows OR2[23-25] = 100
* EAD set for extra time OR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
#define CFG_OR2_PRELIM 0xfc006901
-#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
-#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
-#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
+#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
+#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* LSDMR masks
@@ -236,7 +252,7 @@ extern unsigned long get_clock_freq(void);
/*
* Common settings for all Local Bus SDRAM commands.
* At run time, either BSMA1516 (for CPU 1.1)
- * or BSMA1617 (for CPU 1.0) (old)
+ * or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too.
*/
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
@@ -256,61 +272,63 @@ extern unsigned long get_clock_freq(void);
* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
* port-size = 8-bits = BR[19:20] = 01
* no parity checking = BR[21:22] = 00
- * GPMC for MSEL = BR[24:26] = 000
- * Valid = BR[31] = 1
+ * GPMC for MSEL = BR[24:26] = 000
+ * Valid = BR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
*
* For OR3, need:
- * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
+ * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
* disable buffer ctrl OR[19] = 0
- * CSNT OR[20] = 1
- * ACS OR[21:22] = 11
- * XACS OR[23] = 1
+ * CSNT OR[20] = 1
+ * ACS OR[21:22] = 11
+ * XACS OR[23] = 1
* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
- * SETA OR[28] = 0
- * TRLX OR[29] = 1
- * EHTR OR[30] = 1
- * EAD extra time OR[31] = 1
+ * SETA OR[28] = 0
+ * TRLX OR[29] = 1
+ * EHTR OR[30] = 1
+ * EAD extra time OR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
*/
#define CADMUS_BASE_ADDR 0xf8000000
-#define CFG_BR3_PRELIM 0xf8000801
-#define CFG_OR3_PRELIM 0xfff00ff7
+#define CFG_BR3_PRELIM 0xf8000801
+#define CFG_OR3_PRELIM 0xfff00ff7
#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 2
+#define CONFIG_CONS_INDEX 2
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
-#define CFG_BAUDRATE_TABLE \
+#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
@@ -318,9 +336,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8548@0"
#define OF_SOC "soc8548@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -331,55 +346,74 @@ extern unsigned long get_clock_freq(void);
*/
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
+#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
+
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
-#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
-#define CFG_PCI2_MEM_BASE 0x90000000
+#ifdef CONFIG_PCI2
+#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI2_IO_BASE 0x00000000
#define CFG_PCI2_IO_PHYS 0xe2800000
-#define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */
+#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
+#endif
-#define CFG_PEX_MEM_BASE 0xa0000000
-#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
-#define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PEX_IO_BASE 0x00000000
-#define CFG_PEX_IO_PHYS 0xe3000000
-#define CFG_PEX_IO_SIZE 0x01000000 /* 16M */
+#ifdef CONFIG_PCIE1
+#define CFG_PCIE1_MEM_BASE 0xa0000000
+#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCIE1_IO_BASE 0x00000000
+#define CFG_PCIE1_IO_PHYS 0xe3000000
+#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
+#endif
+#ifdef CONFIG_RIO
/*
* RapidIO MMU
*/
#define CFG_RIO_MEM_BASE 0xC0000000
#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
+#endif
+
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_85XX_PCI2
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
#endif /* CONFIG_PCI */
@@ -387,18 +421,18 @@ extern unsigned long get_clock_freq(void);
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
-#define CONFIG_MPC85XX_TSEC3 1
-#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2"
-#undef CONFIG_MPC85XX_TSEC4
-#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC1"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC2"
+#define CONFIG_TSEC4
+#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
@@ -410,10 +444,14 @@ extern unsigned long get_clock_freq(void);
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC4_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME "eTSEC0"
-
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#endif /* CONFIG_TSEC_ENET */
/*
@@ -427,19 +465,28 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
+ #define CONFIG_CMD_PCI
#endif
-#include <cmd_confdefs.h>
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -449,7 +496,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -464,12 +511,12 @@ extern unsigned long get_clock_freq(void);
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -481,7 +528,7 @@ extern unsigned long get_clock_freq(void);
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -492,58 +539,154 @@ extern unsigned long get_clock_freq(void);
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
+#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
#define CONFIG_HAS_ETH3
-#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
-#define CONFIG_IPADDR 192.168.1.253
+#define CONFIG_IPADDR 192.168.1.253
-#define CONFIG_HOSTNAME unknown
-#define CONFIG_ROOTPATH /nfsroot
-#define CONFIG_BOOTFILE your.uImage
+#define CONFIG_HOSTNAME unknown
+#define CONFIG_ROOTPATH /nfsroot
+#define CONFIG_BOOTFILE 8548cds/uImage.uboot
+#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
-#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
+#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
-#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CONFIG_BAUDRATE 115200
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS1\0" \
- "ramdiskaddr=600000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0" \
- "fdtaddr=400000\0" \
- "fdtfile=your.fdt.dtb\0"
+#if defined(CONFIG_PCIE1)
+#define PCIE_ENV \
+ "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
+ "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
+ "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
+ "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
+ "pci d $b.0 130 1\0" \
+ "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \
+ "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\
+ "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
+ "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
+ "pcie1regs=setenv a e000a; run pciereg\0" \
+ "pcie1cfg=setenv b 3; run pciecfg\0" \
+ "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
+ "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0"
+#else
+#define PCIE_ENV ""
+#endif
+
+#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
+#define PCI_ENV \
+ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
+ "echo e;md ${a}e00 9\0" \
+ "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \
+ "pci d.w $b.0 56 1\0" \
+ "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
+ "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0"
+#else
+#define PCI_ENV ""
+#endif
+
+#if defined(CONFIG_PCI1)
+#define PCI_ENV1 \
+ "pci1regs=setenv a e0008; run pcireg\0" \
+ "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \
+ "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0"
+#else
+#define PCI_ENV1 ""
+#endif
+
+#if defined(CONFIG_PCI2)
+#define PCI_ENV2 \
+ "pci2regs=setenv a e0009; run pcireg\0" \
+ "pci2err=setenv a e0009; setenv b 123; run pcierr\0" \
+ "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0"
+#else
+#define PCI_ENV2 ""
+#endif
+#if defined(CONFIG_TSEC_ENET)
+#define ENET_ENV \
+ "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
+ "md ${a}098 2\0" \
+ "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
+ "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
+ "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
+ "echo mib;md ${a}680 31\0" \
+ "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
+ "enet1regs=setenv a e0024; run enetreg\0" \
+ "enet2regs=setenv a e0025; run enetreg\0" \
+ "enet3regs=setenv a e0026; run enetreg\0" \
+ "enet4regs=setenv a e0027; run enetreg\0"
+#else
+#define ENET_ENV ""
+#endif
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "consoledev=ttyS1\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=mpc8548cds.dtb\0" \
+ "eoi=mw e00400b0 0\0" \
+ "iack=md e00400a0 1\0" \
+ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
+ "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
+ "ddrregs=setenv a e0002; run ddrreg\0" \
+ "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
+ "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
+ "guregs=setenv a e00e0; run gureg\0" \
+ "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
+ "ecmregs=setenv a e0001; run ecmreg\0" \
+ "lawregs=md e0000c08 4b\0" \
+ "lbcregs=md e0005000 36\0" \
+ "dma0regs=md e0021100 12\0" \
+ "dma1regs=md e0021180 12\0" \
+ "dma2regs=md e0021200 12\0" \
+ "dma3regs=md e0021280 12\0" \
+ PCIE_ENV \
+ PCI_ENV \
+ PCI_ENV1 \
+ PCI_ENV2 \
+ ENET_ENV
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "bootm $loadaddr $ramdiskaddr"
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 4c8b4e73f3b..1d1b7c90795 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -312,9 +312,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8555@0"
#define OF_SOC "soc8555@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -350,6 +347,13 @@ extern unsigned long get_clock_freq(void);
#define CFG_PCI2_IO_PHYS 0xe2100000
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
#if defined(CONFIG_PCI)
@@ -373,17 +377,16 @@ extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPC85XX_FEC
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
-#define FEC_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
-#define FEC_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
@@ -401,19 +404,28 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
+ #define CONFIG_CMD_PCI
#endif
-#include <cmd_confdefs.h>
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -423,7 +435,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -443,7 +455,7 @@ extern unsigned long get_clock_freq(void);
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -455,7 +467,7 @@ extern unsigned long get_clock_freq(void);
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -466,6 +478,7 @@ extern unsigned long get_clock_freq(void);
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 21e66376805..a8f362fa134 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -43,9 +43,7 @@
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#undef CONFIG_TSEC_ENET /* tsec ethernet support */
-#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
-#define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
+#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
@@ -294,9 +292,6 @@
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8560@0"
#define OF_SOC "soc8560@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -349,29 +344,33 @@
#endif /* CONFIG_PCI */
-#if defined(CONFIG_TSEC_ENET)
+#ifdef CONFIG_TSEC_ENET
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
+#ifndef CONFIG_MII
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPC85XX_FEC
+#endif
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
-#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
+#endif /* CONFIG_TSEC_ENET */
+
+#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
#undef CONFIG_ETHER_NONE /* define if ether on something else */
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
@@ -392,7 +391,10 @@
#define FETH3_RST 0x80
#endif /* CONFIG_ETHER_INDEX */
-#define CONFIG_MII /* MII PHY management */
+#ifndef CONFIG_MII
+#define CONFIG_MII 1 /* MII PHY management */
+#endif
+
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
/*
@@ -432,46 +434,36 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_CMD_MII
+#endif
+
#if defined(CFG_RAMBOOT)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #elif defined(CONFIG_TSEC_ENET)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C) \
- & ~(CFG_CMD_ENV))
- #elif defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- | CFG_CMD_I2C) \
- & ~(CFG_CMD_ENV))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #elif defined(CONFIG_TSEC_ENET)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #elif defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #endif
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -482,7 +474,7 @@
#define CFG_LOAD_ADDR 0x1000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -503,7 +495,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -515,7 +507,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -527,6 +519,7 @@
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
@@ -553,9 +546,11 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=400000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0"
+ "consoledev=ttyCPM\0" \
+ "ramdiskaddr=1000000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=mpc8560ads.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
@@ -563,14 +558,16 @@
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr $ramdiskaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 3f65644fdd4..ba744e99f8d 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -28,20 +28,21 @@
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
#define CONFIG_MPC8568 1 /* MPC8568 specific */
#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
-#undef CONFIG_PCI
+#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
/*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */
/*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */
-/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
+/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
@@ -62,9 +63,9 @@ extern unsigned long get_clock_freq(void);
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
/*
* Only possible on E500 Version 2 or newer cores.
@@ -292,11 +293,9 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8568@0"
#define OF_SOC "soc8568@e0000000"
+#define OF_QE "qe@e0080000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600"
@@ -306,11 +305,14 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_EEPROM_ADDR 0x52
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
+#define CFG_I2C2_OFFSET 0x3100
/*
* General PCI
@@ -318,7 +320,7 @@ extern unsigned long get_clock_freq(void);
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
@@ -337,6 +339,44 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#ifdef CONFIG_QE
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#ifndef CONFIG_TSEC_ENET
+#define CONFIG_ETHPRIME "FSL UEC0"
+#endif
+#define CONFIG_PHY_MODE_NEED_CHANGE
+#define CONFIG_eTSEC_MDIO_BUS
+
+#ifdef CONFIG_eTSEC_MDIO_BUS
+#define CONFIG_MIIM_ADDRESS 0xE0024520
+#endif
+
+#define CONFIG_UEC_ETH1 /* GETH1 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CFG_UEC1_UCC_NUM 0 /* UCC1 */
+#define CFG_UEC1_RX_CLK QE_CLK_NONE
+#define CFG_UEC1_TX_CLK QE_CLK16
+#define CFG_UEC1_ETH_TYPE GIGA_ETH
+#define CFG_UEC1_PHY_ADDR 7
+#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#endif
+
+#define CONFIG_UEC_ETH2 /* GETH2 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
+#define CFG_UEC2_RX_CLK QE_CLK_NONE
+#define CFG_UEC2_TX_CLK QE_CLK16
+#define CFG_UEC2_ETH_TYPE GIGA_ETH
+#define CFG_UEC2_PHY_ADDR 1
+#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#endif
+#endif /* CONFIG_QE */
+
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -345,21 +385,17 @@ extern unsigned long get_clock_freq(void);
#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
+#if defined(CONFIG_TSEC_ENET)
+
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
-#undef CONFIG_MPC85XX_TSEC3
-#undef CONFIG_MPC85XX_TSEC4
-#undef CONFIG_MPC85XX_FEC
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 3
@@ -367,7 +403,10 @@ extern unsigned long get_clock_freq(void);
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
-/* Options are: eTSEC[0-3] */
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME "eTSEC0"
#endif /* CONFIG_TSEC_ENET */
@@ -383,19 +422,29 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
+ #define CONFIG_CMD_PCI
#endif
-#include <cmd_confdefs.h>
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -405,7 +454,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -425,7 +474,7 @@ extern unsigned long get_clock_freq(void);
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -437,7 +486,7 @@ extern unsigned long get_clock_freq(void);
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -447,12 +496,15 @@ extern unsigned long get_clock_freq(void);
*/
/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.253
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index bbe35053dd7..7d8a380dc04 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -46,8 +46,10 @@
#define CFG_RESET_ADDRESS 0xfff00100
-/*#undef CONFIG_PCI*/
-#define CONFIG_PCI
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */
+#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -76,6 +78,9 @@
#define L2_ENABLE (L2CR_L2E)
#ifndef CONFIG_SYS_CLK_FREQ
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
#endif
@@ -93,6 +98,9 @@
#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
+
/*
* DDR Setup
*/
@@ -177,6 +185,7 @@
#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
+#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
@@ -232,7 +241,7 @@
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
@@ -260,9 +269,6 @@
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8641@0"
#define OF_SOC "soc8641@f8000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
@@ -296,9 +302,9 @@
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0xe2000000
-#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
/* PCI view of System Memory */
#define CFG_PCI_MEMORY_BUS 0x00000000
@@ -311,10 +317,10 @@
#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
-#define CFG_PCI2_IO_BASE 0xe3000000
-#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xe3000000
+#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
@@ -330,12 +336,43 @@
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
+/************************************************************
+ * USB support
+ ************************************************************/
+#define CONFIG_PCI_OHCI 1
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_USB_KEYBOARD 1
+#define CFG_DEVICE_DEREGISTER
+#define CFG_USB_EVENT_POLL 1
+#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET CFG_PCI2_IO_PHYS
+
+/*PCI video card used*/
+/*#define VIDEO_IO_OFFSET CFG_PCI1_IO_PHYS*/
+
+/* video */
+#define CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_CONSOLE_CURSOR*/
+#define CFG_ISA_IO_BASE_ADDRESS CFG_PCI2_IO_PHYS
+#endif
+
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
@@ -349,6 +386,8 @@
#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
#endif
+#define CONFIG_MPC86XX_PCI2
+
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
@@ -359,14 +398,14 @@
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC86XX_TSEC1 1
-#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1"
-#define CONFIG_MPC86XX_TSEC2 1
-#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2"
-#define CONFIG_MPC86XX_TSEC3 1
-#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3"
-#define CONFIG_MPC86XX_TSEC4 1
-#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
+#define CONFIG_TSEC4 1
+#define CONFIG_TSEC4_NAME "eTSEC4"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
@@ -376,6 +415,10 @@
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC4_PHYIDX 0
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define CONFIG_ETHPRIME "eTSEC1"
@@ -396,20 +439,20 @@
* 0xa000_0000 512M PCI-Express 2 Memory
* Changed it for operating from 0xd0000000
*/
-#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
+#define CFG_DBAT1L ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
+#define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT1U CFG_DBAT1U
/*
* BAT2 512M Cache-inhibited, guarded
* 0xc000_0000 512M RapidIO Memory
*/
-#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \
+#define CFG_DBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_DBAT2U (CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT2U CFG_DBAT2U
/*
@@ -428,10 +471,10 @@
* 0xe300_0000 16M PCI-Express 2 I/0
* Note that this is at 0xe0000000
*/
-#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \
+#define CFG_DBAT4L ( CFG_PCI1_IO_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_DBAT4U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT4U CFG_DBAT4U
/*
@@ -463,8 +506,8 @@
*/
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
- #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000)
+ #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
@@ -475,39 +518,34 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
#if defined(CFG_RAMBOOT)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C \
- | CFG_CMD_SCSI \
- | CFG_CMD_EXT2) \
- & \
- ~(CFG_CMD_ENV))
- #else
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_SCSI \
- | CFG_CMD_EXT2)
- #else
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #endif
+ #undef CONFIG_CMD_ENV
+#endif
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+ #define CONFIG_CMD_SCSI
+ #define CONFIG_CMD_EXT2
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -518,7 +556,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -539,8 +577,8 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#if defined(CONFIG_CMD_KGDB)
+ #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
/*
@@ -551,9 +589,9 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#if defined(CONFIG_CMD_KGDB)
+ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
@@ -568,6 +606,7 @@
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
+#define CONFIG_HAS_ETH0 1
#define CONFIG_HAS_ETH1 1
#define CONFIG_HAS_ETH2 1
#define CONFIG_HAS_ETH3 1
@@ -577,6 +616,7 @@
#define CONFIG_HOSTNAME unknown
#define CONFIG_ROOTPATH /opt/nfsroot
#define CONFIG_BOOTFILE uImage
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
@@ -592,10 +632,17 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=your.ramdisk.u-boot\0" \
- "dtbaddr=400000\0" \
+ "dtbaddr=c00000\0" \
"dtbfile=mpc8641_hpcn.dtb\0" \
"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h
index da52e0ec0b8..f8cf01e5d3e 100644
--- a/include/configs/MUSENKI.h
+++ b/include/configs/MUSENKI.h
@@ -52,11 +52,20 @@
#define CONFIG_BOOTDELAY 5
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
/*
@@ -280,7 +289,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
index 88eefa19074..0defafec260 100644
--- a/include/configs/MVBLUE.h
+++ b/include/configs/MVBLUE.h
@@ -76,15 +76,44 @@
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY 60
-#define CONFIG_COMMANDS ( CFG_CMD_ASKENV | CFG_CMD_BOOTD | CFG_CMD_CACHE | CFG_CMD_DHCP | \
- CFG_CMD_ECHO | CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_IMI | \
- CFG_CMD_IRQ | CFG_CMD_NET | CFG_CMD_PCI | CFG_CMD_RUN )
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_RUN
-#define CONFIG_BOOTP_MASK ( 0xffffffff )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
+
/*
* Miscellaneous configurable options
@@ -310,7 +339,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h
index 5995918266d..75efd1e0e42 100644
--- a/include/configs/MVS1.h
+++ b/include/configs/MVS1.h
@@ -63,27 +63,36 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_VENDOREX )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_VENDOREX
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-/* MVsensor uses a really minimal U-Boot ! */
-#define CONFIG_COMMANDS (CFG_CMD_LOADS | \
- CFG_CMD_LOADB | \
- CFG_CMD_IMI | \
- CFG_CMD_FLASH | \
- CFG_CMD_MEMORY | \
- CFG_CMD_NET | \
- CFG_CMD_DHCP | \
- CFG_CMD_ENV | \
- CFG_CMD_BOOTD | \
- CFG_CMD_RUN )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_RUN
+
/*
* Miscellaneous configurable options
@@ -96,7 +105,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -172,7 +181,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index a12c8da13ec..c051a351e85 100644
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -85,7 +85,15 @@
#undef CONFIG_STATUS_LED /* Status LED disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
#define FEC_ENET
@@ -134,25 +142,28 @@
#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR 0x51
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_NAND | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -230,7 +241,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
index 444f721cc85..bb3d19d14ca 100644
--- a/include/configs/NETPHONE.h
+++ b/include/configs/NETPHONE.h
@@ -82,7 +82,15 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
@@ -105,20 +113,22 @@
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_NAND | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_MII | \
- CFG_CMD_CDP \
- )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_CDP
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
@@ -128,7 +138,7 @@
#define CFG_HUSH_PARSER 1
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -220,7 +230,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 25b63457c74..19743c04e87 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -77,7 +77,16 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
@@ -111,26 +120,28 @@
CFG_POST_CODEC | \
CFG_POST_DSP )
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_CDP | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_FAT | \
- CFG_CMD_IDE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_NAND | \
- CFG_CMD_NFS | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_PING | \
- 0)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_PING
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
@@ -140,7 +151,7 @@
#define CFG_HUSH_PARSER 1
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -223,7 +234,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
index e20e72495cc..fb8085d56c7 100644
--- a/include/configs/NETTA2.h
+++ b/include/configs/NETTA2.h
@@ -82,7 +82,16 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
@@ -105,20 +114,22 @@
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_NAND | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_MII | \
- CFG_CMD_CDP \
- )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_CDP
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
@@ -128,7 +139,7 @@
#define CFG_HUSH_PARSER 1
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -220,7 +231,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
index e30be0987aa..d4cb9e7ea9e 100644
--- a/include/configs/NETVIA.h
+++ b/include/configs/NETVIA.h
@@ -81,35 +81,45 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS_BASE ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-#define CONFIG_COMMANDS (CONFIG_COMMANDS_BASE | CFG_CMD_NAND)
-#else
-#define CONFIG_COMMANDS CONFIG_COMMANDS_BASE
+#define CONFIG_CMD_NAND
#endif
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -192,7 +202,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h
index d994420096b..4cd44720611 100644
--- a/include/configs/NSCU.h
+++ b/include/configs/NSCU.h
@@ -84,7 +84,15 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -93,16 +101,19 @@
#define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -117,7 +128,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -201,7 +212,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/NX823.h b/include/configs/NX823.h
index 1cb8b8ff3b5..524aa0621b9 100644
--- a/include/configs/NX823.h
+++ b/include/configs/NX823.h
@@ -55,22 +55,35 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled, for now */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_AUTOSCRIPT)
#define CONFIG_AUTOSCRIPT
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_AUTOSCRIPT
+
+
/* call various generic functions */
#define CONFIG_MISC_INIT_R
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -152,7 +165,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
index aa9d1ba735a..5840ea25f4b 100644
--- a/include/configs/OCRTC.h
+++ b/include/configs/OCRTC.h
@@ -54,20 +54,32 @@
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ASKENV | \
- CFG_CMD_ELF | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -77,7 +89,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -215,7 +227,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h
index 2e7c505f99e..937df229f16 100644
--- a/include/configs/ORSG.h
+++ b/include/configs/ORSG.h
@@ -54,20 +54,32 @@
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ASKENV | \
- CFG_CMD_ELF | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -77,7 +89,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -213,7 +225,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/OXC.h b/include/configs/OXC.h
index 787407c5eb8..8d61bcd2d41 100644
--- a/include/configs/OXC.h
+++ b/include/configs/OXC.h
@@ -51,10 +51,23 @@
#define CONFIG_BAUDRATE 9600
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+
/*
* Miscellaneous configurable options
@@ -299,7 +312,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h
index a933e1b180c..ef970f1cd7e 100644
--- a/include/configs/P3G4.h
+++ b/include/configs/P3G4.h
@@ -120,30 +120,40 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_ELF | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_UNIVERSE| \
- CFG_CMD_BSP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_UNIVERSE
+#define CONFIG_CMD_BSP
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -396,7 +406,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
index d88fff33ead..0de7591da66 100644
--- a/include/configs/PATI.h
+++ b/include/configs/PATI.h
@@ -39,14 +39,35 @@
#define CONFIG_BAUDRATE 9600
-#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \
- CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ENV | CFG_CMD_REGINFO | \
- CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_RUN | CFG_CMD_BSP | \
- CFG_CMD_IMI | CFG_CMD_EEPROM | CFG_CMD_IRQ | CFG_CMD_MISC \
-)
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MISC
+
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
@@ -71,7 +92,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "pati=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index 027dd22bf46..d6e7082f6a9 100644
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -68,17 +68,29 @@
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -97,7 +109,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -244,7 +256,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h
index 3a7f7f06474..24b25d98500 100644
--- a/include/configs/PCI5441.h
+++ b/include/configs/PCI5441.h
@@ -122,22 +122,32 @@
#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_ECHO | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IRQ | \
- CFG_CMD_LOADS | \
- CFG_CMD_LOADB | \
- CFG_CMD_MEMORY | \
- CFG_CMD_MISC | \
- CFG_CMD_RUN | \
- CFG_CMD_SAVES )
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVES
+
/*------------------------------------------------------------------------
* MISC
diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h
index 3a97fbcbde8..268b0343a36 100644
--- a/include/configs/PCIPPC2.h
+++ b/include/configs/PCIPPC2.h
@@ -53,30 +53,37 @@
#define CONFIG_PREBOOT ""
#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
- CFG_CMD_ELF | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
#define CFG_NAND_LEGACY
/*
@@ -223,7 +230,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h
index 130beb78e63..250b5860481 100644
--- a/include/configs/PCIPPC6.h
+++ b/include/configs/PCIPPC6.h
@@ -53,32 +53,39 @@
#define CONFIG_PREBOOT ""
#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
- CFG_CMD_ELF | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SCSI | \
- CFG_CMD_SNTP )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_SNTP
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
#define CFG_NAND_LEGACY
/*
@@ -225,7 +232,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 806e95f4808..efa015746e1 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -40,33 +40,42 @@
***********************************************************/
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-/***********************************************************
- * Command definitions
- ***********************************************************/
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_IDE | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_CACHE | \
- CFG_CMD_IRQ | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_REGINFO | \
- CFG_CMD_FDC | \
- CFG_CMD_SCSI | \
- CFG_CMD_FAT | \
- CFG_CMD_DATE | \
- CFG_CMD_ELF | \
- CFG_CMD_USB | \
- CFG_CMD_MII | \
- CFG_CMD_SDRAM | \
- CFG_CMD_DOC | \
- CFG_CMD_PING | \
- CFG_CMD_SAVES | \
- CFG_CMD_BSP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_FDC
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_BSP
+
#define CFG_NAND_LEGACY
@@ -150,7 +159,7 @@
**********************************************************/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -227,7 +236,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -366,7 +375,7 @@
/************************************************************
* Debug support
************************************************************/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h
index 83a7ec27b43..d90351add35 100644
--- a/include/configs/PK1C20.h
+++ b/include/configs/PK1C20.h
@@ -160,30 +160,41 @@
#define CONFIG_IPADDR 192.168.2.21
#define CONFIG_SERVERIP 192.168.2.16
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IRQ | \
- CFG_CMD_LOADS | \
- CFG_CMD_LOADB | \
- CFG_CMD_MEMORY | \
- CFG_CMD_MISC | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CFG_CMD_RUN | \
- CFG_CMD_SAVES )
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVES
+
/*------------------------------------------------------------------------
* COMPACT FLASH
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(CONFIG_CMD_IDE)
#define CONFIG_IDE_PREINIT /* Implement id_preinit */
#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */
#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */
@@ -201,12 +212,12 @@
#define CFG_CF_POWER 0x00900890 /* CF Power FET PIO base*/
#define CFG_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */
-#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */
+#endif
/*------------------------------------------------------------------------
* JFFS2
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#if defined(CONFIG_CMD_JFFS2)
#define CFG_JFFS_CUSTOM_PART /* board defined part */
#endif
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index d02c39b28f9..652210c19da 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -61,19 +61,34 @@
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ELF | \
- CFG_CMD_NAND | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -81,10 +96,6 @@
#define CONFIG_SUPPORT_VFAT
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
-#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -104,7 +115,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -156,38 +167,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
@@ -264,11 +255,6 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
@@ -294,9 +280,6 @@
#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
/* total size of a CAT24WC16 is 2048 bytes */
-#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CFG_NVRAM_SIZE 242 /* NVRAM size */
-
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
@@ -305,7 +288,7 @@
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
-#if 1 /* test-only */
+
/* CAT24WC08/16... */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
@@ -313,15 +296,6 @@
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
-#else
-/* CAT24WC32/64... */
-#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
- /* 32 byte page write mode using*/
- /* last 5 bits of the address */
-#endif
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
@@ -331,7 +305,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index 9c241e67e73..5ba8f4a4e2a 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -40,11 +40,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -77,12 +72,6 @@
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#undef CONFIG_NS8382X
-#define ADD_PCI_CMD CFG_CMD_PCI
-
-#else /* MPC5100 */
-
-#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
-
#endif
/* Partitions */
@@ -91,39 +80,48 @@
/* USB */
#if 1
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
#endif
-#if defined(CONFIG_BOOT_ROM)
-#define ADD_DOC_CMD 0
-#else
-#define ADD_DOC_CMD CFG_CMD_DOC
+#if !defined(CONFIG_BOOT_ROM)
/* DoC requires legacy NAND for now */
#define CFG_NAND_LEGACY
#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- ADD_DOC_CMD | \
- ADD_PCI_CMD | \
- ADD_USB_CMD | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+#if !defined(CONFIG_BOOT_ROM)
+#define CONFIG_CMD_DOC
+#endif
+
+#if defined(CONFIG_MPC5200)
+#define CONFIG_CMD_PCI
+#endif
+
/*
* Autobooting
@@ -160,7 +158,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
* I2C configuration
@@ -294,7 +292,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -310,6 +308,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index 88fdb51adef..c80b1538807 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -103,8 +103,7 @@
* - CONFIG_NET_MULTI must be defined
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#define CONFIG_NET_MULTI
#undef CONFIG_ETHER_NONE /* define if ether on something else */
@@ -152,33 +151,34 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
#ifdef CONFIG_PCI
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
-#else /* ! PCI */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#endif /* CONFIG_PCI */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_CMD_PCI
+#endif
+
#define CFG_NAND_LEGACY
@@ -197,7 +197,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -345,7 +345,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PM828.h b/include/configs/PM828.h
index 37ee9771b52..8f5be5f63a5 100644
--- a/include/configs/PM828.h
+++ b/include/configs/PM828.h
@@ -103,8 +103,7 @@
* - CONFIG_NET_MULTI must be defined
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#define CONFIG_NET_MULTI
#undef CONFIG_ETHER_NONE /* define if ether on something else */
@@ -152,33 +151,34 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
#ifdef CONFIG_PCI
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
-#else /* ! PCI */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#endif /* CONFIG_PCI */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_CMD_PCI
+#endif
+
/*
* Disk-On-Chip configuration
@@ -196,7 +196,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -338,7 +338,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index 4fb54402b1b..a6a1e738a80 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -262,23 +262,27 @@
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#define CONFIG_MPC85XX_FEC 1
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
+#define FEC_FLAGS 0
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
+#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1 1
#define CONFIG_HAS_ETH2 1
@@ -303,43 +307,36 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
#if defined(CFG_RAMBOOT)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #else
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_EEPROM \
- | CFG_CMD_DATE \
- | CFG_CMD_MII \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #else
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_EEPROM \
- | CFG_CMD_DATE \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #endif
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -350,7 +347,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -372,7 +369,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -384,7 +381,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 87ab9348735..9a17e3d7333 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -258,15 +258,16 @@
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPC85XX_FEC
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#endif /* CONFIG_TSEC_ENET */
@@ -306,41 +307,35 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
#if defined(CFG_RAMBOOT)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #else
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_EEPROM \
- | CFG_CMD_DATE \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #else
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_EEPROM \
- | CFG_CMD_DATE \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #endif
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -351,7 +346,7 @@
#define CFG_LOAD_ADDR 0x1000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -373,7 +368,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -385,7 +380,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -397,6 +392,7 @@
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:40:42:01:00:00
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:40:42:01:00:01
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index 6e0bd7f23ec..b29f368f57c 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -63,25 +63,37 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BSP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_I2C | \
- CFG_CMD_PING | \
- CFG_CMD_UNIVERSE | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_UNIVERSE
+#define CONFIG_CMD_EEPROM
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
@@ -100,7 +112,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -263,7 +275,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PN62.h b/include/configs/PN62.h
index a717659bb69..72acf5ae8d5 100644
--- a/include/configs/PN62.h
+++ b/include/configs/PN62.h
@@ -42,15 +42,29 @@
#define CONFIG_CONS_INDEX 1
-#define REMOVE_COMMANDS ( CFG_CMD_AUTOSCRIPT | \
- CFG_CMD_LOADS | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMLS )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_BSP
+
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
-#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~REMOVE_COMMANDS) |\
- CFG_CMD_PCI |\
- CFG_CMD_BSP)
#define CONFIG_BAUDRATE 19200 /* console baudrate */
@@ -82,10 +96,6 @@
"loadp 200000; bootm"
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-
/*
* Miscellaneous configurable options
*/
@@ -287,7 +297,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 16e2cc6d648..8a74c4f5c90 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -113,26 +113,38 @@
#endif
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_NAND | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */
@@ -162,7 +174,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -417,6 +429,8 @@
#define CFG_ENV_ADDR_REDUND 0xFFFFA000
#define CFG_ENV_SIZE_REDUND 0x2000
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
#endif /* ENVIRONMENT_IN_EEPROM */
@@ -446,7 +460,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/QS823.h b/include/configs/QS823.h
index 235bc480c7f..3657feaf703 100644
--- a/include/configs/QS823.h
+++ b/include/configs/QS823.h
@@ -189,27 +189,37 @@
#undef CONFIG_STATUS_LED /* Status LED disabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_BOOTD | \
- CFG_CMD_CONSOLE | \
- CFG_CMD_DATE | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IMMAP | \
- CFG_CMD_MEMORY | \
- CFG_CMD_NET | \
- CFG_CMD_RUN)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_RUN
+
/*-----------------------------------------------------------------------
* Environment variable storage is in FLASH, one sector before U-boot
@@ -228,7 +238,7 @@
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -303,7 +313,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/QS850.h b/include/configs/QS850.h
index 967582b45ed..3db539fa90a 100644
--- a/include/configs/QS850.h
+++ b/include/configs/QS850.h
@@ -189,27 +189,37 @@
#undef CONFIG_STATUS_LED /* Status LED disabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_BOOTD | \
- CFG_CMD_CONSOLE | \
- CFG_CMD_DATE | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IMMAP | \
- CFG_CMD_MEMORY | \
- CFG_CMD_NET | \
- CFG_CMD_RUN)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_RUN
+
/*-----------------------------------------------------------------------
* Environment variable storage is in FLASH, one sector before U-boot
@@ -228,7 +238,7 @@
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -303,7 +313,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h
index 32faa61607b..b3442de3627 100644
--- a/include/configs/QS860T.h
+++ b/include/configs/QS860T.h
@@ -92,23 +92,33 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_ASKENV | \
- CFG_CMD_NET | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
/* TODO */
@@ -136,7 +146,7 @@ CONFIG_SPI
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -210,7 +220,7 @@ CONFIG_SPI
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h
index 82228c0126b..a98b4af29e3 100644
--- a/include/configs/R360MPI.h
+++ b/include/configs/R360MPI.h
@@ -79,7 +79,14 @@
#define CONFIG_CAN_DRIVER /* CAN Driver support enabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -111,20 +118,23 @@
#define CFG_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */
#define CFG_I2C_TEM_ADDR 0x49 /* Temperature Sensors */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_NFS | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -134,7 +144,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -223,12 +233,13 @@
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
index 242c837a3b8..2f6de815514 100644
--- a/include/configs/RBC823.h
+++ b/include/configs/RBC823.h
@@ -79,7 +79,15 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#undef CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -94,42 +102,45 @@
#define CFG_EEPROM_WRITE_BITS 4
#define CFG_EEPROM_WRITE_DELAY_MS 10
-#define CONFIG_COMMANDS ( CFG_CMD_ALL & \
- ~CFG_CMD_BSP & \
- ~CFG_CMD_DATE & \
- ~CFG_CMD_DISPLAY& \
- ~CFG_CMD_DTT & \
- ~CFG_CMD_EXT2 & \
- ~CFG_CMD_FDC & \
- ~CFG_CMD_FDOS & \
- ~CFG_CMD_HWFLOW & \
- ~CFG_CMD_IDE & \
- ~CFG_CMD_IRQ & \
- ~CFG_CMD_JFFS2 & \
- ~CFG_CMD_MII & \
- ~CFG_CMD_MMC & \
- ~CFG_CMD_NAND & \
- ~CFG_CMD_PCI & \
- ~CFG_CMD_PCMCIA & \
- ~CFG_CMD_REISER & \
- ~CFG_CMD_SCSI & \
- ~CFG_CMD_SETGETDCR & \
- ~CFG_CMD_SNTP & \
- ~CFG_CMD_SPI & \
- ~CFG_CMD_UNIVERSE & \
- ~CFG_CMD_USB & \
- ~CFG_CMD_VFD & \
- ~CFG_CMD_XIMG )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_BSP
+#undef CONFIG_CMD_DATE
+#undef CONFIG_CMD_DISPLAY
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_MFSL
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_PCI
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_SNTP
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_UNIVERSE
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_XIMG
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -205,7 +216,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h
index 591382cd24d..793b1db8894 100644
--- a/include/configs/RPXClassic.h
+++ b/include/configs/RPXClassic.h
@@ -88,15 +88,26 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-#define CONFIG_COMMANDS ((CFG_CMD_ALL & ~CFG_CMD_NONSTD) | CFG_CMD_ELF)
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -104,7 +115,7 @@
#define CFG_RESET_ADDRESS 0x80000000
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -182,7 +193,7 @@
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFF000000
-#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
@@ -222,7 +233,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h
index 48ada0ed9b6..3c5e6b89139 100644
--- a/include/configs/RPXlite.h
+++ b/include/configs/RPXlite.h
@@ -62,17 +62,28 @@
#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -154,7 +165,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h
index 31025473f43..872765c92f4 100644
--- a/include/configs/RPXlite_DW.h
+++ b/include/configs/RPXlite_DW.h
@@ -115,29 +115,36 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#if 1 /* Enable this stuff could make image enlarge about 25KB. Mask it if you
don't want the advanced function */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_DHCP
+
#ifdef CONFIG_SPLASH_SCREEN
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BMP | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_PING | \
- CFG_CMD_ELF | \
- CFG_CMD_REGINFO | \
- CFG_CMD_DHCP )
-#else
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_PING | \
- CFG_CMD_ELF | \
- CFG_CMD_REGINFO | \
- CFG_CMD_DHCP )
-#endif /* CONFIG_SPLASH_SCREEN */
+#define CONFIG_CMD_BMP
+#endif
+
/* test-only */
#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
@@ -147,16 +154,13 @@
#endif /* 1 */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "u-boot>" /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -200,7 +204,7 @@
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFF000000
-#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
@@ -239,7 +243,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h
index 45907aa0e79..dfadd2a11f0 100644
--- a/include/configs/RPXsuper.h
+++ b/include/configs/RPXsuper.h
@@ -91,8 +91,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
@@ -150,13 +149,28 @@
/* Monitor Command Prompt */
#define CFG_PROMPT "=> "
-/* What U-Boot subsytems do you want enabled? */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_IMMAP | \
- CFG_CMD_ASKENV | \
- CFG_CMD_I2C | \
- CFG_CMD_REGINFO & \
- ~CFG_CMD_KGDB )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_CMD_KGDB
+
/* Where do the internal registers live? */
#define CFG_IMMR 0xF0000000
@@ -176,13 +190,10 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -310,7 +321,7 @@
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h
index 3885bcdb1ef..32e22854545 100644
--- a/include/configs/RRvision.h
+++ b/include/configs/RRvision.h
@@ -92,7 +92,15 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -135,23 +143,26 @@
#endif /* CONFIG_SOFT_I2C */
-#define CONFIG_COMMANDS ( ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_DATE ) & \
- ~( CFG_CMD_PCMCIA | \
- CFG_CMD_IDE ) )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DATE
+
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_IDE
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -224,11 +235,13 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h
index dbc57e8b271..d7652fa9ba5 100644
--- a/include/configs/Rattler.h
+++ b/include/configs/Rattler.h
@@ -62,8 +62,8 @@
* SCC, 1-3 for FCC)
*
* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CFG_CMD_NET must
- * be removed from CONFIG_COMMANDS to remove support for networking.
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
@@ -125,22 +125,33 @@
#define CONFIG_BAUDRATE 38400
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_DHCP \
- | CFG_CMD_IMMAP \
- | CFG_CMD_JFFS2 \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -158,7 +169,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -184,7 +195,7 @@
#define CFG_DIRECT_FLASH_TFTP
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#if defined(CONFIG_CMD_JFFS2)
#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
#define CFG_JFFS2_SORT_FRAGMENTS
@@ -205,7 +216,7 @@
#define MTDIDS_DEFAULT "nor0=rattler-0"
#define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)"
*/
-#endif /* CFG_CMD_JFFS2 */
+#endif /* CONFIG_CMD_JFFS2 */
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
@@ -256,7 +267,7 @@
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index f8e3397a3f0..f2c3699ab74 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -338,28 +338,37 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV | \
- CFG_CMD_LOADS ))
- #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C)
- #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C)
- #endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_CMD_MII
+#endif
+
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -368,7 +377,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "SBC8540=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -389,7 +398,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -401,7 +410,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/SCM.h b/include/configs/SCM.h
index e263db65a2f..f900968c5a1 100644
--- a/include/configs/SCM.h
+++ b/include/configs/SCM.h
@@ -133,8 +133,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*
* (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
* X.29 connector, and FCC2 is hardwired to the X.1 connector)
@@ -191,23 +190,33 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_BSP)
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_BSP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -353,7 +362,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/SL8245.h b/include/configs/SL8245.h
index 61896d0d7d1..4d9d41b9277 100644
--- a/include/configs/SL8245.h
+++ b/include/configs/SL8245.h
@@ -53,11 +53,22 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#include <cmd_confdefs.h>
+#define CONFIG_CMD_PCI
/*
@@ -255,7 +266,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/SM850.h b/include/configs/SM850.h
index 49776291211..41a54f0f5ad 100644
--- a/include/configs/SM850.h
+++ b/include/configs/SM850.h
@@ -68,23 +68,34 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && defined(KGDB_DEBUG)
+#if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -167,7 +178,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h
new file mode 100644
index 00000000000..a5d3d695889
--- /dev/null
+++ b/include/configs/SMN42.h
@@ -0,0 +1,206 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Configuation settings for the SMN42 board from Siemens.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start u-boot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#undef CONFIG_INIT_CRITICAL /* undef for developing */
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
+#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
+#define CONFIG_LPC2292
+#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
+
+#undef CONFIG_USE_IRQ /* don't need them anymore */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1 1 /* we use Serial line 1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/* enable I2C and select the hardware/software driver */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+/* this would be 0xAE if E0, E1 and E2 were pulled high */
+#define CFG_I2C_SLAVE 0xA0
+#define CFG_I2C_EEPROM_ADDR (0xA0 >> 1)
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit address */
+#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+/* not used but required by devices.c */
+#define CFG_I2C_SPEED 10000
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define SCL 0x00000004 /* P0.2 */
+#define SDA 0x00000008 /* P0.3 */
+
+#define I2C_READ ((GET32(IO0PIN) & SDA) ? 1 : 0)
+#define I2C_SDA(x) { if (x) PUT32(IO0SET, SDA); else PUT32(IO0CLR, SDA); }
+#define I2C_SCL(x) { if (x) PUT32(IO0SET, SCL); else PUT32(IO0CLR, SCL); }
+#define I2C_DELAY { udelay(100); }
+#define I2C_ACTIVE { unsigned int i2ctmp; \
+ i2ctmp = GET32(IO0DIR); \
+ i2ctmp |= SDA; \
+ PUT32(IO0DIR, i2ctmp); }
+#define I2C_TRISTATE { unsigned int i2ctmp; \
+ i2ctmp = GET32(IO0DIR); \
+ i2ctmp &= ~SDA; \
+ PUT32(IO0DIR, i2ctmp); }
+#endif /* CONFIG_SOFT_I2C */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PING
+
+
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_BOOTDELAY 5
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "SMN42 # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x81800000 /* memtest works on */
+#define CFG_MEMTEST_END 0x83000000 /* 24 MB in SRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0x81000000 /* default load address */
+ /* for uClinux img is here*/
+
+#define CFG_SYS_CLK_FREQ 58982400 /* Hz */
+#define CFG_HZ 2048 /* decrementer freq in Hz */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SRAM */
+#define PHYS_SDRAM_1 0x81000000 /* SRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB SRAM */
+
+/* This is the external flash */
+#define PHYS_FLASH_1 0x80000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/*
+ * The first entry in CFG_FLASH_BANKS_LIST is a dummy, but it must be present.
+ */
+#define CFG_FLASH_BANKS_LIST { 0, PHYS_FLASH_1 }
+#define CFG_FLASH_ADDR0 0x555
+#define CFG_FLASH_ADDR1 0x2AA
+#define CFG_FLASH_ERASE_TOUT 16384 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
+
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+
+#define CFG_ENV_IS_IN_FLASH 1
+/* The Environment Sector is in the CPU-internal flash */
+#define CFG_FLASH_BASE 0
+#define CFG_ENV_OFFSET 0x3C000
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_MMC 1
+/* we use this ethernet chip */
+#define CONFIG_ENC28J60
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h
index ae4dcc2ccca..395c7a1e7a0 100644
--- a/include/configs/SPD823TS.h
+++ b/include/configs/SPD823TS.h
@@ -59,15 +59,29 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_COMMANDS \
-((CONFIG_CMD_DFL & ~(CFG_CMD_FLASH)) | CFG_CMD_IDE) /* no Flash, but IDE */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+
+#undef CONFIG_CMD_FLASH
+
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*----------------------------------------------------------------------*/
#define CONFIG_ETHADDR 00:D0:93:00:01:CB
@@ -82,7 +96,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -160,7 +174,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/SX1.h b/include/configs/SX1.h
index 6ed98b8fb18..05cef873e5f 100644
--- a/include/configs/SX1.h
+++ b/include/configs/SX1.h
@@ -93,12 +93,26 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | \
- CFG_CMD_I2C ) & \
- ~CFG_CMD_NET)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+
+#undef CONFIG_CMD_NET
+
+
#include <configs/omap1510.h>
#define CONFIG_BOOTARGS "mem=16M console=ttyS0,115200n8 root=/dev/mtdblock3 rw"
diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h
index a8454d99fc0..8f2a5ece2c7 100644
--- a/include/configs/SXNI855T.h
+++ b/include/configs/SXNI855T.h
@@ -146,14 +146,26 @@
#define CFG_DISCOVER_PHY
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_NAND | \
- CFG_CMD_DATE)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DATE
+
#define CFG_JFFS2_SORT_FRAGMENTS
@@ -226,7 +238,7 @@
*/
#define CFG_LONGHELP /* undef to save a little memory */
#define CFG_PROMPT "=>" /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -309,7 +321,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h
index f4339ecd9c8..5bbe3c5919d 100644
--- a/include/configs/Sandpoint8240.h
+++ b/include/configs/Sandpoint8240.h
@@ -80,18 +80,30 @@
""
#define CONFIG_BOOTCOMMAND "run flash_self"
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_SDRAM | \
- CFG_CMD_EEPROM | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
+
#define CONFIG_DRAM_SPEED 100 /* MHz */
@@ -384,7 +396,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h
index d42bd69231e..a08451eb30b 100644
--- a/include/configs/Sandpoint8245.h
+++ b/include/configs/Sandpoint8245.h
@@ -51,17 +51,28 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
/*
@@ -363,7 +374,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
index 119bc2442bb..dccdf0ca9b4 100644
--- a/include/configs/TASREG.h
+++ b/include/configs/TASREG.h
@@ -43,6 +43,10 @@
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
@@ -50,20 +54,34 @@
#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C ) & \
- ~(CFG_CMD_NET))
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+
+#undef CONFIG_CMD_NET
+
+
#define CONFIG_BOOTDELAY 3
#define CFG_PROMPT "=> "
#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
index 8a6e5a61b73..1c6a9ae4f1b 100644
--- a/include/configs/TB5200.h
+++ b/include/configs/TB5200.h
@@ -42,11 +42,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -72,12 +67,6 @@
#define CFG_CONSOLE_IS_IN_ENV
#endif
-#ifdef CONFIG_VIDEO
-#define ADD_BMP_CMD CFG_CMD_BMP
-#else
-#define ADD_BMP_CMD 0
-#endif
-
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -85,7 +74,6 @@
/* USB */
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
/* POST support */
@@ -94,41 +82,51 @@
CFG_POST_I2C)
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#else
-#define CFG_CMD_POST_DIAG 0
#endif
-/* IDE */
-#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
/*
- * Supported commands
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- ADD_BMP_CMD | \
- ADD_IDE_CMD | \
- ADD_PCI_CMD | \
- ADD_USB_CMD | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP | \
- CFG_CMD_BSP)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
+
+#ifdef CONFIG_POST
+#define CONFIG__CMD_DIAG
+#endif
+
#define CONFIG_TIMESTAMP /* display image timestamps */
@@ -200,17 +198,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@@ -394,7 +392,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -403,6 +401,11 @@
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST
@@ -414,8 +417,7 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -432,7 +434,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
index f41dbd0ccb1..7240ce12835 100644
--- a/include/configs/TOP5200.h
+++ b/include/configs/TOP5200.h
@@ -50,11 +50,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -81,12 +76,6 @@
# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
# define CONFIG_PCI_IO_SIZE 0x01000000
-# define ADD_PCI_CMD CFG_CMD_PCI
-
-#else /* no Evaluation board */
-
-# define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
-
#endif
/* USB */
@@ -99,49 +88,49 @@
# else
# define CONFIG_USB_CONFIG 0x00001000
# endif
-# define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
# define CONFIG_DOS_PARTITION
# define CONFIG_USB_STORAGE
-#else
-
-# define ADD_USB_CMD 0
-
#endif
/* IDE */
#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
-
-# define ADD_IDE_CMD CFG_CMD_IDE | CFG_CMD_FAT
# define CONFIG_DOS_PARTITION
+#endif
-#else
-# define ADD_IDE_CMD 0
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#endif
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- ADD_PCI_CMD | \
- ADD_USB_CMD | \
- ADD_IDE_CMD | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_ELF | \
- CFG_CMD_MII | \
- CFG_CMD_BEDBUG \
- )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_REGINFO
+
+#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_PCI
+#endif
+
/*
* MUST be low boot - HIGHBOOT is not supported anymore
@@ -186,7 +175,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
@@ -336,7 +325,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -352,6 +341,12 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+
#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */
#define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */
#define RTC(reg) (0xf0010000+reg)
diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h
index 2344b96811b..66f7a1150d0 100644
--- a/include/configs/TOP860.h
+++ b/include/configs/TOP860.h
@@ -107,30 +107,28 @@
*/
#define CFG_MATCH_PARTIAL_CMD
+
/*
- * List of available monitor commands. Use the system default list
- * plus add some of the "non-standard" commands back in.
- * See ./cmd_confdefs.h
- */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_MII | \
- CFG_CMD_BEDBUG \
- )
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_BEDBUG
+
#define CONFIG_AUTOSCRIPT 1
#define CFG_LOADS_BAUD_CHANGE 1
#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
@@ -141,7 +139,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -239,7 +237,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
@@ -411,10 +409,11 @@
/*
* BOOTP options
*/
-#undef CONFIG_BOOTP_MASK
-#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE \
- )
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
/*
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 7069b35ad60..e0c9d81be08 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -44,14 +44,9 @@
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -105,12 +100,6 @@
#define CONFIG_NS8382X 1
#endif /* CONFIG_STK52XX */
-#ifdef CONFIG_PCI
-#define ADD_PCI_CMD CFG_CMD_PCI
-#else
-#define ADD_PCI_CMD 0
-#endif
-
/*
* Video console
*/
@@ -133,11 +122,6 @@
#define CFG_CONSOLE_IS_IN_ENV
#endif /* #ifndef CONFIG_TQM5200S */
-#ifdef CONFIG_VIDEO
-#define ADD_BMP_CMD CFG_CMD_BMP
-#else
-#define ADD_BMP_CMD 0
-#endif
/* Partitions */
#define CONFIG_MAC_PARTITION
@@ -146,11 +130,17 @@
/* USB */
#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
-#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT
+#define CFG_USB_OHCI_REGS_BASE MPC5XXX_USB
+#define CFG_USB_OHCI_SLOT_NAME "mpc5200"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
#endif
#ifndef CONFIG_CAM5200
@@ -161,44 +151,61 @@
#endif
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#else
-#define CFG_CMD_POST_DIAG 0
#endif
-/* IDE */
-#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) || defined(CONFIG_FO300)
-#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
-#else
-#define ADD_IDE_CMD 0
-#endif
/*
- * Supported commands
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- ADD_BMP_CMD | \
- ADD_IDE_CMD | \
- ADD_PCI_CMD | \
- ADD_USB_CMD | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP | \
- CFG_CMD_BSP)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_BSP
+
+#ifdef CONFIG_VIDEO
+ #define CONFIG_CMD_BMP
+#endif
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_CMD_PCI
+#endif
+
+#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+ #define CONFIG_CMD_IDE
+ #define CONFIG_CMD_FAT
+ #define CONFIG_CMD_EXT2
+#endif
+
+#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+ #define CONFIG_CFG_USB
+ #define CONFIG_CFG_FAT
+#endif
+
+#ifdef CONFIG_POST
+ #define CONFIG_CMD_DIAG
+#endif
+
#define CONFIG_TIMESTAMP /* display image timestamps */
@@ -234,15 +241,21 @@
#ifndef CONFIG_CAM5200
#define CUSTOM_ENV_SETTINGS \
"bootfile=/tftpboot/tqm5200/uImage\0" \
+ "bootfile_fdt=/tftpboot/tqm5200/uImage_fdt\0" \
+ "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0"
#else
-#define CUSTOM_ENV_SETTINGS \
+#define CUSTOM_ENV_SETTINGS \
"bootfile=cam5200/uImage\0" \
"u-boot=cam5200/u-boot.bin\0" \
"setup=tftp 200000 cam5200/setup.img; autoscr 200000\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=ttyS0\0" \
+ "kernel_addr=200000\0" \
+ "fdt_addr=400000\0" \
+ "hostname=tqm5200\0" \
"netdev=eth0\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@@ -252,13 +265,17 @@
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addcons=setenv bootargs ${bootargs} " \
- "console=ttyS0,${baudrate}\0" \
+ "console=${console},${baudrate}\0" \
"flash_self=run ramargs addip addcons;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addcons;" \
"bootm ${kernel_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
- "bootm\0" \
+ "net_nfs=tftp ${kernel_addr} ${bootfile};" \
+ "run nfsargs addip addcons;bootm\0" \
+ "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt};" \
+ "tftp ${fdt_addr} ${fdt_file};setenv console ttyPSC0;" \
+ "run nfsargs addip addcons;" \
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
CUSTOM_ENV_SETTINGS \
"load=tftp 200000 ${u-boot}\0" \
ENV_UPDT \
@@ -269,17 +286,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133) && !defined(CONFIG_CAM5200)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
+ * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@@ -556,7 +573,12 @@
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -576,8 +598,7 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -594,7 +615,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
@@ -676,4 +697,16 @@
/* Interval between registers */
#define CFG_ATA_STRIDE 4
+/*-----------------------------------------------------------------------
+ * Open firmware flat tree support
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,5200@0"
+#define OF_SOC "soc5200@f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
+
#endif /* __CONFIG_H */
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index 247f705fb66..7a3801026fb 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -70,8 +70,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -88,34 +89,38 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
#ifdef CONFIG_SPLASH_SCREEN
-# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BMP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#else
-# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+ #define CONFIG_CMD_BMP
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -129,7 +134,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -201,6 +206,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -212,7 +219,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index 1461b5f2031..e8b6a80b19e 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -70,8 +70,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -88,23 +89,34 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -118,7 +130,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -191,6 +203,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -202,7 +216,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h
index ffd5c0b95ca..3b7832397f2 100644
--- a/include/configs/TQM8260.h
+++ b/include/configs/TQM8260.h
@@ -167,8 +167,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*
* (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
* X.29 connector, and FCC2 is hardwired to the X.1 connector)
@@ -220,17 +219,28 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -244,7 +254,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -385,7 +395,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
index 925bf343171..50f67524fde 100644
--- a/include/configs/TQM8272.h
+++ b/include/configs/TQM8272.h
@@ -97,10 +97,6 @@
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-#define ADD_CMD_I2C CFG_CMD_I2C | \
- CFG_CMD_DATE |\
- CFG_CMD_DTT |\
- CFG_CMD_EEPROM
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
@@ -140,7 +136,6 @@
#else
#undef CONFIG_HARD_I2C
#undef CONFIG_SOFT_I2C
-#define ADD_CMD_I2C 0
#endif
/*
@@ -177,8 +172,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*
* (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
* X.29 connector, and FCC2 is hardwired to the X.1 connector)
@@ -272,20 +266,37 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_NAND | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- ADD_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
+#if CONFIG_I2C
+ #define CONFIG_CMD_I2C
+ #define CONFIG_CMD_DATE
+ #define CONFIG_CMD_DTT
+ #define CONFIG_CMD_EEPROM
+#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -301,7 +312,7 @@
#endif
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -392,7 +403,7 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
#define CFG_NAND_CS_DIST 0x80
#define CFG_NAND_UPM_WRITE_CMD_OFS 0x20
@@ -430,7 +441,7 @@
WRITE_NAND(d, addr); \
} while(0)
-#endif /* CFG_CMD_NAND */
+#endif /* CONFIG_CMD_NAND */
#define CONFIG_PCI
#ifdef CONFIG_PCI
@@ -502,7 +513,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index ed0357791b4..01472529d04 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -28,9 +28,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define DEBUG
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
@@ -248,14 +245,16 @@ extern int tqm834x_num_flash_banks;
#define CONFIG_NET_MULTI
#endif
-#define CONFIG_MPC83XX_TSEC1 1
-#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC83XX_TSEC2 1
-#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
@@ -281,7 +280,6 @@ extern int tqm834x_num_flash_banks;
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
-
#undef CONFIG_EEPRO100
#define CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -316,38 +314,36 @@ extern int tqm834x_num_flash_banks;
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-/* Common commands */
-#define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\
- | CFG_CMD_PING | CFG_CMD_EEPROM \
- | CFG_CMD_MII | CFG_CMD_JFFS2
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#if defined(CFG_RAMBOOT)
-#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \
- | CFG_CMD_TQM8349_COMMON) \
- & \
- ~(CFG_CMD_ENV | CFG_CMD_LOADS))
-#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_TQM8349_COMMON) \
- & \
- ~(CFG_CMD_ENV | CFG_CMD_LOADS))
-#endif
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#else /* CFG_RAMBOOT */
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \
- | CFG_CMD_TQM8349_COMMON)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_TQM8349_COMMON)
+ #define CONFIG_CMD_PCI
#endif
-#endif /* CFG_RAMBOOT */
-
-#include <cmd_confdefs.h>
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
+#endif
/*
* Miscellaneous configurable options
@@ -362,7 +358,7 @@ extern int tqm834x_num_flash_banks;
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -387,7 +383,7 @@ extern int tqm834x_num_flash_banks;
*/
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -495,7 +491,7 @@ extern int tqm834x_num_flash_banks;
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -505,6 +501,7 @@ extern int tqm834x_num_flash_banks;
*/
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR D2:DA:5E:44:BC:29
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index 90ecbadb2e1..beeca6343e8 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -66,8 +66,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM850L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -80,23 +81,33 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -110,7 +121,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -182,6 +193,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -193,7 +206,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index b3f8f8d835a..d5609c1d485 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -64,8 +64,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM850M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -78,23 +79,33 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -108,7 +119,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -181,6 +192,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -192,7 +205,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index 49aaeea44de..e35b5b2ac1e 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -69,8 +69,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM855L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -83,23 +84,34 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -113,7 +125,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -185,6 +197,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -196,7 +210,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index 50df49e93cc..cd5212eff8e 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -69,8 +69,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM855M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -116,24 +117,35 @@
#define CFG_EEPROM_PAGE_WRITE_BITS 5
#endif
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -147,7 +159,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -220,6 +232,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -231,7 +245,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index f45f3a2f5ac..6dbd3924bdd 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -94,7 +94,6 @@
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
-#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/
#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
/* TQM8540 & 8560 need DLL-override */
@@ -258,16 +257,20 @@
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
+#define FEC_FLAGS 0
+#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
@@ -357,24 +360,35 @@
#define CONFIG_TIMESTAMP /* Print image info with ts */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_MII
+
#if defined(CONFIG_PCI)
-# define ADD_PCI_CMD (CFG_CMD_PCI)
-#else
-# define ADD_PCI_CMD 0
+ #define CONFIG_CMD_PCI
#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP | \
- ADD_PCI_CMD | \
- CFG_CMD_I2C | \
- CFG_CMD_DATE | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DTT | \
- CFG_CMD_MII | \
- CFG_CMD_PING )
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -385,7 +399,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -406,7 +420,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
#endif
@@ -418,7 +432,7 @@
#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -435,7 +449,7 @@
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
- CFG_BOOTFILE \
+ "bootfile="CFG_BOOTFILE_PATH"\0" \
"netdev=eth0\0" \
"consdev=ttyS0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index 9be5db1e424..d5838dbf372 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -69,8 +69,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -83,26 +84,37 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#define CONFIG_NETCONSOLE
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+#define CONFIG_NETCONSOLE
/*
* Miscellaneous configurable options
@@ -116,7 +128,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -188,6 +200,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -199,7 +213,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 37f6c985d3a..684b86f2efe 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -69,8 +69,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -83,24 +84,35 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -114,7 +126,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -187,6 +199,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -198,7 +212,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index f03690a7b21..f09d3d1654f 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -72,8 +72,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM862L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -86,23 +87,34 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -116,7 +128,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -189,6 +201,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -200,7 +214,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index 495934045f9..039aa3af428 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -72,8 +72,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM862M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -86,23 +87,34 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -116,7 +128,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -190,6 +202,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -201,7 +215,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index 148490b5863..0d778919a2b 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -81,8 +81,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM866M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -125,7 +126,15 @@
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -134,16 +143,19 @@
#define CONFIG_TIMESTAMP /* but print image timestmps */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+
/*
* Miscellaneous configurable options
@@ -157,7 +169,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -230,6 +242,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -241,7 +255,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index d470ade847d..f36b729cd5e 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -131,7 +131,15 @@
# define CONFIG_RTC_DS1337 1
# define CFG_I2C_RTC_ADDR 0x68
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -140,19 +148,22 @@
#define CONFIG_TIMESTAMP /* but print image timestmps */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+
/*
* Miscellaneous configurable options
@@ -166,7 +177,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -187,8 +198,7 @@
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
- * Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -258,7 +268,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
@@ -478,7 +488,7 @@
#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
-#if (CONFIG_COMMANDS & CFG_CMD_MII)
+#if defined(CONFIG_CMD_MII)
#define CFG_DISCOVER_PHY
#endif
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
index 81757032362..9edf79022dc 100644
--- a/include/configs/Total5200.h
+++ b/include/configs/Total5200.h
@@ -48,11 +48,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -63,7 +58,6 @@
/*
* Video console
*/
-#if 1
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SED13806
#define CONFIG_VIDEO_SED13806_16BPP
@@ -76,10 +70,6 @@
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
-#define ADD_VIDEO_CMD CFG_CMD_BMP
-#else
-#define ADD_VIDEO_CMD 0
-#endif
#ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */
/*
@@ -105,12 +95,9 @@
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
-#define ADD_PCI_CMD CFG_CMD_PCI
-
#else /* MGT5100 */
#define CONFIG_MII 1
-#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
#endif
@@ -119,29 +106,36 @@
#define CONFIG_DOS_PARTITION
/* USB */
-#if 1
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
-#endif
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PING | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_IDE | \
- ADD_VIDEO_CMD | \
- ADD_PCI_CMD | \
- ADD_USB_CMD)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#if defined(CONFIG_MPC5200)
+ #define CONFIG_CMD_PCI
+#endif
+
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
#if (TEXT_BASE == 0xFE000000) /* Boot low */
# define CFG_LOWBOOT 1
@@ -183,7 +177,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
@@ -303,7 +297,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -319,6 +313,12 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+
/*
* Various low-level settings
*/
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 5f48a709381..df6894f3240 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -48,27 +48,33 @@
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_CACHE | \
- /*CFG_CMD_JFFS2 |*/ \
- /*CFG_CMD_NAND |*/ \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_USB | \
- CFG_CMD_REGINFO | \
- CFG_CMD_FAT | \
- CFG_CMD_DATE | \
- CFG_CMD_ELF | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_BSP)
-
-/* this must be included after the definiton of CONFIG_COMMANDS */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
@@ -145,7 +151,7 @@
#define CONFIG_IPADDR 10.0.0.110
#define CONFIG_SERVERIP 10.0.0.1
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
@@ -246,7 +252,7 @@
/*-----------------------------------------------------------------------
* NAND flash settings
*/
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
@@ -280,6 +286,6 @@
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_MTD_NAND_ECC_JFFS2 1
-#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
+#endif
#endif /* __CONFIG_H */
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index 96f3d26cc5e..14848abe5b2 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -58,28 +58,40 @@
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ELF | \
- CFG_CMD_NAND | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
@@ -98,7 +110,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -141,38 +153,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
@@ -319,7 +311,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index f2f3ea7cc4d..5512f4be21a 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -60,24 +60,33 @@
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_BSP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -96,7 +105,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -244,7 +253,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h
index 92bade5187e..14057847b82 100644
--- a/include/configs/VoVPN-GW.h
+++ b/include/configs/VoVPN-GW.h
@@ -95,8 +95,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC
#define CONFIG_ETHER_ON_FCC
@@ -138,24 +137,34 @@
#endif
-/* configure commands */
-#define CONFIG_COMMANDS ( CFG_CMD_AUTOSCRIPT | \
- CFG_CMD_BDI | \
- CFG_CMD_CONSOLE | \
- CFG_CMD_ECHO | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IMLS | \
- CFG_CMD_LOADB | \
- CFG_CMD_MEMORY | \
- CFG_CMD_MISC | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CFG_CMD_RUN )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IMLS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+
/*
* boot options & environment
@@ -206,7 +215,7 @@
#define CFG_PROMPT "=> "
/* console i/o buffer size */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024
#else
#define CFG_CBSIZE 256
@@ -305,7 +314,7 @@
/* cache configuration */
#define CFG_CACHELINE_SIZE 32 /* for MPC8260 */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of above */
#endif
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
index 8dc623ea069..fc177fb1f56 100644
--- a/include/configs/W7OLMC.h
+++ b/include/configs/W7OLMC.h
@@ -70,13 +70,31 @@
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
- CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_REGINFO
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
@@ -92,7 +110,7 @@
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -277,7 +295,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */
#endif
@@ -309,7 +327,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
index 2bd98b3af33..20d693fa478 100644
--- a/include/configs/W7OLMG.h
+++ b/include/configs/W7OLMG.h
@@ -75,14 +75,34 @@
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
- CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO | \
- CFG_CMD_DTT)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_DTT
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
@@ -98,7 +118,7 @@
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -278,7 +298,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */
#endif
@@ -310,7 +330,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index faf855d2492..656784aa0cc 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -60,19 +60,31 @@
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_NAND | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -92,7 +104,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -133,38 +145,16 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
+
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
+
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
/*-----------------------------------------------------------------------
@@ -270,7 +260,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h
index 9b32514867a..611f5a62caa 100644
--- a/include/configs/XPEDITE1K.h
+++ b/include/configs/XPEDITE1K.h
@@ -182,25 +182,33 @@ extern void out32(unsigned int, unsigned long);
#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */
#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_I2C | \
- CFG_CMD_DATE | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_PING | \
- CFG_CMD_ELF | \
- CFG_CMD_MII | \
- CFG_CMD_DIAG | \
- CFG_CMD_FAT )
-
-/* CFG_CMD_DHCP | \ */
-/* CFG_CMD_KGDB | \ */
-
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -209,7 +217,7 @@ extern void out32(unsigned int, unsigned long);
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -238,7 +246,6 @@ extern void out32(unsigned int, unsigned long);
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
@@ -255,7 +262,7 @@ extern void out32(unsigned int, unsigned long);
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 440GX CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -267,7 +274,7 @@ extern void out32(unsigned int, unsigned long);
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h
index 37ef1058f90..00c4ff093a6 100644
--- a/include/configs/Yukon8220.h
+++ b/include/configs/Yukon8220.h
@@ -39,12 +39,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -70,31 +64,40 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BOOTD | \
- CFG_CMD_CACHE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#define CONFIG_NET_MULTI
#define CONFIG_MII
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Autobooting
*/
@@ -293,7 +296,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -309,6 +312,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
index a5085cfb79d..7c1a5b9e88f 100644
--- a/include/configs/ZPC1900.h
+++ b/include/configs/ZPC1900.h
@@ -55,8 +55,8 @@
* SCC, 1-3 for FCC)
*
* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CFG_CMD_NET must
- * be removed from CONFIG_COMMANDS to remove support for networking.
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
@@ -106,22 +106,33 @@
#define CONFIG_BAUDRATE 38400
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_ASKENV \
- | CFG_CMD_DHCP \
- | CFG_CMD_IMMAP \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -139,7 +150,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -223,7 +234,7 @@
#endif
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -248,18 +259,18 @@
#define CFG_LSRT 0x0F
#define CFG_MPTPR 0x4000
-#define CFG_PSDRAM_BR CFG_SDRAM_BASE | 0x00000041
+#define CFG_PSDRAM_BR (CFG_SDRAM_BASE | 0x00000041)
#define CFG_PSDRAM_OR 0xFC0028C0
-#define CFG_LSDRAM_BR CFG_LSDRAM_BASE | 0x00001861
+#define CFG_LSDRAM_BR (CFG_LSDRAM_BASE | 0x00001861)
#define CFG_LSDRAM_OR 0xFF803480
-#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00000801)
#define CFG_OR0_PRELIM 0xFFE00856
-#define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801
+#define CFG_BR5_PRELIM (CFG_EEPROM | 0x00000801)
#define CFG_OR5_PRELIM 0xFFFF03F6
-#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00001801
+#define CFG_BR6_PRELIM (CFG_FLSIMM_BASE | 0x00001801)
#define CFG_OR6_PRELIM 0xFF000856
-#define CFG_BR7_PRELIM CFG_BCSR | 0x00000801
+#define CFG_BR7_PRELIM (CFG_BCSR | 0x00000801)
#define CFG_OR7_PRELIM 0xFFFF83F6
#define CFG_RESET_ADDRESS 0xC0000000
diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h
index f163d003b9a..5ba8d1a7157 100644
--- a/include/configs/ZUMA.h
+++ b/include/configs/ZUMA.h
@@ -101,17 +101,29 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_MII /* enable MII commands */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BSP | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_DATE)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+
/*
* JFFS2 partitions
@@ -131,15 +143,12 @@
#define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
*/
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -349,7 +358,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index 35b6a519e32..e3f6e2c8b34 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -34,7 +34,9 @@
#define CONFIG_ACADIA 1 /* Board is Acadia */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
-#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
+/* Detect Acadia PLL input clock automatically via CPLD bit */
+#define CONFIG_SYS_CLK_FREQ ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \
+ 66666666 : 33333000)
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
@@ -73,7 +75,7 @@
#define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */
/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_ADDR 0xf8000000
#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
@@ -107,6 +109,7 @@
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
@@ -120,6 +123,10 @@
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#else
+#define CFG_NO_FLASH 1 /* No NOR on Acadia when NAND-booting */
+#endif
+
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
@@ -130,6 +137,63 @@
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 4k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ * On 440EPx the SPL is copied to SDRAM before the NAND controller is
+ * set up. While still running from cache, I experienced problems accessing
+ * the NAND controller. sr - 2006-08-25
+ */
+#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
+#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
+#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
+#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
+#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
+#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
+#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
+
+/*
+ * Now the NAND chip has to be defined (no autodetection used!)
+ */
+#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
+#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
+#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
+#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
+#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
+
+#define CFG_NAND_ECCSIZE 256
+#define CFG_NAND_ECCBYTES 3
+#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+#define CFG_NAND_OOBSIZE 16
+#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
+
+#ifdef CFG_ENV_IS_IN_NAND
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
+ */
+#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
+#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
+#endif
+
/*-----------------------------------------------------------------------
* RAM (CRAM)
*----------------------------------------------------------------------*/
@@ -207,7 +271,11 @@
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b ${fileaddr} fffc0000 ${filesize};" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
+ "nload=tftp 200000 acadia/u-boot-nand.bin\0" \
+ "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
+ "setenv filesize;saveenv\0" \
+ "nupd=run nload nupdate\0" \
"kozio=bootm ffc60000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -224,16 +292,6 @@
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
-#if 0 /* test-only */
-#define TEST_ONLY_NAND
-#endif
-
-#ifdef TEST_ONLY_NAND
-#define CMD_NAND CFG_CMD_NAND
-#else
-#define CMD_NAND 0
-#endif
-
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -241,27 +299,45 @@
#define CONFIG_SUPPORT_VFAT
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DTT | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CMD_NAND | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_USB)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_USB
+
+/*
+ * No NOR on Acadia when NAND-booting
+ */
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -270,7 +346,7 @@
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -300,7 +376,6 @@
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#ifdef TEST_ONLY_NAND
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
@@ -308,26 +383,29 @@
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
#endif
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
-#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
-
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_NAND_CS 3
/* Memory Bank 0 (Flash) initialization */
#define CFG_EBC_PB0AP 0x03337200
#define CFG_EBC_PB0CR 0xfe0bc000
+/* Memory Bank 3 (NAND-FLASH) initialization */
+#define CFG_EBC_PB3AP 0x018003c0
+#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
+
/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
/* Memory Bank 1 (CRAM) initialization */
#define CFG_EBC_PB1AP 0x030400c0
@@ -336,10 +414,24 @@
/* Memory Bank 2 (CRAM) initialization */
#define CFG_EBC_PB2AP 0x030400c0
#define CFG_EBC_PB2CR 0x020bc000
+#else
+#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
+/* Memory Bank 0 (NAND-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x018003c0
+#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
-/* Memory Bank 3 (NAND-FLASH) initialization */
-#define CFG_EBC_PB3AP 0x018003c0
-#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
+/*
+ * When NAND-booting the CRAM EBC setup must be done in sync mode, since the
+ * NAND-SPL already initialized the CRAM and EBC to sync mode.
+ */
+/* Memory Bank 1 (CRAM) initialization */
+#define CFG_EBC_PB1AP 0x9C0201C0
+#define CFG_EBC_PB1CR 0x000bc000
+
+/* Memory Bank 2 (CRAM) initialization */
+#define CFG_EBC_PB2AP 0x9C0201C0
+#define CFG_EBC_PB2CR 0x020bc000
+#endif
/* Memory Bank 4 (CPLD) initialization */
#define CFG_EBC_PB4AP 0x04006000
@@ -351,14 +443,15 @@
* GPIO Setup
*----------------------------------------------------------------------*/
#define CFG_GPIO_CRAM_CLK 8
-#define CFG_GPIO_CRAM_WAIT 9
+#define CFG_GPIO_CRAM_WAIT 9 /* GPIO-In */
#define CFG_GPIO_CRAM_ADV 10
-#define CFG_GPIO_CRAM_CRE (32 + 21)
+#define CFG_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */
/*-----------------------------------------------------------------------
* Definitions for GPIO_0 setup (PPC405EZ specific)
*
- * GPIO0[0-3] - External Bus Controller CS_4 - CS_7 Outputs
+ * GPIO0[0-2] - External Bus Controller CS_4 - CS_6 Outputs
+ * GPIO0[3] - NAND FLASH Controller CE3 (NFCE3) Output
* GPIO0[4] - External Bus Controller Hold Input
* GPIO0[5] - External Bus Controller Priority Input
* GPIO0[6] - External Bus Controller HLDA Output
@@ -374,12 +467,12 @@
* GPIO0[28-30] - Trace Outputs / PWM Inputs
* GPIO0[31] - PWM_8 I/O
*/
-#define CFG_GPIO0_TCR 0xC0000000
-#define CFG_GPIO0_OSRL 0x50000000
-#define CFG_GPIO0_OSRH 0x00000055
-#define CFG_GPIO0_ISR1L 0x00000000
+#define CFG_GPIO0_TCR 0xC0A00000
+#define CFG_GPIO0_OSRL 0x50004400
+#define CFG_GPIO0_OSRH 0x02000055
+#define CFG_GPIO0_ISR1L 0x00001000
#define CFG_GPIO0_ISR1H 0x00000055
-#define CFG_GPIO0_TSRL 0x00000000
+#define CFG_GPIO0_TSRL 0x02000000
#define CFG_GPIO0_TSRH 0x00000055
/*-----------------------------------------------------------------------
@@ -396,13 +489,13 @@
* GPIO1[16] - SPI_SS_1_N Output
* GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
*/
-#define CFG_GPIO1_OSRH 0x55455555
+#define CFG_GPIO1_TCR 0xFFFF8414
#define CFG_GPIO1_OSRL 0x40000110
-#define CFG_GPIO1_ISR1H 0x00000000
+#define CFG_GPIO1_OSRH 0x55455555
#define CFG_GPIO1_ISR1L 0x15555445
-#define CFG_GPIO1_TSRH 0x00000000
+#define CFG_GPIO1_ISR1H 0x00000000
#define CFG_GPIO1_TSRL 0x00000000
-#define CFG_GPIO1_TCR 0xFFFF8014
+#define CFG_GPIO1_TSRH 0x00000000
/*
* Internal Definitions
@@ -412,7 +505,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
new file mode 100644
index 00000000000..22eac1b4b95
--- /dev/null
+++ b/include/configs/ads5121.h
@@ -0,0 +1,401 @@
+/*
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * ADS5121 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DEBUG
+#undef DEBUG
+
+/*
+ * Memory map for the ADS5121 board:
+ *
+ * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
+ * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
+ * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
+ * 0x8200_0000 - 0x8200_001F CPLD (32 B)
+ * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+#define CONFIG_MPC512X 1 /* MPC512X family */
+
+#undef CONFIG_PCI
+
+#define CFG_MPC512X_CLKIN 66000000 /* in Hz */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
+
+#define CFG_IMMR 0x80000000
+
+#define CFG_MEMTEST_START 0x00200000 /* memtest region */
+#define CFG_MEMTEST_END 0x00400000
+
+/*
+ * DDR Setup - manually set all parameters as there's no SPD etc.
+ */
+#define CFG_DDR_SIZE 256 /* MB */
+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+
+/* DDR Controller Configuration
+ *
+ * SYS_CFG:
+ * [31:31] MDDRC Soft Reset: Diabled
+ * [30:30] DRAM CKE pin: Enabled
+ * [29:29] DRAM CLK: Enabled
+ * [28:28] Command Mode: Enabled (For initialization only)
+ * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
+ * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
+ * [20:19] Read Test: DON'T USE
+ * [18:18] Self Refresh: Enabled
+ * [17:17] 16bit Mode: Disabled
+ * [16:13] Ready Delay: 2
+ * [12:12] Half DQS Delay: Disabled
+ * [11:11] Quarter DQS Delay: Disabled
+ * [10:08] Write Delay: 2
+ * [07:07] Early ODT: Disabled
+ * [06:06] On DIE Termination: Disabled
+ * [05:05] FIFO Overflow Clear: DON'T USE here
+ * [04:04] FIFO Underflow Clear: DON'T USE here
+ * [03:03] FIFO Overflow Pending: DON'T USE here
+ * [02:02] FIFO Underlfow Pending: DON'T USE here
+ * [01:01] FIFO Overlfow Enabled: Enabled
+ * [00:00] FIFO Underflow Enabled: Enabled
+ * TIME_CFG0
+ * [31:16] DRAM Refresh Time: 0 CSB clocks
+ * [15:8] DRAM Command Time: 0 CSB clocks
+ * [07:00] DRAM Precharge Time: 0 CSB clocks
+ * TIME_CFG1
+ * [31:26] DRAM tRFC:
+ * [25:21] DRAM tWR1:
+ * [20:17] DRAM tWRT1:
+ * [16:11] DRAM tDRR:
+ * [10:05] DRAM tRC:
+ * [04:00] DRAM tRAS:
+ * TIME_CFG2
+ * [31:28] DRAM tRCD:
+ * [27:23] DRAM tFAW:
+ * [22:19] DRAM tRTW1:
+ * [18:15] DRAM tCCD:
+ * [14:10] DRAM tRTP:
+ * [09:05] DRAM tRP:
+ * [04:00] DRAM tRPA
+ */
+
+#define CFG_MDDRC_SYS_CFG 0xF8604200
+#define CFG_MDDRC_SYS_CFG_RUN 0xE8604200
+#define CFG_MDDRC_SYS_CFG_EN 0x30000000
+#define CFG_MDDRC_TIME_CFG0 0x0000281E
+#define CFG_MDDRC_TIME_CFG0_RUN 0x01F4281E
+#define CFG_MDDRC_TIME_CFG1 0x54EC1168
+#define CFG_MDDRC_TIME_CFG2 0x35210864
+
+#define CFG_MICRON_NOP 0x01380000
+#define CFG_MICRON_PCHG_ALL 0x01100400
+#define CFG_MICRON_MR 0x01000022
+#define CFG_MICRON_EM2 0x01020000
+#define CFG_MICRON_EM3 0x01030000
+#define CFG_MICRON_EN_DLL 0x01010000
+#define CFG_MICRON_RST_DLL 0x01000932
+#define CFG_MICRON_RFSH 0x01080000
+#define CFG_MICRON_INIT_DEV_OP 0x01000832
+#define CFG_MICRON_OCD_DEFAULT 0x01010780
+#define CFG_MICRON_OCD_EXIT 0x01010400
+
+/* DDR Priority Manager Configuration */
+#define CFG_MDDRCGRP_PM_CFG1 0x000777AA
+#define CFG_MDDRCGRP_PM_CFG2 0x00000055
+#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000
+#define CFG_MDDRCGRP_LUT0_MU 0x11111117
+#define CFG_MDDRCGRP_LUT0_ML 0x7777777A
+#define CFG_MDDRCGRP_LUT1_MU 0x4444EEEE
+#define CFG_MDDRCGRP_LUT1_ML 0xEEEEEEEE
+#define CFG_MDDRCGRP_LUT2_MU 0x44444444
+#define CFG_MDDRCGRP_LUT2_ML 0x44444444
+#define CFG_MDDRCGRP_LUT3_MU 0x55555555
+#define CFG_MDDRCGRP_LUT3_ML 0x55555558
+#define CFG_MDDRCGRP_LUT4_MU 0x11111111
+#define CFG_MDDRCGRP_LUT4_ML 0x1111117C
+#define CFG_MDDRCGRP_LUT0_AU 0x33333377
+#define CFG_MDDRCGRP_LUT0_AL 0x7777EEEE
+#define CFG_MDDRCGRP_LUT1_AU 0x11111111
+#define CFG_MDDRCGRP_LUT1_AL 0x11111111
+#define CFG_MDDRCGRP_LUT2_AU 0x11111111
+#define CFG_MDDRCGRP_LUT2_AL 0x11111111
+#define CFG_MDDRCGRP_LUT3_AU 0x11111111
+#define CFG_MDDRCGRP_LUT3_AL 0x11111111
+#define CFG_MDDRCGRP_LUT4_AU 0x11111111
+#define CFG_MDDRCGRP_LUT4_AL 0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI /* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */
+#define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */
+#define CFG_FLASH_USE_BUFFER_WRITE
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+
+/*
+ * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
+ * window is 64KB
+ */
+#define CFG_CPLD_BASE 0x82000000
+#define CFG_CPLD_SIZE 0x00010000 /* 64 KB */
+
+#define CFG_SRAM_BASE 0x30000000
+#define CFG_SRAM_SIZE 0x00020000 /* 128 KB */
+
+#define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
+#define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
+
+/* Use SRAM for initial stack */
+#define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */
+#define CFG_INIT_RAM_END CFG_SRAM_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
+#if CONFIG_PSC_CONSOLE != 3
+#error CONFIG_PSC_CONSOLE must be 3
+#endif
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#if 0
+#define CFG_I2C_NOPROBES {{0,0x69}} * Don't probe these addrs */
+#endif
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC 1
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR 0x1
+#define CONFIG_MII 1 /* MII PHY management */
+
+#if 0
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+#endif
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+/* This has to be a multiple of the Flash sector size */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_ENV_SIZE 0x2000
+#define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+/*
+ * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
+ * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
+ * to 0xFFFF, watchdog timeouts after about 64s. For details refer
+ * to chapter 36 of the MPC5121e Reference Manual.
+ */
+#define CONFIG_WATCHDOG /* enable watchdog */
+#define CFG_WATCHDOG_VALUE 0xFFFF
+
+ /*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#ifdef CONFIG_CMD_KGDB
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#ifdef CONFIG_CMD_KGDB
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CFG_HID2 HID2_HBE
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_HOSTNAME ads5121
+#define CONFIG_BOOTFILE uImage
+
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "load=tftp 200000 /tftpboot/ads5121/u-boot.bin\0" \
+ "update=protect off FFF00000 +${filesize};" \
+ "era FFF00000 +${filesize};cp.b 200000 FFF00000 ${filesize}\0" \
+ "upd=run load;run update\0" \
+ ""
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h
index c4108912a6b..703d3124e6f 100644
--- a/include/configs/adsvix.h
+++ b/include/configs/adsvix.h
@@ -68,10 +68,28 @@
#define CONFIG_DOS_PARTITION 1
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_NET) | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_IDE | CFG_CMD_PCMCIA)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PCMCIA
+
+#undef CONFIG_CMD_NET
+
#undef CONFIG_SHOW_BOOT_PROGRESS
@@ -162,7 +180,7 @@
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
/* #define CONFIG_INITRD_TAG 1 */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/aev.h b/include/configs/aev.h
index 8d9f0a16610..5bab793e9cc 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -44,11 +44,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -91,34 +86,42 @@
CFG_POST_I2C)
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#else
-#define CFG_CMD_POST_DIAG 0
#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- ADD_BMP_CMD | \
- CFG_CMD_PCI | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
+#ifdef CONFIG_POST
+#define CONFIG_CMD_DIAG
+#endif
+
#define CONFIG_TIMESTAMP /* display image timestamps */
@@ -166,17 +169,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@@ -324,7 +327,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -343,9 +346,13 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -362,7 +369,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index 67f62d3dfbe..d88c3ad43b0 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -29,6 +29,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_ALPR 1 /* Board is ebony */
#define CONFIG_440GX 1 /* Specifc GX support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
@@ -94,7 +95,7 @@
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -209,25 +210,37 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_FPGA | \
- CFG_CMD_NAND | \
- CFG_CMD_REGINFO)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -236,7 +249,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -256,7 +269,7 @@
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
@@ -274,7 +287,6 @@
#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_MASTER_INIT
@@ -358,7 +370,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h
index 9a1c5596b7a..73a88854b38 100644
--- a/include/configs/armadillo.h
+++ b/include/configs/armadillo.h
@@ -71,12 +71,21 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL) /* | CFG_CMD_JFFS2)*/
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200"
diff --git a/include/configs/assabet.h b/include/configs/assabet.h
index 1a69ebe0dae..226ad54723e 100644
--- a/include/configs/assabet.h
+++ b/include/configs/assabet.h
@@ -66,18 +66,30 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp"
#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
#define CFG_AUTOLOAD "n" /* No autoload */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 8fad55d81cf..a65c5f3422f 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -97,18 +97,31 @@
#define CONFIG_BOOTDELAY 3
/* #define CONFIG_ENV_OVERWRITE 1 */
-#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | CFG_CMD_MII |\
- CFG_CMD_DHCP ) & \
- ~(CFG_CMD_BDI | \
- CFG_CMD_IMI | \
- CFG_CMD_AUTOSCRIPT | \
- CFG_CMD_FPGA | \
- CFG_CMD_MISC | \
- CFG_CMD_LOADS ))
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DHCP
+
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_LOADS
+
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
@@ -150,6 +163,11 @@
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_AT91C_USE_RMII
+/* AC Characteristics */
+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS (0xC << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+
#define CONFIG_HAS_DATAFLASH 1
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
#define CFG_MAX_DATAFLASH_BANKS 2
diff --git a/include/configs/atc.h b/include/configs/atc.h
index bf6c1709d90..3ff4b68083a 100644
--- a/include/configs/atc.h
+++ b/include/configs/atc.h
@@ -64,9 +64,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#undef CONFIG_ETHER_NONE /* define if ether on something else */
@@ -124,27 +122,37 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_PCI | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_DATE | \
- CFG_CMD_IDE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_DOS_PARTITION
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_IDE
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+#define CONFIG_DOS_PARTITION
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -285,7 +293,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index beaf3851dc8..75b153e4a85 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -108,47 +108,29 @@
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#define CONFIG_NET_MULTI 1
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_SUBNETMASK \
- | CONFIG_BOOTP_GATEWAY)
-
-#define CONFIG_COMMANDS (CFG_CMD_BDI \
- | CFG_CMD_LOADS \
- | CFG_CMD_LOADB \
- | CFG_CMD_IMI \
- /* | CFG_CMD_CACHE */ \
- | CFG_CMD_FLASH \
- | CFG_CMD_MEMORY \
- | CFG_CMD_NET \
- | CFG_CMD_ENV \
- /* | CFG_CMD_IRQ */ \
- | CFG_CMD_BOOTD \
- | CFG_CMD_CONSOLE \
- /* | CFG_CMD_EEPROM */ \
- | CFG_CMD_ASKENV \
- | CFG_CMD_RUN \
- | CFG_CMD_ECHO \
- /* | CFG_CMD_I2C */ \
- | CFG_CMD_REGINFO \
- /* | CFG_CMD_DATE */ \
- | CFG_CMD_DHCP \
- /* | CFG_CMD_AUTOSCRIPT */ \
- /* | CFG_CMD_MII */ \
- | CFG_CMD_MISC \
- /* | CFG_CMD_SDRAM */ \
- /* | CFG_CMD_DIAG */ \
- /* | CFG_CMD_HWFLOW */ \
- /* | CFG_CMD_SAVES */ \
- /* | CFG_CMD_SPI */ \
- /* | CFG_CMD_PING */ \
- | CFG_CMD_MMC \
- | CFG_CMD_FAT \
- | CFG_CMD_IMLS \
- /* | CFG_CMD_ITEST */ \
- | CFG_CMD_EXT2 \
- | CFG_CMD_JFFS2 \
- )
-
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
#define CONFIG_ATMEL_USART 1
#define CONFIG_MACB 1
@@ -201,10 +183,9 @@
#define CFG_LONGHELP 1
#define CFG_MEMTEST_START \
- ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; })
+ ({ gd->bd->bi_dram[0].start; })
#define CFG_MEMTEST_END \
({ \
- DECLARE_GLOBAL_DATA_PTR; \
gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \
})
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index db58a9fa74a..14c563808bb 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -32,6 +32,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
@@ -50,7 +51,7 @@
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
@@ -73,9 +74,9 @@
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
-#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
+#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (4 << 10)
-#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -104,21 +105,18 @@
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH or EEPROM).
- * Note: DENX encourages to use redundant environment in FLASH.
- */
-#if 1
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
-#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
+#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
#endif
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
-#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
+#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
+#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
@@ -128,12 +126,12 @@
#define CFG_FLASH_ADDR1 0x2aa
#define CFG_FLASH_WORD_SIZE unsigned char
-#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
-#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
+#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
+#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
@@ -141,22 +139,91 @@
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 4k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ * On 440EPx the SPL is copied to SDRAM before the NAND controller is
+ * set up. While still running from cache, I experienced problems accessing
+ * the NAND controller. sr - 2006-08-25
+ */
+#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
+#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
+#define CFG_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
+#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
+#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
+#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
+#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
+
+/*
+ * Now the NAND chip has to be defined (no autodetection used!)
+ */
+#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
+#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
+#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
+#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
+#define CFG_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
+
+#define CFG_NAND_ECCSIZE 256
+#define CFG_NAND_ECCBYTES 3
+#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+#define CFG_NAND_OOBSIZE 16
+#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
+
+#ifdef CFG_ENV_IS_IN_NAND
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
+ */
+#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
+#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
+#endif
+
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
-#define CFG_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
-#define CFG_NAND_CS 1
+#define CFG_MAX_NAND_DEVICE 2
+#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE, CFG_NAND_ADDR + 2 }
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_NAND_CS 1
+#else
+#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
+/* Memory Bank 0 (NAND-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x018003c0
+#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
+#endif
+
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------------- */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
#undef CONFIG_DDR_ECC /* don't use ECC */
#define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
-#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
+#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
+#define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
+#define CONFIG_PROG_SDRAM_TLB
+#undef CFG_DRAM_TEST
/*-----------------------------------------------------------------------
* I2C
@@ -251,45 +318,55 @@
#define USB_2_0_DEVICE
#endif /*CONFIG_440EP*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_SNTP
+
#ifdef CONFIG_BAMBOO_NAND
-#define _CFG_CMD_NAND CFG_CMD_NAND
-#else
-#define _CFG_CMD_NAND 0
-#endif /* CONFIG_BAMBOO_NAND */
+#define CONFIG_CMD_NAND
+#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_USB | \
- CFG_CMD_FAT | \
- CFG_CMD_EXT2 | \
- _CFG_CMD_NAND | \
- CFG_CMD_SNTP )
#define CONFIG_SUPPORT_VFAT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -324,7 +401,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
@@ -343,7 +419,7 @@
*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -355,7 +431,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/barco.h b/include/configs/barco.h
index 624fa1d6e28..0bb446f7844 100644
--- a/include/configs/barco.h
+++ b/include/configs/barco.h
@@ -70,22 +70,30 @@
#define CONFIG_BOOTARGS "mem=32M"
-/* Add support for a few extra bootp options like:
- * - File size
- * - DNS
+
+/*
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE | \
- CONFIG_BOOTP_DNS)
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PCI
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_PCI )
+#undef CONFIG_CMD_NET
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */
#define CONFIG_BOOTDELAY 1
@@ -110,7 +118,6 @@
*/
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP
-#undef CFG_CMD_NET
#define PCI_ENET0_IOADDR 0x80000000
#define PCI_ENET0_MEMADDR 0x80000000
@@ -340,7 +347,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index 65dfc815548..6cb6bc4f71c 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -97,19 +97,31 @@
#define CONFIG_LOADS_ECHO 1
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PING | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_DATE)
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_DATE
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"
#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 79a1404a40d..cce6ef79f27 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -240,23 +240,6 @@
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
-#if (CONFIG_DRIVER_SMC91111)
-#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \
- CFG_CMD_PING | \
- CFG_CMD_ELF | \
- CFG_CMD_CACHE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DATE)
-
-#else
-#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \
- CFG_CMD_ELF | \
- CFG_CMD_CACHE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DATE)
-#endif
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#if (CONFIG_DRIVER_SMC91111)
@@ -305,20 +288,39 @@
#endif
#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+
+#if (CONFIG_DRIVER_SMC91111)
+#define CONFIG_CMD_PING
+#endif
+
#if (CONFIG_SOFT_I2C)
-#define CONFIG_COMMANDS2 CFG_CMD_I2C
-#else
-#define CONFIG_COMMANDS2 0
-#endif /* CONFIG_SOFT_I2C */
+#define CONFIG_CMD_I2C
+#endif
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
-#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 | CFG_CMD_DHCP)
-#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2)
+#define CONFIG_CMD_DHCP
#endif
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Console settings
@@ -345,7 +347,7 @@
#endif
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -395,7 +397,7 @@
/* Enabled below option for CF support */
/* #define CONFIG_STAMP_CF 1 */
-#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(CONFIG_STAMP_CF) && defined(CONFIG_CMD_IDE)
#define CONFIG_MISC_INIT_R 1
#define CONFIG_DOS_PARTITION 1
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index f6755acf694..b9a9e3cb792 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -144,11 +144,8 @@
#endif
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
-#else
-#define CFG_CMD_POST_DIAG 0
#endif
/* CF-CARD IDE-HDD Support */
@@ -159,51 +156,65 @@
#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
# define CONFIG_BFIN_IDE 1
-# define ADD_IDE_CMD CFG_CMD_IDE
-#else
-# define ADD_IDE_CMD 0
#endif
/*#define CONFIG_BF537_NAND */ /* Add nand flash support */
-#ifdef CONFIG_BF537_NAND
-# define ADD_NAND_CMD CFG_CMD_NAND
-#else
-# define ADD_NAND_CMD 0
-#endif
-
#define CONFIG_NETCONSOLE 1
#define CONFIG_NET_MULTI 1
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+
#if (BFIN_CPU == ADSP_BF534)
-#define CONFIG_BFIN_CMD (CONFIG_CMD_DFL & ~CFG_CMD_NET)
+#undef CONFIG_CMD_NET
#else
-#define CONFIG_BFIN_CMD (CONFIG_CMD_DFL | CFG_CMD_PING)
+#define CONFIG_CMD_PING
+#endif
+
+#if defined(CONFIG_BFIN_CF_IDE) \
+ || defined(CONFIG_BFIN_HDD_IDE) \
+ || defined(CONFIG_BFIN_TRUE_IDE)
+#define CONFIG_CMD_IDE
+#endif
+
#endif
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
-#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_CACHE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DHCP | \
- ADD_IDE_CMD | \
- ADD_NAND_CMD | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_DATE)
-#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
-#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_CACHE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_EEPROM | \
- ADD_IDE_CMD | \
- CFG_CMD_DATE)
+
+#define CONFIG_CMD_DHCP
+
+#if defined(CONFIG_POST)
+#define CONFIG_CMD_DIAG
#endif
+#ifdef CONFIG_BF537_NAND
+#define CONFIG_CMD_NAND
+#endif
+
+#endif
+
+
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
#define CONFIG_LOADADDR 0x1000000
@@ -256,9 +267,6 @@
#endif
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
#if (BFIN_CPU == ADSP_BF534)
#define CFG_PROMPT "serial_bf534> " /* Monitor Command Prompt */
@@ -277,7 +285,7 @@
#endif
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 8d826faaa0d..29662604f99 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -164,12 +164,6 @@
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
#if (CONFIG_DRIVER_SMC91111)
-#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \
- CFG_CMD_PING | \
- CFG_CMD_ELF | \
- CFG_CMD_CACHE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_DHCP)
#define CONFIG_EXTRA_ENV_SETTINGS \
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
@@ -186,20 +180,36 @@
"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
""
#else
-#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \
- CFG_CMD_ELF | \
- CFG_CMD_CACHE | \
- CFG_CMD_JFFS2)
#define CONFIG_EXTRA_ENV_SETTINGS \
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
"flashboot=bootm 0x20100000\0" \
""
#endif
-#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_JFFS2
+
+#if defined(CONFIG_DRIVER_SMC91111)
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#endif
+
/*
* Console settings
@@ -208,7 +218,7 @@
#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index 10c48143117..7736a1e32d0 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -137,25 +137,37 @@
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_CACHE | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -166,7 +178,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -219,7 +231,7 @@
#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
-#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
+#if defined(CONFIG_CMD_EEPROM)
#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
#endif
@@ -314,7 +326,7 @@
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -426,7 +438,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h
index ae75539c37a..a9a52547756 100644
--- a/include/configs/c2mon.h
+++ b/include/configs/c2mon.h
@@ -68,7 +68,15 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -77,15 +85,18 @@
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -98,7 +109,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -174,7 +185,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index 2c160a44891..d577b95e05d 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -38,11 +38,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
#define CONFIG_BOARD_EARLY_INIT_R
/*
@@ -52,21 +47,30 @@
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IMMAP | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
/*
* MUST be low boot - HIGHBOOT is not supported anymore
@@ -111,7 +115,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* Flash configuration, expect one 16 Megabyte Bank at most
@@ -181,7 +185,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -199,6 +203,11 @@
#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h
index 6997c7a6f43..e06735da631 100644
--- a/include/configs/cerf250.h
+++ b/include/configs/cerf250.h
@@ -61,10 +61,21 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_ETHADDR 00:D0:CA:F1:3C:D2
@@ -75,7 +86,7 @@
#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400"
#define CONFIG_CMDLINE_TAG
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h
index 5947c2a3193..ae40b358e95 100644
--- a/include/configs/cm4008.h
+++ b/include/configs/cm4008.h
@@ -58,10 +58,23 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-#undef CONFIG_COMMANDS
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV))
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_ENV
+
#define CONFIG_BOOTDELAY 0
#define CONFIG_BOOTARGS "mem=16M console=ttyAM0,115200"
diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h
index e62fc06337b..c1dd33d1d25 100644
--- a/include/configs/cm41xx.h
+++ b/include/configs/cm41xx.h
@@ -58,10 +58,23 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-#undef CONFIG_COMMANDS
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV))
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_ENV
+
#define CONFIG_BOOTDELAY 0
#define CONFIG_BOOTARGS "mem=32M console=ttyAM0,115200"
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
new file mode 100644
index 00000000000..d554348021f
--- /dev/null
+++ b/include/configs/cm5200.h
@@ -0,0 +1,338 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_CM5200 1 /* ... on CM5200 platform */
+
+/*
+ * Supported commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_PHY_ADDR 0x00
+#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */
+/* use misc_init_r() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */
+#define CONFIG_MISC_INIT_R 1
+#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */
+
+/*
+ * POST support
+ */
+#define CONFIG_POST (CFG_POST_MEMORY | CFG_POST_CPU | CFG_POST_I2C)
+#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
+/* List of I2C addresses to be verified by POST */
+#define I2C_ADDR_LIST { CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM }
+
+/* display image timestamps */
+#define CONFIG_TIMESTAMP 1
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
+ "echo"
+#undef CONFIG_BOOTARGS
+
+/*
+ * Default environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "netmask=255.255.0.0\0" \
+ "ipaddr=192.168.160.33\0" \
+ "serverip=192.168.1.1\0" \
+ "gatewayip=192.168.1.1\0" \
+ "console=ttyPSC0\0" \
+ "u-boot_addr=100000\0" \
+ "kernel_addr=200000\0" \
+ "kernel_addr_flash=fc0c0000\0" \
+ "fdt_addr=400000\0" \
+ "fdt_addr_flash=fc0a0000\0" \
+ "ramdisk_addr=500000\0" \
+ "rootpath=/opt/eldk-4.1/ppc_6xx\0" \
+ "u-boot=/tftpboot/cm5200/u-boot.bin\0" \
+ "bootfile_fdt=/tftpboot/cm5200/uImage\0" \
+ "fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \
+ "load=tftp ${u-boot_addr} ${u-boot}\0" \
+ "update=prot off fc000000 +${filesize}; " \
+ "era fc000000 +${filesize}; " \
+ "cp.b ${u-boot_addr} fc000000 ${filesize}; " \
+ "prot on fc000000 +${filesize}\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \
+ "addcons=setenv bootargs ${bootargs} " \
+ "console=${console},${baudrate}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off panic=1\0" \
+ "flash_flash=run flashargs addinit addip addcons;" \
+ "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \
+ "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \
+ "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \
+ "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_flash"
+
+/*
+ * Low level configuration
+ */
+
+/*
+ * Clock configuration
+ */
+#define CFG_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */
+#define CFG_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR 0xF0000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_DEFAULT_MBAR 0x80000000
+
+#define CFG_LOWBOOT 1
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#endif
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_BOARD_TYPES 1 /* we use board_type */
+
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
+#define CFG_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#define CFG_FLASH_BASE 0xfc000000
+/* we need these despite using CFI */
+#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
+#define CFG_FLASH_SIZE 0x02000000 /* 32 MiB */
+
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT 1
+#undef CFG_LOWBOOT
+#endif
+
+
+/*
+ * Chip selects configuration
+ */
+/* Boot Chipselect */
+#define CFG_BOOTCS_START CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */
+/* use board_early_init_r to enable flash write in CS_BOOT */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/* Flash memory addressing */
+#define CFG_CS0_START CFG_FLASH_BASE
+#define CFG_CS0_SIZE CFG_FLASH_SIZE
+
+/* No burst, dead cycle = 1 for CS0 (Flash) */
+#define CFG_CS_BURST 0x00000000
+#define CFG_CS_DEADCYCLE 0x00000001
+
+/*
+ * SDRAM configuration
+ * settings for k4s561632E-xx75, assuming XLB = 132 MHz
+ */
+#define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */
+#define SDRAM_CONTROL 0x514F0000
+#define SDRAM_CONFIG1 0xE2333900
+#define SDRAM_CONFIG2 0x8EE70000
+
+/*
+ * MTD configuration
+ */
+#define CONFIG_JFFS2_CMDLINE 1
+#define MTDIDS_DEFAULT "nor0=cm5200-0"
+#define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \
+ "384k(uboot),128k(env)," \
+ "128k(redund_env),128k(dtb)," \
+ "2m(kernel),27904k(rootfs)," \
+ "-(config)"
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_MODULE 2 /* Select I2C module #2 */
+#define CFG_I2C_SPEED 40000 /* 40 kHz */
+#define CFG_I2C_SLAVE 0x0
+#define CFG_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */
+#define CFG_I2C_EEPROM 0x53 /* I2C EEPROM device address */
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
+
+/*
+ * USB configuration
+ */
+#define CONFIG_USB_OHCI 1
+#define CONFIG_USB_STORAGE 1
+#define CONFIG_USB_CLOCK 0x0001BBBB
+#define CONFIG_USB_CONFIG 0x00001000
+/* Partitions (for USB) */
+#define CONFIG_MAC_PARTITION 1
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_ISO_PARTITION 1
+
+/*
+ * Invoke our last_stage_init function - needed by fwupdate
+ */
+#define CONFIG_LAST_STAGE_INIT 1
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 0x10000
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+/* Configuration of redundant environment */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+/*
+ * Pin multiplexing configuration
+ */
+
+/*
+ * CS1/GPIO_WKUP_6: GPIO (default)
+ * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
+ * IRDA/PSC6: UART
+ * Ether: Ethernet 100Mbit with MD
+ * PCI_DIS: PCI controller disabled
+ * USB: USB
+ * PSC3: SPI with UART3
+ * PSC2: UART
+ * PSC1: UART
+ */
+#define CFG_GPS_PORT_CONFIG 0x10559C44
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP 1 /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_ALT_MEMTEST 1
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */
+
+#define CONFIG_LOOPW 1
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_XLB_PIPELINING 1 /* enable transaction pipeling */
+
+/*
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#ifdef CONFIG_CMD_KGDB
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Flat Device Tree support
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define OF_CPU "PowerPC,5200@0"
+#define OF_SOC "soc5200@f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index 572a70f1200..f32c8c2c66b 100644
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -104,35 +104,44 @@
#define CFG_I2C_EEPROM_ADDR 0x50
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_I2C_EEPROM_ADDR_OVERFLOW
+#else
+#define CONFIG_TIMESTAMP
#endif
/* still about 20 kB free with this defined */
#define CFG_LONGHELP
#define CONFIG_BOOTDELAY 1
-#ifdef CONFIG_HARD_I2C
-#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP ) & \
- ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
-#else
-#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP ) & \
- ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
-#define CONFIG_TIMESTAMP
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+
+#if defined(CONFIG_HARD_I2C)
+ #define CONFIG_CMD_DATE
+ #define CONFIG_CMD_EEPROM
+ #define CONFIG_CMD_I2C
#endif
-#define CFG_LONGHELP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+#define CFG_LONGHELP
#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h
index e4599192941..a869364c605 100644
--- a/include/configs/cmi_mpc5xx.h
+++ b/include/configs/cmi_mpc5xx.h
@@ -44,13 +44,35 @@
#define CONFIG_BAUDRATE 57600
-#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \
- CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ASKENV | \
- CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_ENV | CFG_CMD_RUN | \
- CFG_CMD_IMI)
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NET /* disabeled - causes compile errors */
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_IMI
+
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
@@ -73,7 +95,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -149,8 +171,9 @@
#define CFG_ENV_IS_IN_FLASH 1
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
-#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */
+#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
+#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#endif
/*-----------------------------------------------------------------------
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 9033fa88ed1..104d94ec141 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -65,8 +65,10 @@
* Enable use of Ethernet
* ---
*/
+#define CONFIG_MCFFEC
-#define FEC_ENET
+/* Enable Dma Timer */
+#define CONFIG_MCFTMR
/* ---
* Define baudrate for UART1 (console output, tftp, ...)
@@ -76,6 +78,8 @@
* ---
*/
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
@@ -130,16 +134,47 @@
#define CFG_ENV_IS_IN_FLASH 1
#endif
-/* ---
- * Define which commmands should be available at u-boot command prompt
- * ---
+
+/*
+ * BOOTP options
*/
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | CFG_CMD_PING & ~(CFG_CMD_LOADS | \
-CFG_CMD_LOADB) | CFG_CMD_MII)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_MII
+
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
/*
*-----------------------------------------------------------------------------
@@ -184,7 +219,7 @@ from which user programs will be started */
#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h
index aea2e64365a..84d50c71dd5 100644
--- a/include/configs/cogent_mpc8260.h
+++ b/include/configs/cogent_mpc8260.h
@@ -71,8 +71,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -88,10 +87,25 @@
#define CONFIG_BAUDRATE 9600
#endif
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL|CFG_CMD_KGDB)&~CFG_CMD_NET)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_KGDB
+
+#undef CONFIG_CMD_NET
+
#ifdef DEBUG
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
@@ -102,7 +116,7 @@
#define CONFIG_BOOTARGS "root=/dev/ram rw"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -124,7 +138,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -256,7 +270,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
#endif
diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h
index 80962d35fdf..ce38af1dd85 100644
--- a/include/configs/cogent_mpc8xx.h
+++ b/include/configs/cogent_mpc8xx.h
@@ -59,10 +59,25 @@
#define CFG_I2C_SLAVE 0x7F
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_KGDB | CFG_CMD_I2C) & ~CFG_CMD_NET)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_KGDB
+#define CONFIG_CMD_I2C
+
+#undef CONFIG_CMD_NET
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
@@ -73,7 +88,7 @@
#define CONFIG_BOOTARGS "root=/dev/ram rw"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#define CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -88,7 +103,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -200,7 +215,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
index f9586fbcb94..ce4ea1f8dbe 100644
--- a/include/configs/cpci5200.h
+++ b/include/configs/cpci5200.h
@@ -50,11 +50,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -92,12 +87,6 @@
#define CONFIG_NS8382X 1
#endif
-#define ADD_PCI_CMD CFG_CMD_PCI
-
-#else /* MPC5100 */
-
-#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
-
#endif
/* Partitions */
@@ -107,28 +96,35 @@
/* USB */
#if 0
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
#endif
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_IDE | \
- CFG_CMD_I2C | \
- CFG_CMD_BSP | \
- CFG_CMD_ELF | \
- CFG_CMD_EXT2 | \
- CFG_CMD_DATE | \
- ADD_PCI_CMD )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_DATE
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CFG_LOWBOOT 1
@@ -179,7 +175,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
* I2C configuration
@@ -277,7 +273,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -295,6 +291,11 @@
#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/cradle.h b/include/configs/cradle.h
index 776e1d2b7f7..eb93a8f083f 100644
--- a/include/configs/cradle.h
+++ b/include/configs/cradle.h
@@ -61,10 +61,21 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200"
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
index f04102e95c5..0be0f219248 100644
--- a/include/configs/csb226.h
+++ b/include/configs/csb226.h
@@ -57,10 +57,34 @@
#define CONFIG_BAUDRATE 19200
#undef CONFIG_MISC_INIT_R /* not used yet */
-#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_DHCP|CFG_CMD_CACHE)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_CACHE
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0"
@@ -73,7 +97,7 @@
#define CONFIG_CMDLINE_TAG 1
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/csb272.h b/include/configs/csb272.h
index 27d64c1e434..c43b49737d9 100644
--- a/include/configs/csb272.h
+++ b/include/configs/csb272.h
@@ -73,30 +73,32 @@
#endif
/*
- * BOOTP/DHCP protocol configuration
- *
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_BOOTFILESIZE )
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS2
+
+
/*
- * U-Boot Monitor Command Line Functions Configuration
- *
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF | \
- CFG_CMD_IRQ | \
- CFG_CMD_I2C | \
- CFG_CMD_PCI | \
- CFG_CMD_DATE | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_DHCP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
/*
* Serial download configuration
@@ -109,7 +111,7 @@
* KGDB Configuration
*
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -125,7 +127,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/csb472.h b/include/configs/csb472.h
index 09d52ded9ee..a7120aa57f9 100644
--- a/include/configs/csb472.h
+++ b/include/configs/csb472.h
@@ -73,30 +73,31 @@
#endif
/*
- * BOOTP/DHCP protocol configuration
- *
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_BOOTFILESIZE )
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS2
+
+
/*
- * U-Boot Monitor Command Line Functions Configuration
- *
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF | \
- CFG_CMD_IRQ | \
- CFG_CMD_I2C | \
- CFG_CMD_PCI | \
- CFG_CMD_DATE | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_DHCP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
/*
* Serial download configuration
@@ -109,7 +110,7 @@
* KGDB Configuration
*
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -125,7 +126,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index 071d5b7f36c..976dae39f69 100644
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -99,20 +99,32 @@
#define CONFIG_BOOTDELAY 3
/* #define CONFIG_ENV_OVERWRITE 1 */
-#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING ) & \
- ~(CFG_CMD_BDI | \
- CFG_CMD_IMI | \
- CFG_CMD_AUTOSCRIPT | \
- CFG_CMD_FPGA | \
- CFG_CMD_MISC | \
- CFG_CMD_LOADS ))
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_LOADS
+
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
new file mode 100644
index 00000000000..8ecd0595a20
--- /dev/null
+++ b/include/configs/davinci_dvevm.h
@@ -0,0 +1,214 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * Define this to make U-Boot skip low level initialization when loaded
+ * by initial bootloader. Not required by NAND U-Boot version but IS
+ * required for a NOR version used to burn the real NOR U-Boot into
+ * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
+ * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
+ * NOR U-Boot is loaded directly from Flash so it must perform all the
+ * low level initialization itself. NAND version is loaded by an initial
+ * bootloader (UBL in TI-ese) that performs such an initialization so it's
+ * skipped in NAND version. The third DaVinci boot mode loads a bootloader
+ * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
+ * performing low level init prior to loading. All that means we can NOT use
+ * NAND version to put U-Boot into NOR because it doesn't have NOR support and
+ * we can NOT use NOR version because it performs low level initialization
+ * effectively destroying itself in DDR memory. That's why a separate NOR
+ * version with this define is needed. It is loaded via UART, then one uses
+ * it to somehow download a proper NOR version built WITHOUT this define to
+ * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
+ * NOR support into the initial bootloader so it won't be needed but DaVinci
+ * static RAM might be too small for this (I have something like 2Kbytes left
+ * as of now, without NOR support) so this might've not happened...
+ *
+#define CONFIG_NOR_UART_BOOT
+ */
+
+/*=======*/
+/* Board */
+/*=======*/
+#define DV_EVM
+#define CFG_NAND_SMALLPAGE
+#define CFG_USE_NOR
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
+#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
+#define CFG_HZ 1000
+/*====================================================*/
+/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
+/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
+/*====================================================*/
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_EEPROM_PAGE_WRITE_BITS 6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
+#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
+#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */
+#define DDR_8BANKS /* 8-bank DDR2 (256MB) */
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
+#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */
+#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/*===================*/
+/* I2C Configuration */
+/*===================*/
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+/*==================================*/
+/* Network & Ethernet Configuration */
+/*==================================*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#ifdef CFG_USE_NAND
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_NO_FLASH
+#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#ifdef CFG_NAND_SMALLPAGE
+#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */
+#define CFG_ENV_SIZE SZ_16K
+#else
+#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */
+#define CFG_ENV_SIZE SZ_128K
+#endif
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
+#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+#define CFG_NAND_BASE 0x02000000
+#define CFG_NAND_HW_ECC
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+#define DEF_BOOTM ""
+#elif defined(CFG_USE_NOR)
+#ifdef CONFIG_NOR_UART_BOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
+#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+#else
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#endif
+#define CFG_ENV_IS_IN_FLASH
+#undef CFG_NO_FLASH
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
+#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*3)
+#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
+#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
+#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
+#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
+#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
+#endif
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CFG_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR 0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2050000"
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#ifdef CFG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#elif defined(CFG_USE_NOR)
+#define CONFIG_CMD_JFFS2
+#else
+#error "Either CFG_USE_NAND or CFG_USE_NOR _MUST_ be defined !!!"
+#endif
+/*=======================*/
+/* KGDB support (if any) */
+/*=======================*/
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
new file mode 100644
index 00000000000..96c9a301478
--- /dev/null
+++ b/include/configs/davinci_schmoogie.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*=======*/
+/* Board */
+/*=======*/
+#define SCHMOOGIE
+#define CFG_NAND_LARGEPAGE
+#define CFG_USE_NAND
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
+#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
+#define CFG_HZ 1000
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
+#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
+#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
+#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
+#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */
+#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/*===================*/
+/* I2C Configuration */
+/*===================*/
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+/*==================================*/
+/* Network & Ethernet Configuration */
+/*==================================*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_NO_FLASH
+#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */
+#define CFG_ENV_SIZE SZ_128K
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
+#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+#define CFG_NAND_BASE 0x02000000
+#define CFG_NAND_HW_ECC
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+/*=====================*/
+/* Board related stuff */
+/*=====================*/
+#define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */
+#define CFG_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */
+#define CONFIG_HAS_UID
+#define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */
+#define CFG_UID_ADDR 0x50 /* UID chip I2C address */
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CFG_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR 0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_NAND
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+/*=======================*/
+/* KGDB support (if any) */
+/*=======================*/
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
new file mode 100644
index 00000000000..de8c4fac2b0
--- /dev/null
+++ b/include/configs/davinci_sonata.h
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * Define this to make U-Boot skip low level initialization when loaded
+ * by initial bootloader. Not required by NAND U-Boot version but IS
+ * required for a NOR version used to burn the real NOR U-Boot into
+ * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
+ * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
+ * NOR U-Boot is loaded directly from Flash so it must perform all the
+ * low level initialization itself. NAND version is loaded by an initial
+ * bootloader (UBL in TI-ese) that performs such an initialization so it's
+ * skipped in NAND version. The third DaVinci boot mode loads a bootloader
+ * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
+ * performing low level init prior to loading. All that means we can NOT use
+ * NAND version to put U-Boot into NOR because it doesn't have NOR support and
+ * we can NOT use NOR version because it performs low level initialization
+ * effectively destroying itself in DDR memory. That's why a separate NOR
+ * version with this define is needed. It is loaded via UART, then one uses
+ * it to somehow download a proper NOR version built WITHOUT this define to
+ * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
+ * NOR support into the initial bootloader so it won't be needed but DaVinci
+ * static RAM might be too small for this (I have something like 2Kbytes left
+ * as of now, without NOR support) so this might've not happened...
+ *
+#define CONFIG_NOR_UART_BOOT
+ */
+
+/*=======*/
+/* Board */
+/*=======*/
+#define SONATA_BOARD
+#define CFG_NAND_SMALLPAGE
+#define CFG_USE_NOR
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
+#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
+#define CFG_HZ 1000
+/*====================================================*/
+/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
+/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
+/*====================================================*/
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_EEPROM_PAGE_WRITE_BITS 6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
+#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
+#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
+#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
+#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */
+#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/*===================*/
+/* I2C Configuration */
+/*===================*/
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+/*==================================*/
+/* Network & Ethernet Configuration */
+/*==================================*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#ifdef CFG_USE_NAND
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_NO_FLASH
+#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */
+#define CFG_ENV_SIZE SZ_16K
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
+#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+#define CFG_NAND_BASE 0x02000000
+#define CFG_NAND_HW_ECC
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+#define DEF_BOOTM ""
+#elif defined(CFG_USE_NOR)
+#ifdef CONFIG_NOR_UART_BOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
+#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+#else
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#endif
+#define CFG_ENV_IS_IN_FLASH
+#undef CFG_NO_FLASH
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */
+#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*2)
+#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
+#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
+#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
+#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
+#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
+#endif
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CFG_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR 0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000"
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#ifdef CFG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#elif defined(CFG_USE_NOR)
+#define CONFIG_CMD_JFFS2
+#else
+#error "Either CFG_USE_NAND or CFG_USE_NOR _MUST_ be defined !!!"
+#endif
+/*=======================*/
+/* KGDB support (if any) */
+/*=======================*/
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 4cc5085293b..b2f606f498b 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -75,21 +75,57 @@
#ifdef CONFIG_DBAU1550
/* Boot from flash by default, revert to bootp */
#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
-
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_NET) & \
- ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FPGA | CFG_CMD_IDE | \
- CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_BDI | CFG_CMD_BEDBUG | \
- CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_PCMCIA | CFG_CMD_I2C))
#else /* CONFIG_DBAU1550 */
#define CONFIG_BOOTCOMMAND "bootp;bootm"
-
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP | CFG_CMD_ELF) & \
- ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
- CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | \
- CFG_CMD_ELF | CFG_CMD_BDI | CFG_CMD_BEDBUG))
#endif /* CONFIG_DBAU1550 */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_RUN
+
+
+#ifdef CONFIG_DBAU1550
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_NET
+
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_PCMCIA
+
+#else
+
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DHCP
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+#endif
+
/*
* Miscellaneous configurable options
diff --git a/include/configs/debris.h b/include/configs/debris.h
index 8ff963f55a2..7667e5e60e3 100644
--- a/include/configs/debris.h
+++ b/include/configs/debris.h
@@ -122,23 +122,35 @@
#define CONFIG_BAUDRATE 9600
#define CONFIG_DRAM_SPEED 100 /* MHz */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_CACHE | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_KGBD | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_SAVES | \
- CFG_CMD_SDRAM)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_KGBD
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
/*
@@ -435,7 +447,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/delta.h b/include/configs/delta.h
index 15681208b62..09667edaa5a 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -87,22 +87,49 @@
#define CONFIG_BAUDRATE 115200
-/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#ifdef TURN_ON_ETHERNET
-# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
+
+#define CONFIG_CMD_PING
+
#else
-# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_ENV \
- | CFG_CMD_NAND \
- | CFG_CMD_I2C) \
- & ~(CFG_CMD_NET \
- | CFG_CMD_FLASH \
- | CFG_CMD_IMLS))
+
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+
#endif
+/* USB */
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_USB_STORAGE 1
+#define CONFIG_DOS_PARTITION 1
+
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE OHCI_REGS_BASE
+#define CFG_USB_OHCI_SLOT_NAME "delta"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 3
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define LITTLEENDIAN 1 /* used by usb_ohci.c */
#define CONFIG_BOOTDELAY -1
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
@@ -114,7 +141,7 @@
#define CONFIG_CMDLINE_TAG
#define CONFIG_TIMESTAMP
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h
index 9ac2856f653..d32e0460234 100644
--- a/include/configs/dnp1110.h
+++ b/include/configs/dnp1110.h
@@ -66,10 +66,21 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200"
@@ -80,7 +91,7 @@
#define CONFIG_BOOTFILE "dnp1110"
#define CONFIG_BOOTCOMMAND "tftp; bootm"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h
index a014c7c07f8..f8e2c885b06 100644
--- a/include/configs/eXalion.h
+++ b/include/configs/eXalion.h
@@ -58,17 +58,27 @@
/*#define CONFIG_DRAM_SPEED 66 */ /* MHz */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_FLASH | \
- CFG_CMD_SDRAM | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ENV | \
- CFG_CMD_PCI )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_PCI
/*-----------------------------------------------------------------------
@@ -398,7 +408,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ebony.h b/include/configs/ebony.h
index a42319b097d..2c626a03288 100644
--- a/include/configs/ebony.h
+++ b/include/configs/ebony.h
@@ -32,6 +32,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_EBONY 1 /* Board is ebony */
#define CONFIG_440GP 1 /* Specifc GP support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
@@ -121,7 +122,7 @@
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
@@ -207,26 +208,38 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -235,7 +248,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -269,7 +282,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
@@ -286,7 +298,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -298,7 +310,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h
index bdda6292ed7..f5cf477a313 100644
--- a/include/configs/ep7312.h
+++ b/include/configs/ep7312.h
@@ -62,12 +62,23 @@
#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_JFFS2)
+#define CONFIG_CMD_JFFS2
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600"
@@ -78,7 +89,7 @@
/*#define CONFIG_BOOTFILE "impa7" */
#define CONFIG_BOOTCOMMAND "bootp;bootm"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h
index 04147a55d1d..85ad70a0d50 100644
--- a/include/configs/ep8248.h
+++ b/include/configs/ep8248.h
@@ -60,8 +60,8 @@
* SCC, 1-3 for FCC)
*
* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CFG_CMD_NET must
- * be removed from CONFIG_COMMANDS to remove support for networking.
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
@@ -123,23 +123,34 @@
#define CONFIG_BAUDRATE 38400
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_DHCP \
- | CFG_CMD_ECHO \
- | CFG_CMD_I2C \
- | CFG_CMD_IMMAP \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -157,7 +168,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -183,20 +194,20 @@
#define CFG_DIRECT_FLASH_TFTP
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#if defined(CONFIG_CMD_JFFS2)
#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
#define CFG_JFFS2_FIRST_SECTOR 0
#define CFG_JFFS2_LAST_SECTOR 62
#define CFG_JFFS2_SORT_FRAGMENTS
#define CFG_JFFS_CUSTOM_PART
-#endif /* CFG_CMD_JFFS2 */
+#endif
-#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#if defined(CONFIG_CMD_I2C)
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
#define CFG_I2C_SPEED 100000 /* I2C speed */
#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
-#endif /* CFG_CMD_I2C */
+#endif
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
@@ -240,7 +251,7 @@
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index 68625193091..025c24960d2 100644
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -183,8 +183,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
@@ -291,37 +290,49 @@
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
-/* What U-Boot subsytems do you want enabled? */
+
/*
-*/
-#define CONFIG_COMMANDS ( CFG_CMD_ALL & \
- ~( CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_DCR | \
- CFG_CMD_DHCP | \
- CFG_CMD_DISPLAY | \
- CFG_CMD_DOC | \
- CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_KGDB | \
- CFG_CMD_MII | \
- CFG_CMD_MMC | \
- CFG_CMD_NAND | \
- CFG_CMD_PCI | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_REISER | \
- CFG_CMD_SCSI | \
- CFG_CMD_SPI | \
- CFG_CMD_UNIVERSE| \
- CFG_CMD_USB | \
- CFG_CMD_VFD | \
- CFG_CMD_XIMG ) )
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_BSP
+#undef CONFIG_CMD_DCR
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DISPLAY
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_MFSL
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_PCI
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_UNIVERSE
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_XIMG
/* Where do the internal registers live? */
@@ -342,13 +353,10 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -496,7 +504,7 @@
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
index a77ccef63b9..4febd322a4f 100644
--- a/include/configs/ep82xxm.h
+++ b/include/configs/ep82xxm.h
@@ -60,8 +60,8 @@
* SCC, 1-3 for FCC)
*
* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CFG_CMD_NET must
- * be removed from CONFIG_COMMANDS to remove support for networking.
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
@@ -108,22 +108,34 @@
#define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_DHCP \
- | CFG_CMD_ECHO \
- | CFG_CMD_I2C \
- | CFG_CMD_IMMAP \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- | CFG_CMD_DATE \
- | CFG_CMD_DTT \
- | CFG_CMD_EEPROM \
- | CFG_CMD_PCI \
- | CFG_CMD_DIAG \
- )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_DIAG
+
#define CONFIG_ETHADDR 00:10:EC:00:88:65
#define CONFIG_HAS_ETH1
@@ -138,7 +150,7 @@
#define CONFIG_AUTO_COMPLETE 1
#define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3 ETHERNET"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -156,7 +168,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "ep82xxm=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -308,20 +320,20 @@
#define CFG_DIRECT_FLASH_TFTP
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#if defined(CONFIG_CMD_JFFS2)
#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
#define CFG_JFFS2_FIRST_SECTOR 0
#define CFG_JFFS2_LAST_SECTOR 62
#define CFG_JFFS2_SORT_FRAGMENTS
#define CFG_JFFS_CUSTOM_PART
-#endif /* CFG_CMD_JFFS2 */
+#endif
-#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#if defined(CONFIG_CMD_I2C)
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
#define CFG_I2C_SPEED 100000 /* I2C speed */
#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
-#endif /* CFG_CMD_I2C */
+#endif
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
@@ -358,7 +370,7 @@
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h
index 88c2c7437d0..66500c21e02 100644
--- a/include/configs/evb4510.h
+++ b/include/configs/evb4510.h
@@ -72,12 +72,23 @@
#define CONFIG_BAUDRATE 19200
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
+#define CONFIG_CMD_PING
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_ETHADDR 00:40:95:36:35:33
#define CONFIG_NETMASK 255.255.255.0
@@ -89,7 +100,7 @@
#define CONFIG_BOOTCOMMAND "tftp 100000 uImage"
/* #define CONFIG_BOOTARGS "console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h
index b68a2dca09c..e11ce4c715e 100644
--- a/include/configs/gcplus.h
+++ b/include/configs/gcplus.h
@@ -79,18 +79,30 @@
#define CONFIG_BAUDRATE 38400
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySA0,38400n8 mtdparts=sa1100-flash:1m@0(zImage),3m@1m(ramdisk.gz),12m@4m(userfs) root=/dev/nfs ip=bootp"
#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
#define CFG_AUTOLOAD "n" /* No autoload */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 38400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/gth2.h b/include/configs/gth2.h
index a49ed3bae3e..c2a50c1f473 100644
--- a/include/configs/gth2.h
+++ b/include/configs/gth2.h
@@ -71,12 +71,37 @@
/* Boot from Compact flash partition 2 as default */
#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm"
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \
- ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
- CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_LOADB | CFG_CMD_ELF | \
- CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_NFS | CFG_CMD_AUTOSCRIPT ))
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DHCP
+
+#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_AUTOSCRIPT
+
/*
* Miscellaneous configurable options
diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h
index 4f83b1945d3..ff5724082d0 100644
--- a/include/configs/gw8260.h
+++ b/include/configs/gw8260.h
@@ -194,8 +194,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC
@@ -286,13 +285,16 @@
#undef CONFIG_AUTOBOOT_DELAY_STR
#define DEBUG_BOOTKEYS 0
-/* Add support for a few extra bootp options like:
- * - File size
- * - DNS
+/*
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE | \
- CONFIG_BOOTP_DNS)
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
/* undef this to save memory */
#define CFG_LONGHELP
@@ -300,14 +302,21 @@
/* Monitor Command Prompt */
#define CFG_PROMPT "=> "
-/* What U-Boot subsytems do you want enabled? */
-#define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF | \
- CFG_CMD_ASKENV | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_MII)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+
+#undef CONFIG_CMD_KGDB
+
/* Where do the internal registers live? */
#define CFG_IMMR 0xf0000000
@@ -331,13 +340,10 @@
#define CONFIG_GW8260 1 /* on an GW8260 Board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -473,7 +479,7 @@
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h
new file mode 100644
index 00000000000..577f459e29e
--- /dev/null
+++ b/include/configs/hcu4.h
@@ -0,0 +1,348 @@
+/*
+ *(C) Copyright 2005-2007 Netstal Maschinen AG
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * hcu4.h - configuration for HCU4 board (similar to hcu5.h)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_HCU4 1 /* Board is HCU4 */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405GPr 1 /* HCU4 has a 405GPr */
+#define CONFIG_405GP 1
+#define CONFIG_4xx 1
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+*----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+
+
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+
+/* ... with on-chip memory here (4KBytes) */
+#define CFG_OCM_DATA_ADDR 0xF4000000
+#define CFG_OCM_DATA_SIZE 0x00001000
+/* Do not set up locked dcache as init ram. */
+#undef CFG_INIT_DCACHE_CS
+
+/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
+#define CFG_TEMP_STACK_OCM 1
+
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CONFIG_SERIAL_MULTI /* needed to be able to define
+ CONFIG_SERIAL_SOFTWARE_FIFO */
+#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD 691200
+
+/* Size (bytes) of interrupt driven serial port buffer.
+ * Set to 0 to use polling instead of interrupts.
+ * Setting to 0 will also disable RTS/CTS handshaking.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+/* Set console baudrate to 9600 */
+#define CONFIG_BAUDRATE 9600
+
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_NOWHERE
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+/* Put the environment after the SDRAM configuration */
+#define PROM_SIZE 2048
+#define CFG_ENV_OFFSET 512
+#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+/* Put the environment in Flash */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
+ * the first internal I2C controller of the PPC440EPx
+ *----------------------------------------------------------------------*/
+#define CFG_SPD_BUS_NUM 0
+
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/* This is the 7bit address of the device, not including P. */
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+
+/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#undef CFG_I2C_MULTI_EEPROMS
+
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+/* Setup some board specific values for the default environment variables */
+#define CONFIG_HOSTNAME hcu4
+#define CONFIG_IPADDR 172.25.1.42
+#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_SERVERIP 172.25.1.3
+
+#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=0x01000000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/home/diagnose/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/hcu4/uImage\0" \
+ "load=tftp 100000 hcu4/u-boot.bin\0" \
+ "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
+ "cp.b 100000 FFFa0000 60000\0" \
+ "upd=run load;run update\0" \
+ "vx=tftp ${loadaddr} hcu4_vx_rom;" \
+ "setenv bootargs emac(0,0)hcu4_vx_rom e=${ipaddr} " \
+ " h=${serverip} u=dpu pw=netstal8752 tn=hcu4 f=0x3008;" \
+ "bootvx ${loadaddr}\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run vx"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1 /* PHY address */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+/* SPD EEPROM (sdram speed config) disabled */
+#define CONFIG_SPD_EEPROM 1
+#define SPD_EEPROM_ADDRESS 0x50
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x02005400
+#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
+
+#define CFG_EBC_PB1AP 0x03041200
+#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_EBC_PB2AP 0x02054500
+#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_EBC_PB3AP 0x01840300
+#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_EBC_PB4AP 0x01800300
+#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_GPIO0_TCR 0x7ffe0000 /* GPIO value */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/* Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
+
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR 0xF0000500
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_HUSH_PARSER /* use "hush" command parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h
new file mode 100644
index 00000000000..90858819b67
--- /dev/null
+++ b/include/configs/hcu5.h
@@ -0,0 +1,391 @@
+/*
+ * (C) Copyright 2007 Netstal Maschinen AG
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * hcu5.h - configuration for HCU5 board (derived from sequoia.h)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_HCU5 1 /* Board is HCU5 */
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_440 1 /* ... PPC440 family */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+
+#define CFG_BOOT_BASE_ADDR 0xfff00000
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+
+#define CFG_USB2D0_BASE 0xe0000100
+#define CFG_USB_DEVICE 0xe0000000
+#define CFG_USB_HOST 0xe0000400
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#define CONFIG_BAUDRATE 9600
+#undef CONFIG_SERIAL_MULTI /* needed to be able to define
+ CONFIG_SERIAL_SOFTWARE_FIFO, but
+ CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */
+/* Size (bytes) of interrupt driven serial port buffer.
+ * Set to 0 to use polling instead of interrupts.
+ * Setting to 0 will also disable RTS/CTS handshaking.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_NOWHERE
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+/* Put the environment after the SDRAM and bootstrap configuration */
+#define PROM_SIZE 2048
+#define CFG_BOOSTRAP_OPTION_OFFSET 512
+#define CFG_ENV_OFFSET (CFG_BOOSTRAP_OPTION_OFFSET + 0x10)
+#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+/* Put the environment in Flash */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
+#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
+#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
+#define CONFIG_DDR_ECC 1 /* enable ECC */
+
+/*-----------------------------------------------------------------------
+ * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
+ * the second internal I2C controller of the PPC440EPx
+ *----------------------------------------------------------------------*/
+#define CFG_SPD_BUS_NUM 1
+
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/* This is the 7bit address of the device, not including P. */
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+
+/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#undef CFG_I2C_MULTI_EEPROMS
+
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+/* Setup some board specific values for the default environment variables */
+#define CONFIG_HOSTNAME hcu5
+#define CONFIG_IPADDR 172.25.1.42
+#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_SERVERIP 172.25.1.3
+
+#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=0x01000000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "bootfile=hcu5/uImage\0" \
+ "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
+ "load=tftp 100000 hcu5/u-boot.bin\0" \
+ "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
+ "cp.b 100000 FFFa0000 60000\0" \
+ "upd=run load;run update\0" \
+ "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \
+ "setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \
+ " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \
+ "bootvx ${loadaddr}\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run vx"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_M88E1111_PHY 1
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 1
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_USB
+
+#define CONFIG_SUPPORT_VFAT
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH CFG_FLASH_BASE
+#define CFG_CS_1 0xC8000000 /* CAN */
+#define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */
+#define CFG_CPLD CFG_CS_2
+#define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ * Memory Bank 0 (BOOT-FLASH) initialization
+ */
+#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */
+#define CFG_EBC_PB0AP 0x02005400
+#define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH | 0xda000) */
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
+
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/* Memory Bank 1 CAN-Chips initialization */
+#define CFG_EBC_PB1AP 0x02054500
+#define CFG_EBC_PB1CR 0xC8018000
+
+/* Memory Bank 2 CPLD/IMC-Bus standard initialization */
+#define CFG_EBC_PB2AP 0x01840300
+#define CFG_EBC_PB2CR 0xCC0BA000
+
+/* Memory Bank 3 IMC-Bus fast mode initialization */
+#define CFG_EBC_PB3AP 0x01800300
+#define CFG_EBC_PB3CR 0xCE0BA000
+
+/* Memory Bank 4 (not used) initialization */
+#undef CFG_EBC_PB4AP
+#undef CFG_EBC_PB4CR
+
+/* Memory Bank 5 (not used) initialization */
+#undef CFG_EBC_PB5AP
+#undef CFG_EBC_PB5CR
+
+#define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 )
+#define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 )
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_HUSH_PARSER /* use "hush" command parser */
+#ifdef CFG_HUSH_PARSER
+ #define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/hermes.h b/include/configs/hermes.h
index 91117bab726..e3a2ed28034 100644
--- a/include/configs/hermes.h
+++ b/include/configs/hermes.h
@@ -64,23 +64,28 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_COMMANDS CONFIG_CMD_DFL
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-/*----------------------------------------------------------------------*/
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
-/*----------------------------------------------------------------------*/
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -157,7 +162,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
index 095b5f6dc27..6c15b4e14c0 100644
--- a/include/configs/hmi1001.h
+++ b/include/configs/hmi1001.h
@@ -38,11 +38,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
#define CONFIG_BOARD_EARLY_INIT_R
/*
@@ -55,22 +50,31 @@
/* Partitions */
#define CONFIG_DOS_PARTITION
+
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DISPLAY | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DISPLAY
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
+
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
@@ -110,7 +114,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
@@ -222,7 +226,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -231,6 +235,11 @@
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST
@@ -242,8 +251,7 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
diff --git a/include/configs/hymod.h b/include/configs/hymod.h
index 8cad98dbd29..2547afb3cf0 100644
--- a/include/configs/hymod.h
+++ b/include/configs/hymod.h
@@ -69,8 +69,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -174,32 +173,44 @@
#define CONFIG_LAST_STAGE_INIT
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_CMD_BEDBUG | \
- CFG_CMD_BMP | \
- CFG_CMD_DISPLAY | \
- CFG_CMD_DOC | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_FPGA | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_NAND | \
- CFG_CMD_MMC | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_PCI | \
- CFG_CMD_USB | \
- CFG_CMD_REISER | \
- CFG_CMD_SCSI | \
- CFG_CMD_SPI | \
- CFG_CMD_UNIVERSE| \
- CFG_CMD_VFD | \
- CFG_CMD_XIMG ) )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_DISPLAY
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_MFSL
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_PCI
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_UNIVERSE
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_XIMG
+
#ifdef DEBUG
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
@@ -218,7 +229,7 @@
#define DEBUG_BOOTKEYS 0
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -247,7 +258,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -395,12 +406,13 @@
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
#endif
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
index b1dbe2ccb94..3821ebcf0d1 100644
--- a/include/configs/idmr.h
+++ b/include/configs/idmr.h
@@ -44,6 +44,8 @@
*/
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CONFIG_BOOTDELAY 5
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#define CONFIG_ETHADDR 00:06:3b:01:41:55
@@ -58,6 +60,8 @@
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root " \
"filesystem over NFS; echo"
+#define CONFIG_MCFTMR
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@@ -78,18 +82,27 @@
"u-boot=/tftpboot/idmr/u-boot.bin\0" \
""
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Commands' definition
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
- CFG_CMD_PING | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_NET) & \
- ~(CFG_CMD_LOADS | \
- CFG_CMD_LOADB))
+#include <config_cmd_default.h>
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NET
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
/*
@@ -112,14 +125,16 @@
#define CFG_ENV_IS_IN_FLASH
#endif /* !CONFIG_MONITOR_IS_IN_RAM */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
#define CFG_PROMPT "=> "
#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else /* !(CONFIG_COMMANDS & CFG_CMD_KGDB) */
+#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif /* (CONFIG_COMMANDS & CFG_CMD_KGDB) */
+#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
@@ -138,11 +153,27 @@
/*
* Ethernet
*/
-#define FEC_ENET
-#define CONFIG_NET_RETRY_COUNT 5
-#define CFG_ENET_BD_BASE 0x480000
-#define CFG_DISCOVER_PHY 1
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
#define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
/*
* Definitions for initial stack pointer and data area (in DPRAM)
@@ -177,7 +208,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/* FLASH organization */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
@@ -206,8 +237,8 @@
"2m(rootfs)," \
"-(user)";
-#if (CONFIG_COMMANDS & CFG_CMD_MII)
-#error MII commands don't work on iDMR board and sholud not be enabled.
-#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */
+#if defined(CONFIG_CMD_MII)
+#error "MII commands don't work on iDMR board and should not be enabled."
+#endif
#endif /* _IDMR_H */
diff --git a/include/configs/impa7.h b/include/configs/impa7.h
index 8b841ff546f..0e52ffe0a29 100644
--- a/include/configs/impa7.h
+++ b/include/configs/impa7.h
@@ -61,12 +61,23 @@
#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_JFFS2)
+#define CONFIG_CMD_JFFS2
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600"
@@ -77,7 +88,7 @@
/*#define CONFIG_BOOTFILE "impa7" */
#define CONFIG_BOOTCOMMAND "bootp;bootm"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/incaip.h b/include/configs/incaip.h
index 1c6216be843..4caf54efd31 100644
--- a/include/configs/incaip.h
+++ b/include/configs/incaip.h
@@ -81,15 +81,29 @@
""
#define CONFIG_BOOTCOMMAND "run flash_self"
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_SNTP )
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 773d5d2c1d9..0fac28fadd7 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -40,11 +40,6 @@
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -76,21 +71,30 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
+
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FAT | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP | \
- CFG_CMD_USB )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
@@ -147,7 +151,7 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* Flash configuration
@@ -239,7 +243,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -248,6 +252,11 @@
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST
@@ -259,8 +268,7 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
index 3cb9ebc454c..5310e0d428f 100644
--- a/include/configs/innokom.h
+++ b/include/configs/innokom.h
@@ -54,10 +54,34 @@
#define CONFIG_BAUDRATE 19200
#define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */
-#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP|CFG_CMD_CACHE)
-/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_RUN
+
#define CONFIG_BOOTDELAY 3
/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index 2f6e3993be4..1452bf2c467 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -66,15 +66,26 @@
#define CFG_SERIAL0 0x16000000
#define CFG_SERIAL1 0x17000000
-/*#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */
/*#define CONFIG_NET_MULTI */
-/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */
-#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_MEMORY
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty"
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index 4189f9c995c..69310d4dfbc 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -70,17 +70,28 @@
#define CFG_SERIAL0 0x16000000
#define CFG_SERIAL1 0x17000000
+
/*
-#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_PCI)
-*/
-#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | \
- CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV \
- )
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-/* #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+
#if 0
#define CONFIG_BOOTDELAY 2
diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h
index 9f9fdb25e2c..bc5f9e19bdc 100644
--- a/include/configs/ixdp425.h
+++ b/include/configs/ixdp425.h
@@ -53,14 +53,28 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF | CFG_CMD_PCI)
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_PCI
+
#define CONFIG_PCI
#define CONFIG_NET_MULTI
#define CONFIG_EEPRO100
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-/* These are u-boot generic parameters */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b*/
@@ -71,7 +85,7 @@
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
#define CONFIG_CMDLINE_TAG
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h
index af4ecf621a3..da59230bb65 100644
--- a/include/configs/ixdpg425.h
+++ b/include/configs/ixdpg425.h
@@ -75,16 +75,27 @@
#define CONFIG_BAUDRATE 115200
#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_NET | \
- CFG_CMD_MII | \
- CFG_CMD_PING)
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-/* These are u-boot generic parameters */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index 5b97526fc49..b7100e986cd 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -41,11 +41,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -71,7 +66,6 @@
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
-#define ADD_PCI_CMD CFG_CMD_PCI
#endif
#define CFG_XLB_PIPELINING 1
@@ -87,15 +81,28 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP)
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#if defined(CONFIG_PCI)
+#define CODFIG_CMD_PCI
+#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Autobooting
@@ -138,12 +145,9 @@
#if 0
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -254,7 +258,7 @@
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -271,6 +275,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index cc47a168ed3..7908e5a4743 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -42,7 +42,6 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
-#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
#undef CONFIG_SHOW_BOOT_PROGRESS
/*-----------------------------------------------------------------------
@@ -67,11 +66,11 @@
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
-#define CFG_PCIE0_XCFGBASE 0xc0000400
-#define CFG_PCIE1_CFGBASE 0xc0001000
-#define CFG_PCIE1_XCFGBASE 0xc0001400
-#define CFG_PCIE2_CFGBASE 0xc0002000
-#define CFG_PCIE2_XCFGBASE 0xc0002400
+#define CFG_PCIE1_CFGBASE 0xc1000000
+#define CFG_PCIE2_CFGBASE 0xc2000000
+#define CFG_PCIE0_XCFGBASE 0xc3000000
+#define CFG_PCIE1_XCFGBASE 0xc3001000
+#define CFG_PCIE2_XCFGBASE 0xc3002000
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
@@ -202,6 +201,7 @@
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
"kozio=bootm ffc60000\0" \
+ "pciconfighost=1\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -210,28 +210,40 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_DTT | \
- CFG_CMD_ELF | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
#define CONFIG_MII 1 /* MII PHY management */
@@ -254,7 +266,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -311,10 +323,9 @@
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#undef CFG_PCI_MASTER_INIT
@@ -421,7 +432,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -433,7 +444,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h
index 6590f6f5f0d..75d9c3b3b46 100644
--- a/include/configs/kb9202.h
+++ b/include/configs/kb9202.h
@@ -78,17 +78,29 @@
#define CONFIG_BOOTDELAY 3
#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | \
- CFG_CMD_I2C | \
- CFG_CMD_PING | \
- CFG_CMD_DHCP ) & \
- ~(CFG_CMD_BDI | \
- CFG_CMD_FPGA | \
- CFG_CMD_MISC))
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h
index 61cf70576d7..569800aa231 100644
--- a/include/configs/kvme080.h
+++ b/include/configs/kvme080.h
@@ -60,32 +60,44 @@
#undef CONFIG_WATCHDOG
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_DS164x
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_CACHE | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP)
-#define CONFIG_NETCONSOLE
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
-#include <cmd_confdefs.h>
+
+#define CONFIG_NETCONSOLE
#define CFG_LONGHELP
#define CFG_PROMPT "=> "
@@ -178,7 +190,7 @@
#define CONFIG_SYS_CLK_FREQ 33333333
#define CFG_CACHELINE_SIZE 32
-#if CONFIG_COMMANDS & CFG_CMD_KGDB
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5
#endif
diff --git a/include/configs/lart.h b/include/configs/lart.h
index a00640bf8e6..8f18c9f1b1b 100644
--- a/include/configs/lart.h
+++ b/include/configs/lart.h
@@ -59,10 +59,21 @@
#define CONFIG_BAUDRATE 9600
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600"
@@ -73,7 +84,7 @@
#define CONFIG_BOOTFILE "elinos-lart"
#define CONFIG_BOOTCOMMAND "tftp; bootm"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/logodl.h b/include/configs/logodl.h
index 715ed74eade..2b2d37751e0 100644
--- a/include/configs/logodl.h
+++ b/include/configs/logodl.h
@@ -54,10 +54,26 @@
#define CONFIG_BAUDRATE 19200
#undef CONFIG_MISC_INIT_R /* FIXME: misc_init_r() missing */
-#define CONFIG_COMMANDS (CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO)
-/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_RUN
+
#define CONFIG_BOOTDELAY 3
/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h
index 7e515230a33..e3fef5e2ce9 100644
--- a/include/configs/lpc2292sodimm.h
+++ b/include/configs/lpc2292sodimm.h
@@ -1,12 +1,8 @@
/*
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Configuation settings for the EP7312 board.
- *
- * Modified to work on Armadillo HT1070 ARM720T board
- * (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com
+ * Configuation settings for the LPC2292SODIMM board from Embedded Artists.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -31,7 +27,7 @@
#define __CONFIG_H
/*
- * If we are developing, we might want to start armboot from ram
+ * If we are developing, we might want to start u-boot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
#undef CONFIG_INIT_CRITICAL /* undef for developing */
@@ -46,7 +42,7 @@
#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
#define CONFIG_LPC2292
-#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
+#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
#undef CONFIG_USE_IRQ /* don't need them anymore */
@@ -70,24 +66,31 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_FAT | \
- CFG_CMD_MMC | \
- CFG_CMD_NET | \
- CFG_CMD_PING)
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#define CONFIG_BOOTDELAY 5
/*
@@ -103,11 +106,12 @@
#define CFG_MEMTEST_START 0x40000000 /* memtest works on */
#define CFG_MEMTEST_END 0x40000000 /* 4 ... 8 MB in DRAM */
-#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
-#define CFG_LOAD_ADDR 0x00040000 /* default load address for armadillo: kernel img is here*/
+#define CFG_LOAD_ADDR 0x00040000 /* default load address for */
+ /* armadillo: kernel img is here*/
-#define CFG_SYS_CLK_FREQ 58982400 /* Hz */
+#define CFG_SYS_CLK_FREQ 58982400 /* Hz */
#define CFG_HZ 2048 /* decrementer freq in Hz */
/* valid baudrates */
@@ -154,5 +158,7 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_MMC 1
+/* we use this ethernet chip */
+#define CONFIG_ENC28J60
#endif /* __CONFIG_H */
diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h
index d7d0460ef66..04148898eac 100644
--- a/include/configs/lpd7a400.h
+++ b/include/configs/lpd7a400.h
@@ -55,19 +55,32 @@
#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#ifndef USE_920T_MMU
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE))
+ #define CONFIG_CMD_PING
+ #undef CONFIG_CMD_CACHE
#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE)
+ #define CONFIG_CMD_DATE
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#define CONFIG_BOOTDELAY 3
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h
index 4002e6849cc..11ede968180 100644
--- a/include/configs/lpd7a404.h
+++ b/include/configs/lpd7a404.h
@@ -55,19 +55,32 @@
#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#ifndef USE_920T_MMU
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE))
+ #define CONFIG_CMD_PING)
+ #undef CONFIG_CMD_CACHE
#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE)
+ #define CONFIG_CMD_DATE
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#define CONFIG_BOOTDELAY 3
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
diff --git a/include/configs/luan.h b/include/configs/luan.h
index 9c8769b200b..a09dd74733e 100644
--- a/include/configs/luan.h
+++ b/include/configs/luan.h
@@ -39,7 +39,6 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
@@ -135,7 +134,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
-#undef CONFIG_DDR_ECC /* no ECC support for now */
+#define CONFIG_DDR_ECC 1 /* with ECC support */
/*-----------------------------------------------------------------------
* I2C
@@ -212,31 +211,38 @@
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- 0)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -264,7 +270,7 @@
* PCI stuff
*-----------------------------------------------------------------------
*/
-#if (CONFIG_COMMANDS & CFG_CMD_PCI)
+#if defined(CONFIG_CMD_PCI)
/* General PCI */
#define CONFIG_PCI /* include pci support */
@@ -272,14 +278,13 @@
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#undef CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */
-#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */
+#endif
/*
* For booting Linux, the board info and command line data
@@ -293,7 +298,7 @@
*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -305,7 +310,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h
index ad1035b6d63..4adf2542219 100644
--- a/include/configs/lubbock.h
+++ b/include/configs/lubbock.h
@@ -67,10 +67,24 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
@@ -82,7 +96,7 @@
#define CONFIG_CMDLINE_TAG
#define CONFIG_TIMESTAMP
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h
index 9b4c0046ef4..8a8270260a3 100644
--- a/include/configs/lwmon.h
+++ b/include/configs/lwmon.h
@@ -170,34 +170,41 @@
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
-#else
-#define CFG_CMD_POST_DIAG 0
+#define CONFIG_CMD_DIAG
#endif
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_SNTP )
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-/*----------------------------------------------------------------------*/
/*
* Miscellaneous configurable options
@@ -210,7 +217,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -276,7 +283,7 @@
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x40000000
-#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
@@ -370,7 +377,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
new file mode 100644
index 00000000000..be483245b91
--- /dev/null
+++ b/include/configs/lwmon5.h
@@ -0,0 +1,505 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * lwmon5.h - configuration for lwmon5 board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_LWMON5 1 /* Board is lwmon5 */
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_440 1 /* ... PPC440 family */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
+
+#define CFG_BOOT_BASE_ADDR 0xf0000000
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_LIME_BASE_0 0xc0000000
+#define CFG_LIME_BASE_1 0xc1000000
+#define CFG_LIME_BASE_2 0xc2000000
+#define CFG_LIME_BASE_3 0xc3000000
+#define CFG_FPGA_BASE_0 0xc4000000
+#define CFG_FPGA_BASE_1 0xc4200000
+#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+
+#define CFG_USB2D0_BASE 0xe0000100
+#define CFG_USB_DEVICE 0xe0000000
+#define CFG_USB_HOST 0xe0000400
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
+
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK /* no external clock provided */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+/* define this if you want console on UART1 */
+#define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH0 0xFC000000
+#define CFG_FLASH1 0xF8000000
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
+
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM (256) /* 256MB */
+#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
+#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
+#if 0 /* test-only: disable ECC for now */
+#define CONFIG_DDR_ECC 1 /* enable ECC */
+#define CFG_POST_ECC_ON CFG_POST_ECC
+#else
+#define CFG_POST_ECC_ON 0
+#endif
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_CACHE | \
+ CFG_POST_CPU | \
+ CFG_POST_ECC_ON | \
+ CFG_POST_ETHER | \
+ CFG_POST_FPU | \
+ CFG_POST_I2C | \
+ CFG_POST_MEMORY | \
+ CFG_POST_RTC | \
+ CFG_POST_SPR | \
+ CFG_POST_UART)
+
+#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
+#define CONFIG_LOGBUFFER
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
+ /* 64 byte page write mode using*/
+ /* last 6 bits of the address */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
+#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
+#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
+
+#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
+#if 0
+#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
+#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
+#endif
+
+#define CONFIG_PREBOOT "setenv bootdelay 15"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hostname=lwmon5\0" \
+ "netdev=eth0\0" \
+ "unlock=yes\0" \
+ "logversion=2\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xxFP\0" \
+ "bootfile=/tftpboot/lwmon5/uImage\0" \
+ "kernel_addr=FC000000\0" \
+ "ramdisk_addr=FC180000\0" \
+ "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
+ "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
+ "cp.b 200000 FFF80000 80000\0" \
+ "upd=run load;run update\0" \
+ "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
+ "autoscr 200000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_RESET_DELAY 300
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 1
+
+/* USB */
+#ifdef CONFIG_440EPX
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+#endif /* CONFIG_440EPX */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+#ifdef CONFIG_440EPX
+#define CONFIG_CMD_USB
+#endif
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CONFIG_SUPPORT_VFAT
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+
+#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH CFG_FLASH_BASE
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x03050200
+#define CFG_EBC_PB0CR (CFG_FLASH | 0xfc000)
+
+/* Memory Bank 1 (Lime) initialization */
+#define CFG_EBC_PB1AP 0x01004380
+#define CFG_EBC_PB1CR (CFG_LIME_BASE_0 | 0xdc000)
+
+/* Memory Bank 2 (FPGA) initialization */
+#define CFG_EBC_PB2AP 0x01004400
+#define CFG_EBC_PB2CR (CFG_FPGA_BASE_0 | 0x1c000)
+
+/* Memory Bank 3 (FPGA2) initialization */
+#define CFG_EBC_PB3AP 0x01004400
+#define CFG_EBC_PB3CR (CFG_FPGA_BASE_1 | 0x1c000)
+
+#define CFG_EBC_CFG 0xb8400000
+
+/*-----------------------------------------------------------------------
+ * Graphics (Fujitsu Lime)
+ *----------------------------------------------------------------------*/
+/* SDRAM Clock frequency adjustment register */
+#define CFG_LIME_SDRAM_CLOCK 0xC1FC0038
+/* Lime Clock frequency is to set 100MHz */
+#define CFG_LIME_CLOCK_100MHZ 0x00000
+#if 0
+/* Lime Clock frequency for 133MHz */
+#define CFG_LIME_CLOCK_133MHZ 0x10000
+#endif
+
+/* SDRAM Parameter register */
+#define CFG_LIME_MMR 0xC1FCFFFC
+/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
+ and pixel flare on display when 133MHz was configured. According to
+ SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
+#ifdef CFG_LIME_CLOCK_133MHZ
+#define CFG_LIME_MMR_VALUE 0x414FB7F3
+#else
+#define CFG_LIME_MMR_VALUE 0x414FB7F2
+#endif
+
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CFG_GPIO_PHY1_RST 12
+#define CFG_GPIO_FLASH_WP 14
+#define CFG_GPIO_PHY0_RST 22
+#define CFG_GPIO_EEPROM_EXT_WP 55
+#define CFG_GPIO_EEPROM_INT_WP 57
+#define CFG_GPIO_LIME_S 59
+#define CFG_GPIO_LIME_RST 60
+#define CFG_GPIO_WATCHDOG 63
+
+/*-----------------------------------------------------------------------
+ * PPC440 GPIO Configuration
+ */
+#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+{ \
+/* GPIO Core 0 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
+}, \
+{ \
+/* GPIO Core 1 */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
+} \
+}
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index 621a81c9c56..cc2dbcdef9b 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -40,11 +40,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*
@@ -92,27 +87,37 @@
/* USB */
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
/* automatic software updates (see board/mcc200/auto_update.c) */
#define CONFIG_AUTO_UPDATE 1
+
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- ADD_USB_CMD | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C)
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_USB
+
+#undef CONFIG_CMD_NET
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Autobooting
*/
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
@@ -128,20 +133,30 @@
# define CFG__LINUX_CONSOLE "ttyS0"
#else
# define CFG__BOARDNAME "mcc200"
-# define CFG__LINUX_CONSOLE "ttyEU7"
+# define CFG__LINUX_CONSOLE "ttyEU5"
#endif
+/* Network */
+#define CONFIG_ETHADDR 00:17:17:ff:00:00
+#define CONFIG_IPADDR 10.76.9.29
+#define CONFIG_SERVERIP 10.76.9.1
+
+#include <version.h> /* For U-Boot version */
+
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ubootver=" U_BOOT_VERSION "\0" \
"netdev=eth0\0" \
"hostname=" CFG__BOARDNAME "\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "ramargs=setenv bootargs root=/dev/mtdblock2 " \
+ "rootfstype=cramfs\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addcons=setenv bootargs ${bootargs} " \
- "console=${console},${baudrate}\0" \
+ "console=${console},${baudrate} " \
+ "ubootver=${ubootver} board=${board}\0" \
"flash_nfs=run nfsargs addip addcons;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addcons;" \
@@ -153,6 +168,7 @@
"bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \
"load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \
"text_base=" MK_STR(TEXT_BASE) "\0" \
+ "kernel_addr=0xFC0C0000\0" \
"update=protect off ${text_base} +${filesize};" \
"era ${text_base} +${filesize};" \
"cp.b 200000 ${text_base} ${filesize}\0" \
@@ -169,7 +185,7 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
@@ -253,7 +269,7 @@
/*
* Ethernet configuration
*/
-#define CONFIG_MPC5xxx_FEC 1
+/*#define CONFIG_MPC5xxx_FEC 1*/
/*
* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
*/
@@ -291,7 +307,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -307,6 +323,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
@@ -329,6 +350,13 @@
#define CFG_CS1_SIZE 0x00001000
#define CFG_CS1_CFG 0x1d300
+/* Leica - build revision resistors */
+/*
+#define CFG_CS3_START 0x80020000
+#define CFG_CS3_SIZE 0x00000004
+#define CFG_CS3_CFG 0x1d300
+*/
+
/*
* Select one of quarts as a default
* console. If undefined - PSC console
@@ -384,4 +412,8 @@
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00005000
+#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR "432"
+#define CONFIG_SILENT_CONSOLE 1
+
#endif /* __CONFIG_H */
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
index 0c1029426c2..49919fbafbb 100644
--- a/include/configs/mecp5200.h
+++ b/include/configs/mecp5200.h
@@ -50,11 +50,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -88,26 +83,32 @@
/* USB */
#if 0
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_EXT2 | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_BSP | \
- CFG_CMD_ELF)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_ELF
+
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CFG_LOWBOOT 1
@@ -258,7 +259,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -276,6 +277,11 @@
#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/ml300.h b/include/configs/ml300.h
index 6762cd61eae..0183041842a 100644
--- a/include/configs/ml300.h
+++ b/include/configs/ml300.h
@@ -87,13 +87,28 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define REMOVE_COMMANDS (CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_FAT | \
- CFG_CMD_IMLS )
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_NET) \
- & ~REMOVE_COMMANDS)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NET
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_IMLS
+
/* #define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ */
/* 300000000 */
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index cb159e79dc6..7eeae708a72 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -28,6 +28,7 @@
#include "../board/xilinx/ml401/xparameters.h"
#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
+#define MICROBLAZE_V5 1
#define CONFIG_ML401 1 /* ML401 Board */
/* uart */
@@ -36,11 +37,11 @@
#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
/* setting reset address */
-#define CFG_RESET_ADDRESS TEXT_BASE
+/*#define CFG_RESET_ADDRESS TEXT_BASE*/
/* ethernet */
#define CONFIG_EMACLITE 1
-#define XPAR_EMAC_0_DEVICE_ID XPAR_XEMAC_NUM_INSTANCES
+#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
/* gpio */
#define CFG_GPIO_0 1
@@ -58,6 +59,10 @@
#define FREQUENCE XILINX_CLOCK_FREQ
#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
+/* FSL */
+#define CFG_FSL_2
+#define FSL_INTR_2 1
+
/*
* memory layout - Example
* TEXT_BASE = 0x1200_0000;
@@ -93,7 +98,8 @@
/* global pointer */
#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
-#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
+/* start of global data */
+#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
/* monitor code */
#define SIZE 0x40000
@@ -117,6 +123,7 @@
#define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+ #define CFG_FLASH_PROTECTION /* hardware flash protection */
#ifdef RAMENV
#define CFG_ENV_IS_NOWHERE 1
@@ -135,69 +142,62 @@
#define CFG_ENV_IS_NOWHERE 1
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
+ #define CFG_FLASH_PROTECTION /* hardware flash protection */
#endif /* !FLASH */
-#ifdef FLASH
- #ifdef RAMENV
- #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
- CFG_CMD_MEMORY |\
- CFG_CMD_MISC |\
- CFG_CMD_AUTOSCRIPT |\
- CFG_CMD_IRQ |\
- CFG_CMD_ASKENV |\
- CFG_CMD_BDI |\
- CFG_CMD_RUN |\
- CFG_CMD_LOADS |\
- CFG_CMD_LOADB |\
- CFG_CMD_IMI |\
- CFG_CMD_NET |\
- CFG_CMD_CACHE |\
- CFG_CMD_IMLS |\
- CFG_CMD_FLASH |\
- CFG_CMD_PING \
- )
- #else /* !RAMENV */
- #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
- CFG_CMD_MEMORY |\
- CFG_CMD_MISC |\
- CFG_CMD_AUTOSCRIPT |\
- CFG_CMD_IRQ |\
- CFG_CMD_ASKENV |\
- CFG_CMD_BDI |\
- CFG_CMD_RUN |\
- CFG_CMD_LOADS |\
- CFG_CMD_LOADB |\
- CFG_CMD_IMI |\
- CFG_CMD_NET |\
- CFG_CMD_CACHE |\
- CFG_CMD_IMLS |\
- CFG_CMD_FLASH |\
- CFG_CMD_PING |\
- CFG_CMD_ENV |\
- CFG_CMD_SAVES \
- )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MFSL
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+
+#if defined(FLASH)
+ #define CONFIG_CMD_ECHO
+ #define CONFIG_CMD_FLASH
+ #define CONFIG_CMD_IMLS
+ #define CONFIG_CMD_JFFS2
+
+ #if !defined(RAMENV)
+ #define CONFIG_CMD_ENV
+ #define CONFIG_CMD_SAVES
#endif
+#endif
+
+#if defined(CONFIG_CMD_JFFS2)
+/* JFFS2 partitions */
+#define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */
+#define MTDIDS_DEFAULT "nor0=ml401-0"
-#else /* !FLASH */
- #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
- CFG_CMD_MEMORY |\
- CFG_CMD_MISC |\
- CFG_CMD_AUTOSCRIPT |\
- CFG_CMD_IRQ |\
- CFG_CMD_ASKENV |\
- CFG_CMD_BDI |\
- CFG_CMD_RUN |\
- CFG_CMD_LOADS |\
- CFG_CMD_LOADB |\
- CFG_CMD_IMI |\
- CFG_CMD_NET |\
- CFG_CMD_CACHE |\
- CFG_CMD_PING \
- )
-#endif /* !FLASH */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/* default mtd partition table */
+#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\
+ "256k(env),3m(kernel),1m(romfs),"\
+ "1m(cramfs),-(jffs2)"
+#endif
/* Miscellaneous configurable options */
#define CFG_PROMPT "U-Boot-mONStR> "
@@ -207,7 +207,7 @@
#define CFG_LONGHELP
#define CFG_LOAD_ADDR 0x12000000 /* default load address */
-#define CONFIG_BOOTDELAY 30
+#define CONFIG_BOOTDELAY 30
#define CONFIG_BOOTARGS "root=romfs"
#define CONFIG_HOSTNAME "ml401"
#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
@@ -221,10 +221,19 @@
#define CFG_HZ 1000
/* system ace */
-/*#define CONFIG_SYSTEMACE
-#define DEBUG_SYSTEMACE
-#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
-#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
-#define CONFIG_DOS_PARTITION
-*/
+#define CONFIG_SYSTEMACE
+/* #define DEBUG_SYSTEMACE */
+#define SYSTEMACE_CONFIG_FPGA
+#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
+#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo"
+
+#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\
+ "nor0=ml401-0\0"\
+ "mtdparts=mtdparts=ml401-0:"\
+ "256k(u-boot),256k(env),3m(kernel),"\
+ "1m(romfs),1m(cramfs),-(jffs2)\0"
+
#endif /* __CONFIG_H */
diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h
index 20287674fab..4461bdfd187 100644
--- a/include/configs/modnet50.h
+++ b/include/configs/modnet50.h
@@ -63,12 +63,23 @@
#define CONFIG_BAUDRATE 38400
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_JFFS2))
+#define CONFIG_CMD_JFFS2
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.30.2
@@ -81,7 +92,7 @@
#define CONFIG_BOOTCOMMAND "bootm 0x10020000 0x100a0000"
#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K root=/dev/ram keepinitrd"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 5328e8d6b1c..9a216321628 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -26,12 +26,10 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-
/*
* High Level Configuration Options
*/
-
/* CPU and board */
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
@@ -39,21 +37,35 @@
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_ELF | \
- CFG_CMD_MII | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_NET | \
- CFG_CMD_PING)
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DTT
/*
@@ -71,7 +83,7 @@
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_PHY_ADDR 0x2
#define CONFIG_PHY_TYPE 0x79c874
-
+#define CONFIG_RESET_PHY_R 1
/*
* Autobooting
@@ -94,42 +106,51 @@
* Default environment settings
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
- "sdram_test=0\0" \
"netdev=eth0\0" \
"hostname=motionpro\0" \
"netmask=255.255.0.0\0" \
"ipaddr=192.168.160.22\0" \
"serverip=192.168.1.1\0" \
"gatewayip=192.168.1.1\0" \
- "kernel_addr=200000\0" \
+ "console=ttyPSC0,115200\0" \
"u-boot_addr=100000\0" \
- "kernel_sector=20\0" \
- "kernel_size=1000\0" \
- "console=ttyS0,115200\0" \
+ "kernel_addr=200000\0" \
+ "fdt_addr=400000\0" \
+ "ramdisk_addr=500000\0" \
+ "multi_image_addr=800000\0" \
"rootpath=/opt/eldk-4.1/ppc_6xx\0" \
- "bootfile=/tftpboot/motionpro/uImage\0" \
"u-boot=/tftpboot/motionpro/u-boot.bin\0" \
- "load=tftp $(u-boot_addr) $(u-boot)\0" \
+ "bootfile=/tftpboot/motionpro/uImage\0" \
+ "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \
+ "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \
+ "multi_image_file=kernel+initrd+dtb.img\0" \
+ "load=tftp ${u-boot_addr} ${u-boot}\0" \
"update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; " \
- "cp.b $(u-boot_addr) fff00000 $(filesize);" \
+ "cp.b ${u-boot_addr} fff00000 ${filesize};" \
"prot on fff00000 fff3ffff\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) console=$(console) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):" \
- "$(netmask):$(hostname):$(netdev):off panic=1\0" \
- "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
- "flash_self=run ramargs addip;bootm $(kernel_addr) " \
- "$(ramdisk_addr)\0" \
- "net_nfs=tftp $(kernel_addr) $(bootfile); run nfsargs addip; " \
- "bootm $(kernel_addr)\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "fstype=ext3\0" \
- "fatargs=setenv bootargs init=/linuxrc rw\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "fat_args=setenv bootargs rw\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off panic=1 " \
+ "console=${console}\0" \
+ "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
+ "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip; " \
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "net_self=tftp ${kernel_addr} ${bootfile}; " \
+ "tftp ${fdt_addr} ${fdt_file}; " \
+ "tftp ${ramdisk_addr} ${ramdisk_file}; " \
+ "run ramargs addip; " \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+ "fat_multi=run fat_args addip; fatload ide 0:1 " \
+ "${multi_image_addr} ${multi_image_file}; " \
+ "bootm ${multi_image_addr}\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
-
/*
* do board-specific init
*/
@@ -148,6 +169,12 @@
/*
+ * Set IPB speed to 100MHz
+ */
+#define CFG_IPBCLK_EQUALS_XLBCLK
+
+
+/*
* Memory map
*/
/*
@@ -243,6 +270,84 @@
#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
+/*
+ * MTD configuration
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=motionpro-0"
+#define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \
+ "13m(fs),2m(kernel),256k(uboot)," \
+ "64k(env),64k(redund_env),64k(dtb)," \
+ "-(user_data)"
+
+/*
+ * IDE/ATA configuration
+ */
+#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
+#define CFG_IDE_MAXBUS 1
+#define CFG_IDE_MAXDEVICE 1
+#define CONFIG_IDE_PREINIT
+
+#define CFG_ATA_DATA_OFFSET 0x0060
+#define CFG_ATA_REG_OFFSET CFG_ATA_DATA_OFFSET
+#define CFG_ATA_STRIDE 4
+#define CONFIG_DOS_PARTITION
+
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_MODULE 2 /* select I2C module #2 */
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* DTT driver needs this */
+#define CFG_EEPROM_PAGE_WRITE_BITS 1 /* 2 bytes per write cycle */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 2ms/cycle + 3ms extra */
+#define CFG_I2C_MULTI_EEPROMS 1 /* 2 EEPROMs (addr:50,52) */
+
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_DS1337 1
+#define CFG_I2C_RTC_ADDR 0x68
+
+
+/*
+ * Status LED configuration
+ */
+#define CONFIG_STATUS_LED /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED
+
+#define ENABLE_GPIO_OUT 0x00000024
+#define LED_ON 0x00000010
+
+#ifndef __ASSEMBLY__
+/*
+ * In case of Motion-PRO, a LED is identified by its corresponding
+ * GPT Enable and Mode Select Register.
+ */
+typedef volatile unsigned long * led_id_t;
+
+extern void __led_init(led_id_t id, int state);
+extern void __led_toggle(led_id_t id);
+extern void __led_set(led_id_t id, int state);
+#endif /* __ASSEMBLY__ */
+
+
+/*
+ * Temperature sensor
+ */
+#define CONFIG_DTT_LM75 1
+#define CONFIG_DTT_SENSORS { 0x49 }
+
/*
* Environment settings
@@ -253,6 +358,9 @@
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_SECT_SIZE 0x10000
+/* Configuration of redundant environment */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*
* Pin multiplexing configuration
@@ -270,11 +378,17 @@
/*
+ * Motion-PRO's CPLD revision control register
+ */
+#define CPLD_REV_REGISTER (CFG_CS2_START + 0x06)
+
+
+/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
@@ -302,4 +416,13 @@
/* Not needed for MPC 5xxx U-Boot, but used by tools/updater */
#define CFG_RESET_ADDRESS 0xfff00100
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,5200@0"
+#define OF_SOC "soc5200@f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
+
#endif /* __CONFIG_H */
diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
index 04f1f240808..ea5a44b1d1e 100644
--- a/include/configs/mp2usb.h
+++ b/include/configs/mp2usb.h
@@ -101,12 +101,18 @@
#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
-#define CONFIG_USB_OHCI 1
+#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_USB_KEYBOARD 1
#define CONFIG_USB_STORAGE 1
#define CONFIG_DOS_PARTITION 1
#define CONFIG_AT91C_PQFP_UHPBUG 1
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
+#define CFG_USB_OHCI_SLOT_NAME "at91rm9200"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
#undef CONFIG_HARD_I2C
#ifdef CONFIG_HARD_I2C
@@ -123,40 +129,56 @@
#define CONFIG_BOOTDELAY 3
-#ifdef CONFIG_HARD_I2C
-#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP | \
- CFG_CMD_MISC))
-#else
-#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP | \
- CFG_CMD_USB | \
- CFG_CMD_CACHE) & \
- ~(CFG_CMD_BDI | \
- CFG_CMD_IMI | \
- CFG_CMD_AUTOSCRIPT | \
- CFG_CMD_FPGA | \
- CFG_CMD_MISC | \
- CFG_CMD_LOADS ))
+#if !defined(CONFIG_HARD_I2C)
#define CONFIG_TIMESTAMP
#endif
-#define CFG_LONGHELP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#if defined(CONFIG_HARD_I2C)
+
+ #define CONFIG_CMD_DATE
+ #define CONFIG_CMD_EEPROM
+ #define CONFIG_CMD_I2C
+ #define CONFIG_CMD_MISC
+
+#else
+
+ #define CONFIG_CMD_USB
+ #define CONFIG_CMD_CACHE
+
+ #undef CONFIG_CMD_AUTOSCRIPT
+ #undef CONFIG_CMD_BDI
+ #undef CONFIG_CMD_FPGA
+ #undef CONFIG_CMD_IMI
+ #undef CONFIG_CMD_LOADS
+ #undef CONFIG_CMD_MISC
+
+#endif
+
+
+#define CFG_LONGHELP
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
-#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
+#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
#define CFG_MEMTEST_START PHYS_SDRAM
#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h
index 243a3f6c8fc..bd3107ab23c 100644
--- a/include/configs/mpc7448hpc2.h
+++ b/include/configs/mpc7448hpc2.h
@@ -80,9 +80,6 @@
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,7448@0"
#define OF_TSI "tsi108@c0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -146,25 +143,34 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_ASKENV \
- | CFG_CMD_CACHE \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C \
- | CFG_CMD_SDRAM \
- | CFG_CMD_EEPROM \
- | CFG_CMD_FLASH \
- | CFG_CMD_ENV \
- | CFG_CMD_BSP \
- | CFG_CMD_DHCP \
- | CFG_CMD_PING \
- | CFG_CMD_DATE)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+
/*set date in u-boot*/
#define CONFIG_RTC_M48T35A
@@ -182,7 +188,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
#else
@@ -366,9 +372,9 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1/* Flash can be at one of two addresses */
+#define CFG_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */
#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
-#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, /* CFG_FLASH_BASE2 */ }
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
@@ -387,7 +393,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h
index 7f3dfd5c987..5125b21e04f 100644
--- a/include/configs/mx1ads.h
+++ b/include/configs/mx1ads.h
@@ -78,25 +78,32 @@
#define CONFIG_BAUDRATE 115200
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_CACHE | \
- CFG_CMD_REGINFO | \
- CFG_CMD_ELF)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_ELF
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M"
#define CONFIG_BOOTFILE "mx1ads"
#define CONFIG_BOOTCOMMAND "tftp; bootm"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h
index 9816be8dc4f..d527d098f57 100644
--- a/include/configs/mx1fs2.h
+++ b/include/configs/mx1fs2.h
@@ -34,22 +34,30 @@
#undef _CONFIG_UART4 /* internal uart 4 */
#undef CONFIG_SILENT_CONSOLE /* use this to disable output */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
- * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
- * functionality or size of u-boot code.
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- & ~CFG_CMD_LOADS \
- & ~CFG_CMD_CONSOLE \
- & ~CFG_CMD_AUTOSCRIPT \
- & ~CFG_CMD_NET \
- & ~CFG_CMD_PING \
- & ~CFG_CMD_DHCP \
- | CFG_CMD_JFFS2 \
- )
-
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_JFFS2
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_PING
+#undef CONFIG_CMD_DHCP
+
/*
* Boot options. Setting delay to -1 stops autostart count down.
@@ -160,7 +168,7 @@
* Right now there is no gain for user, but later on booting kernel might be
* possible. Consider using XIP kernel running from flash to save RAM
* footprint.
- * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
/*
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index 697796a1143..33159d31563 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -140,42 +140,37 @@
#define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0"
#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)"
-#if 0
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_BOOTD | \
- CFG_CMD_DHCP | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_LOADB | \
- CFG_CMD_NET | \
- CFG_CMD_MEMORY | \
- CFG_CMD_PING | \
- CFG_CMD_RUN)
-#else
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_BOOTD | \
- CFG_CMD_DHCP | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_NAND | \
- CFG_CMD_IMI | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_LOADB | \
- CFG_CMD_NET | \
- CFG_CMD_MEMORY | \
- CFG_CMD_PING | \
- CFG_CMD_RUN)
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#endif
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-#define CONFIG_LOOPW
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_LOOPW
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h
index 0b1541d5c34..1d691f9731d 100644
--- a/include/configs/ns9750dev.h
+++ b/include/configs/ns9750dev.h
@@ -69,33 +69,28 @@
#define CONFIG_BAUDRATE 38400
-/***********************************************************
- * Command definition
- ***********************************************************/
-#if 0 /* @TODO */
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_CACHE | \
- /*CFG_CMD_NAND |*/ \
- /*CFG_CMD_EEPROM |*/ \
- /*CFG_CMD_I2C |*/ \
- /*CFG_CMD_USB |*/ \
- CFG_CMD_REGINFO | \
- CFG_CMD_DATE | \
- CFG_CMD_ELF)
-#else
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_BDI | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CFG_CMD_CONSOLE | \
- CFG_CMD_LOADB | \
- CFG_CMD_LOADS | \
- CFG_CMD_MEMORY)
-#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+
#define CONFIG_BOOTDELAY 3
/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
@@ -108,7 +103,7 @@
/*#define CONFIG_BOOTFILE "elinos-lart" */
/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 5c05a745dbb..f1d73e4c539 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -37,11 +37,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -73,8 +68,6 @@
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
-#define ADD_PCI_CMD CFG_CMD_PCI
-
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -82,20 +75,29 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- ADD_PCI_CMD )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PCI
+
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CFG_LOWBOOT 1
@@ -137,17 +139,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
#endif
@@ -246,7 +248,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -262,6 +264,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
@@ -276,7 +283,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
/*
* For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
*/
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
index fe4e63810ee..bc2fd33ff5e 100644
--- a/include/configs/ocotea.h
+++ b/include/configs/ocotea.h
@@ -41,6 +41,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_OCOTEA 1 /* Board is ebony */
#define CONFIG_440GX 1 /* Specifc GX support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
@@ -136,7 +137,7 @@
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
@@ -231,26 +232,38 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -259,7 +272,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -293,7 +306,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
@@ -310,7 +322,7 @@
*/
#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -322,7 +334,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h
index 016d3d8bd02..8623ed3cc88 100644
--- a/include/configs/omap1510inn.h
+++ b/include/configs/omap1510inn.h
@@ -86,11 +86,24 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+
#include <configs/omap1510.h>
#define CONFIG_BOOTDELAY 3
@@ -98,7 +111,7 @@
#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
#define CFG_AUTOLOAD "n" /* No autoload */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h
index c6ca689a5fe..74bba05fe8a 100644
--- a/include/configs/omap1610h2.h
+++ b/include/configs/omap1610h2.h
@@ -81,11 +81,24 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+
#include <configs/omap1510.h>
#define CONFIG_BOOTDELAY 3
@@ -93,7 +106,7 @@
#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
#define CFG_AUTOLOAD "n" /* No autoload */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h
index f28ede09674..734f3543927 100644
--- a/include/configs/omap1610inn.h
+++ b/include/configs/omap1610inn.h
@@ -82,11 +82,24 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+
#include <configs/omap1510.h>
#define CONFIG_BOOTDELAY 3
@@ -98,7 +111,7 @@
#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */
#define CONFIG_BOOTFILE "uImage" /* file to load */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
index 58374616a14..8ae8efeb817 100644
--- a/include/configs/omap2420h4.h
+++ b/include/configs/omap2420h4.h
@@ -119,15 +119,34 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#ifdef CFG_NAND_BOOT
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2)
+ #define CONFIG_CMD_DHCP
+ #define CONFIG_CMD_I2C
+ #define CONFIG_CMD_NAND
+ #define CONFIG_CMD_JFFS2
#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT)
+ #define CONFIG_CMD_DHCP
+ #define CONFIG_CMD_I2C
+ #define CONFIG_CMD_JFFS2
+
+ #undef CONFIG_CMD_AUTOSCRIPT
#endif
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
/*
* Board NAND Info.
diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h
index 5db4f52beb6..16ce2f61aec 100644
--- a/include/configs/omap5912osk.h
+++ b/include/configs/omap5912osk.h
@@ -86,11 +86,24 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+
#include <configs/omap1510.h>
#define CONFIG_BOOTDELAY 3
@@ -102,7 +115,7 @@
#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */
#define CONFIG_BOOTFILE "uImage" /* file to load */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h
index fda55cf06fd..c4d253af45c 100644
--- a/include/configs/omap730p2.h
+++ b/include/configs/omap730p2.h
@@ -90,14 +90,24 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
/*
- * This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ * Command line configuration.
*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
-#include <cmd_confdefs.h>
#include <configs/omap730.h>
#include <configs/h2_p2_dbg_board.h>
@@ -112,7 +122,7 @@
#define CONFIG_SERVERIP 192.150.0.100
#define CONFIG_BOOTFILE "uImage" /* File to load */
-#if defined (CONFIG_COMMANDS) && defined (CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
#endif
diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h
index 54462f007cd..bec442d9839 100644
--- a/include/configs/p3mx.h
+++ b/include/configs/p3mx.h
@@ -60,7 +60,6 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
-#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
@@ -251,26 +250,36 @@
#endif
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_PCI | \
- CFG_CMD_CACHE | \
- CFG_CMD_SDRAM)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_SDRAM
+
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
@@ -280,7 +289,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -421,7 +430,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
index aa0901f3ff4..51f19a1456c 100644
--- a/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@ -35,6 +35,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_P3P440 1 /* Board is P3P440 */
#define CONFIG_440GP 1 /* Specifc GP support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
@@ -167,25 +168,37 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -194,7 +207,7 @@
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -226,7 +239,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/
@@ -285,7 +297,7 @@
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -304,7 +316,7 @@
*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -316,7 +328,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index ed1893f5742..810e0f04628 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -132,11 +132,8 @@
/*---USB -------------------------------------------*/
#if 0
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
-#else
-#define ADD_USB_CMD 0
#endif
/*---ATA PCMCIA ------------------------------------*/
@@ -179,11 +176,36 @@
#define CFG_ICACHE_SIZE 16384
#define CFG_CACHELINE_SIZE 32
-#define CONFIG_COMMANDS \
- (((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_PING) & \
- ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | CFG_CMD_IDE | \
- CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \
- CFG_CMD_BDI | CFG_CMD_BEDBUG)) | ADD_USB_CMD)
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_RUN
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_BEDBUG
#endif /* __CONFIG_H */
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index 23bdfc8dfb9..7653ba1d245 100644
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -32,6 +32,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_PCS440EP 1 /* Board is PCS440EP */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
@@ -103,21 +104,28 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+#define CONFIG_ENV_OVERWRITE 1
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */
+#define ENV_NAME_REVLEV "revision_level"
+#define ENV_NAME_SOLDER "solder_switch"
+#define ENV_NAME_DIP "dip"
+
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
#undef CONFIG_DDR_ECC /* don't use ECC */
#define SPD_EEPROM_ADDRESS {0x50}
+#define CONFIG_PROG_SDRAM_TLB 1
/*-----------------------------------------------------------------------
* I2C
@@ -142,6 +150,8 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=pcs440ep\0" \
+ "use_eeprom_ethaddr=default\0" \
+ "cs_test=off\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@@ -172,6 +182,36 @@
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+/* check U-Boot image with SHA1 sum */
+#define CONFIG_SHA1_CHECK_UB_IMG 1
+#define CONFIG_SHA1_START CFG_MONITOR_BASE
+#define CONFIG_SHA1_LEN CFG_MONITOR_LEN
+
+/*-----------------------------------------------------------------------
+ * Definitions for status LED
+ */
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED 1
+
+#define STATUS_LED_BIT 0x08 /* DIAG1 is on GPIO_PPC_1 */
+#define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
+#define STATUS_LED_STATE STATUS_LED_OFF
+#define STATUS_LED_BIT1 0x04 /* DIAG2 is on GPIO_PPC_2 */
+#define STATUS_LED_PERIOD1 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
+#define STATUS_LED_STATE1 STATUS_LED_ON
+#define STATUS_LED_BIT2 0x02 /* DIAG3 is on GPIO_PPC_3 */
+#define STATUS_LED_PERIOD2 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
+#define STATUS_LED_STATE2 STATUS_LED_OFF
+#define STATUS_LED_BIT3 0x01 /* DIAG4 is on GPIO_PPC_4 */
+#define STATUS_LED_PERIOD3 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
+#define STATUS_LED_STATE3 STATUS_LED_OFF
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
@@ -207,37 +247,48 @@
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FAT | \
- CFG_CMD_USB )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_SUPPORT_VFAT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_REISER
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_USB
+
+#define CONFIG_SUPPORT_VFAT
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -266,7 +317,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
@@ -315,76 +365,76 @@
/*-----------------------------------------------------------------------
* PPC440 GPIO Configuration
*/
-#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \
+#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
{ \
/* GPIO Core 0 */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6 EBC_CS_N(1) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7 EBC_CS_N(2) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8 EBC_CS_N(3) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9 EBC_CS_N(4) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO10 EBC_CS_N(5) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO11 EBC_BUS_ERR */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO12 ZII_p0Rxd(0) */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO13 ZII_p0Rxd(1) */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO14 ZII_p0Rxd(2) */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO15 ZII_p0Rxd(3) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16 ZII_p0Txd(0) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17 ZII_p0Txd(1) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18 ZII_p0Txd(2) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19 ZII_p0Txd(3) */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO20 ZII_p0Rx_er */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO21 ZII_p0Rx_dv */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO22 ZII_p0RxCrs */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23 ZII_p0Tx_er */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24 ZII_p0Tx_en */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO25 ZII_p0Col */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO26 USB2D_RXVALID */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO28 USB2D_TXVALID */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
}, \
{ \
/* GPIO Core 1 */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO32 USB2D_OPMODE0 */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO33 USB2D_OPMODE1 */ \
-{ GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT3 }, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \
-{ GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37 UART0_RTS_N */ \
-{ GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT2 }, /* GPIO39 UART0_RI_N UART1_SIN */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO40 UIC_IRQ(0) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO41 UIC_IRQ(1) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO42 UIC_IRQ(2) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO43 UIC_IRQ(3) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
-{ GPIO1_BASE, GPIO_BI, GPIO_SEL }, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO49 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO50 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO51 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO52 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO53 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO54 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO55 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO56 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO57 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO58 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO59 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO60 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO61 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO62 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO63 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
+{GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \
} \
}
@@ -393,7 +443,7 @@
*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -405,9 +455,38 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
+
+#define CONFIG_IDE_PREINIT 1
+#define CONFIG_IDE_RESET 1
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR CFG_CF1
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET 0
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET (0x0000)
+
#endif /* __CONFIG_H */
diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h
index 73aa3a88259..e3c884392c7 100644
--- a/include/configs/pcu_e.h
+++ b/include/configs/pcu_e.h
@@ -89,28 +89,34 @@
* ---------------------------------------------------------------- */
#define CFG_SPI_INIT_OFFSET 0xB00
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#define CONFIG_BOOTP_MASK \
- ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-/*----------------------------------------------------------------------*/
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index 06c66528784..5b5b0efb76a 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -71,25 +71,33 @@
#define CONFIG_BAUDRATE 115200
#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
-#if defined(CONFIG_SCPU)
-#define CMD_NAND_ADD 0
-#else
-#define CMD_NAND_ADD CFG_CMD_NAND
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_PING
+
+#if !defined(CONFIG_SCPU)
+#define CONFIG_CMD_NAND
#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_NET | \
- CFG_CMD_MII | \
- CMD_NAND_ADD | \
- CFG_CMD_I2C | \
- CFG_CMD_ELF | \
- CFG_CMD_PING)
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-/* These are u-boot generic parameters */
-#include <cmd_confdefs.h>
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
index fefdb3cca01..18d0c879a9e 100644
--- a/include/configs/pf5200.h
+++ b/include/configs/pf5200.h
@@ -49,11 +49,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -90,13 +85,6 @@
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#endif
-
-#define ADD_PCI_CMD CFG_CMD_PCI
-
-#else /* MPC5100 */
-
-#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
-
#endif
/* Partitions */
@@ -106,26 +94,35 @@
/* USB */
#if 0
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_BSP | \
- CFG_CMD_ELF | \
- ADD_PCI_CMD )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+
+#ifdef CONFIG_MPC5200
+#define CONFIG_CMD_PCI
+#endif
+
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CFG_LOWBOOT 1
@@ -171,7 +168,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
* I2C configuration
@@ -263,7 +260,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -281,6 +278,11 @@
#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h
index a6c23712b5d..863029d146d 100644
--- a/include/configs/pleb2.h
+++ b/include/configs/pleb2.h
@@ -66,10 +66,23 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NET
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
@@ -83,7 +96,7 @@
#define CONFIG_INITRD_TAG
#define CONFIG_SETUP_MEMORY_TAGS
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h
index 072b9dd5b46..fe7de7bed0f 100644
--- a/include/configs/ppmc7xx.h
+++ b/include/configs/ppmc7xx.h
@@ -25,75 +25,91 @@
/*
* Debug
*
- * DEBUG - Define this is you want extra debug info
- * GTREGREAD - Required to build with debug
- * do_bdinfo - Required to build with debug
+ * DEBUG - Define this is you want extra debug info
+ * GTREGREAD - Required to build with debug
+ * do_bdinfo - Required to build with debug
*/
#undef DEBUG
-#define GTREGREAD(x) 0xFFFFFFFF
+#ifdef DEBUG
+#define GTREGREAD(x) 0xFFFFFFFF
#define do_bdinfo(a,b,c,d)
-
+#endif
/*
* CPU type
*
- * CONFIG_7xx - We have a 750 or 755 CPU
- * CONFIG_74xx - We have a 7400 CPU
- * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
- * CONFIG_BUS_CLK - System bus clock in Hz
+ * CONFIG_7xx - We have a 750 or 755 CPU
+ * CONFIG_74xx - We have a 7400 CPU
+ * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
+ * CONFIG_BUS_CLK - System bus clock in Hz
*/
#define CONFIG_7xx
#undef CONFIG_74xx
#undef CONFIG_ALTIVEC
-#define CONFIG_BUS_CLK 66000000
+#define CONFIG_BUS_CLK 66000000
/*
* Monitor configuration
*
- * CONFIG_COMMANDS - List of command sets to include in shell
+ * List of command sets to include in shell
*
* The following command sets have been tested and known to work:
*
- * CFG_CMD_CACHE - Cache control commands
- * CFG_CMD_MEMORY - Memory display, change and test commands
- * CFG_CMD_FLASH - Erase and program flash
- * CFG_CMD_ENV - Environment commands
- * CFG_CMD_RUN - Run commands stored in env vars
- * CFG_CMD_ELF - Load ELF files
- * CFG_CMD_NET - Networking/file download commands
- * CFG_CMD_PING - ICMP Echo Request command
- * CFG_CMD_PCI - PCI Bus scanning command
+ * CMD_CACHE - Cache control commands
+ * CMD_MEMORY - Memory display, change and test commands
+ * CMD_FLASH - Erase and program flash
+ * CMD_ENV - Environment commands
+ * CMD_RUN - Run commands stored in env vars
+ * CMD_ELF - Load ELF files
+ * CMD_NET - Networking/file download commands
+ * CMD_PIN - ICMP Echo Request command
+ * CMD_PCI - PCI Bus scanning command
*/
-#define CONFIG_COMMANDS ( (CFG_CMD_DFL & ~(CFG_CMD_KGDB)) | \
- CFG_CMD_FLASH | \
- CFG_CMD_ENV | \
- CFG_CMD_RUN | \
- CFG_CMD_ELF | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CFG_CMD_PCI)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PCI
+
+#undef CONFIG_CMD_KGDB
/*
* Serial configuration
*
* CONFIG_CONS_INDEX - Serial console port number (COM1)
- * CONFIG_BAUDRATE - Serial speed
+ * CONFIG_BAUDRATE - Serial speed
*/
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 9600
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 9600
/*
* PCI config
*
- * CONFIG_PCI - Enable PCI bus
- * CONFIG_PCI_PNP - Enable Plug & Play support
+ * CONFIG_PCI - Enable PCI bus
+ * CONFIG_PCI_PNP - Enable Plug & Play support
* CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
*/
@@ -105,9 +121,9 @@
/*
* Network config
*
- * CONFIG_NET_MULTI - Support for multiple network interfaces
- * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
- * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
+ * CONFIG_NET_MULTI - Support for multiple network interfaces
+ * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
+ * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
*/
#define CONFIG_NET_MULTI
@@ -130,7 +146,7 @@
* Boot config
*
* CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
- * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
+ * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
*/
#define CONFIG_BOOTCOMMAND \
@@ -149,87 +165,84 @@
*/
-#include <cmd_confdefs.h>
-
-
/*
* Memory map
*
* This board runs in a standard CHRP (Map-B) configuration.
*
- * Type Start End Size Width Chip Sel
+ * Type Start End Size Width Chip Sel
* ----------- ----------- ----------- ------- ------- --------
- * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
- * User LED's 0x78000000 RCS3
- * UART 0x7C000000 RCS2
- * Mailbox 0xFF000000 RCS1
- * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
+ * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
+ * User LED's 0x78000000 RCS3
+ * UART 0x7C000000 RCS2
+ * Mailbox 0xFF000000 RCS1
+ * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
*
* Flash sectors are laid out as follows.
*
- * Sector Start End Size Comments
+ * Sector Start End Size Comments
* ------- ----------- ----------- ------- -----------
- * 0 0xFFC00000 0xFFC3FFFF 256KB
- * 1 0xFFC40000 0xFFC7FFFF 256KB
- * 2 0xFFC80000 0xFFCBFFFF 256KB
- * 3 0xFFCC0000 0xFFCFFFFF 256KB
- * 4 0xFFD00000 0xFFD3FFFF 256KB
- * 5 0xFFD40000 0xFFD7FFFF 256KB
- * 6 0xFFD80000 0xFFDBFFFF 256KB
- * 7 0xFFDC0000 0xFFDFFFFF 256KB
- * 8 0xFFE00000 0xFFE3FFFF 256KB
- * 9 0xFFE40000 0xFFE7FFFF 256KB
- * 10 0xFFE80000 0xFFEBFFFF 256KB
- * 11 0xFFEC0000 0xFFEFFFFF 256KB
- * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
- * 13 0xFFF40000 0xFFF7FFFF 256KB
- * 14 0xFFF80000 0xFFFBFFFF 256KB
- * 15 0xFFFC0000 0xFFFDFFFF 128KB
- * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
- * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
- * 18 0xFFFF0000 0xFFFFFFFF 64KB
+ * 0 0xFFC00000 0xFFC3FFFF 256KB
+ * 1 0xFFC40000 0xFFC7FFFF 256KB
+ * 2 0xFFC80000 0xFFCBFFFF 256KB
+ * 3 0xFFCC0000 0xFFCFFFFF 256KB
+ * 4 0xFFD00000 0xFFD3FFFF 256KB
+ * 5 0xFFD40000 0xFFD7FFFF 256KB
+ * 6 0xFFD80000 0xFFDBFFFF 256KB
+ * 7 0xFFDC0000 0xFFDFFFFF 256KB
+ * 8 0xFFE00000 0xFFE3FFFF 256KB
+ * 9 0xFFE40000 0xFFE7FFFF 256KB
+ * 10 0xFFE80000 0xFFEBFFFF 256KB
+ * 11 0xFFEC0000 0xFFEFFFFF 256KB
+ * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
+ * 13 0xFFF40000 0xFFF7FFFF 256KB
+ * 14 0xFFF80000 0xFFFBFFFF 256KB
+ * 15 0xFFFC0000 0xFFFDFFFF 128KB
+ * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
+ * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
+ * 18 0xFFFF0000 0xFFFFFFFF 64KB
*/
/*
* SDRAM config - see memory map details above.
*
- * CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
- * CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
+ * CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
+ * CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
*/
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 0x04000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_SIZE 0x04000000
/*
* Flash config - see memory map details above.
*
- * CFG_FLASH_BASE - Start address of flash memory
- * CFG_FLASH_SIZE - Total size of contiguous flash mem
+ * CFG_FLASH_BASE - Start address of flash memory
+ * CFG_FLASH_SIZE - Total size of contiguous flash mem
* CFG_FLASH_ERASE_TOUT - Erase timeout in ms
* CFG_FLASH_WRITE_TOUT - Write timeout in ms
* CFG_MAX_FLASH_BANKS - Number of banks of flash on board
* CFG_MAX_FLASH_SECT - Number of sectors in a bank
*/
-#define CFG_FLASH_BASE 0xFFC00000
-#define CFG_FLASH_SIZE 0x00400000
+#define CFG_FLASH_BASE 0xFFC00000
+#define CFG_FLASH_SIZE 0x00400000
#define CFG_FLASH_ERASE_TOUT 250000
#define CFG_FLASH_WRITE_TOUT 5000
-#define CFG_MAX_FLASH_BANKS 1
-#define CFG_MAX_FLASH_SECT 19
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 19
/*
* Monitor config - see memory map details above
*
- * CFG_MONITOR_BASE - Base address of monitor code
- * CFG_MALLOC_LEN - Size of malloc pool (128KB)
+ * CFG_MONITOR_BASE - Base address of monitor code
+ * CFG_MALLOC_LEN - Size of malloc pool (128KB)
*/
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MALLOC_LEN 0x20000
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MALLOC_LEN 0x20000
/*
@@ -247,16 +260,16 @@
* CFG_PROMPT - Prompt string
*/
-#define CFG_BARGSIZE 1024
-#define CFG_BOOTMAPSZ 0x800000
-#define CFG_CBSIZE 1024
-#define CFG_LOAD_ADDR 0x100000
+#define CFG_BARGSIZE 1024
+#define CFG_BOOTMAPSZ 0x800000
+#define CFG_CBSIZE 1024
+#define CFG_LOAD_ADDR 0x100000
#define CFG_LONGHELP
-#define CFG_MAXARGS 16
-#define CFG_MEMTEST_START 0x00040000
-#define CFG_MEMTEST_END 0x00040100
-#define CFG_PBSIZE 1024
-#define CFG_PROMPT "=> "
+#define CFG_MAXARGS 16
+#define CFG_MEMTEST_START 0x00040000
+#define CFG_MEMTEST_END 0x00040100
+#define CFG_PBSIZE 1024
+#define CFG_PROMPT "=> "
/*
@@ -268,12 +281,12 @@
* CFG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
*/
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR 0xFFFE0000
-#define CFG_ENV_SIZE 0x1000
-#define CFG_ENV_ADDR_REDUND 0xFFFE8000
-#define CFG_ENV_SIZE_REDUND 0x1000
-#define CFG_ENV_SECT_SIZE 0x8000
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0xFFFE0000
+#define CFG_ENV_SIZE 0x1000
+#define CFG_ENV_ADDR_REDUND 0xFFFE8000
+#define CFG_ENV_SIZE_REDUND 0x1000
+#define CFG_ENV_SECT_SIZE 0x8000
/*
@@ -284,15 +297,15 @@
* copied to top of RAM by the init code.
*
* CFG_INIT_RAM_ADDR - Address of Init RAM, above exception vect
- * CFG_INIT_RAM_END - Size of Init RAM
+ * CFG_INIT_RAM_END - Size of Init RAM
* CFG_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
* CFG_GBL_DATA_OFFSET - Start of global data, top of stack
*/
-#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + 0x4000)
-#define CFG_INIT_RAM_END 0x4000
-#define CFG_GBL_DATA_SIZE 128
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + 0x4000)
+#define CFG_INIT_RAM_END 0x4000
+#define CFG_GBL_DATA_SIZE 128
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/*
@@ -329,71 +342,71 @@
* Cache config
*
* CFG_CACHELINE_SIZE - Size of a cache line (CPU specific)
- * CFG_L2 - L2 cache enabled if defined
- * L2_INIT - L2 cache init flags
- * L2_ENABLE - L2 cache enable flags
+ * CFG_L2 - L2 cache enabled if defined
+ * L2_INIT - L2 cache init flags
+ * L2_ENABLE - L2 cache enable flags
*/
-#define CFG_CACHELINE_SIZE 32
+#define CFG_CACHELINE_SIZE 32
#undef CFG_L2
-#define L2_INIT 0
-#define L2_ENABLE 0
+#define L2_INIT 0
+#define L2_ENABLE 0
/*
* Clocks config
*
- * CFG_BUS_HZ - Bus clock frequency in Hz
- * CFG_BUS_CLK - As above (?)
- * CFG_HZ - Decrementer freq in Hz
+ * CFG_BUS_HZ - Bus clock frequency in Hz
+ * CFG_BUS_CLK - As above (?)
+ * CFG_HZ - Decrementer freq in Hz
*/
-#define CFG_BUS_HZ CONFIG_BUS_CLK
-#define CFG_BUS_CLK CONFIG_BUS_CLK
-#define CFG_HZ 1000
+#define CFG_BUS_HZ CONFIG_BUS_CLK
+#define CFG_BUS_CLK CONFIG_BUS_CLK
+#define CFG_HZ 1000
/*
* Serial port config
*
* CFG_BAUDRATE_TABLE - List of valid baud rates
- * CFG_NS16550 - Include the NS16550 driver
+ * CFG_NS16550 - Include the NS16550 driver
* CFG_NS16550_SERIAL - Include the serial (wrapper) driver
- * CFG_NS16550_CLK - Frequency of reference clock
+ * CFG_NS16550_CLK - Frequency of reference clock
* CFG_NS16550_REG_SIZE - 64-bit accesses to 8-bit port
- * CFG_NS16550_COM1 - Base address of 1st serial port
+ * CFG_NS16550_COM1 - Base address of 1st serial port
*/
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_NS16550
#define CFG_NS16550_SERIAL
-#define CFG_NS16550_CLK 3686400
+#define CFG_NS16550_CLK 3686400
#define CFG_NS16550_REG_SIZE -8
-#define CFG_NS16550_COM1 0x7C000000
+#define CFG_NS16550_COM1 0x7C000000
/*
* PCI Config - Address Map B (CHRP)
*/
-#define CFG_PCI_MEMORY_BUS 0x00000000
-#define CFG_PCI_MEMORY_PHYS 0x00000000
-#define CFG_PCI_MEMORY_SIZE 0x40000000
-#define CFG_PCI_MEM_BUS 0x80000000
-#define CFG_PCI_MEM_PHYS 0x80000000
-#define CFG_PCI_MEM_SIZE 0x7D000000
-#define CFG_ISA_MEM_BUS 0x00000000
-#define CFG_ISA_MEM_PHYS 0xFD000000
-#define CFG_ISA_MEM_SIZE 0x01000000
-#define CFG_PCI_IO_BUS 0x00800000
-#define CFG_PCI_IO_PHYS 0xFE800000
-#define CFG_PCI_IO_SIZE 0x00400000
-#define CFG_ISA_IO_BUS 0x00000000
-#define CFG_ISA_IO_PHYS 0xFE000000
-#define CFG_ISA_IO_SIZE 0x00800000
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x40000000
+#define CFG_PCI_MEM_BUS 0x80000000
+#define CFG_PCI_MEM_PHYS 0x80000000
+#define CFG_PCI_MEM_SIZE 0x7D000000
+#define CFG_ISA_MEM_BUS 0x00000000
+#define CFG_ISA_MEM_PHYS 0xFD000000
+#define CFG_ISA_MEM_SIZE 0x01000000
+#define CFG_PCI_IO_BUS 0x00800000
+#define CFG_PCI_IO_PHYS 0xFE800000
+#define CFG_PCI_IO_SIZE 0x00400000
+#define CFG_ISA_IO_BUS 0x00000000
+#define CFG_ISA_IO_PHYS 0xFE000000
+#define CFG_ISA_IO_SIZE 0x00800000
#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
-#define CFG_ISA_IO CFG_ISA_IO_PHYS
-#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
+#define CFG_ISA_IO CFG_ISA_IO_PHYS
+#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
/*
@@ -408,12 +421,12 @@
/*
* Boot flags
*
- * BOOTFLAG_COLD - Indicates a power-on boot
- * BOOTFLAG_WARM - Indicates a software reset
+ * BOOTFLAG_COLD - Indicates a power-on boot
+ * BOOTFLAG_WARM - Indicates a software reset
*/
-#define BOOTFLAG_COLD 0x01
-#define BOOTFLAG_WARM 0x02
+#define BOOTFLAG_COLD 0x01
+#define BOOTFLAG_WARM 0x02
#endif /* __CONFIG_H */
diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h
index d671dccc19b..fb5ae99e4cc 100644
--- a/include/configs/ppmc8260.h
+++ b/include/configs/ppmc8260.h
@@ -169,8 +169,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
@@ -261,13 +260,17 @@
"bootm"
#endif /* CONFIG_BOOT_ROOT_NFS */
-/* Add support for a few extra bootp options like:
- * - File size
- * - DNS
+
+/*
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE | \
- CONFIG_BOOTP_DNS)
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+
/* undef this to save memory */
#define CFG_LONGHELP
@@ -275,14 +278,20 @@
/* Monitor Command Prompt */
#define CFG_PROMPT "=> "
-/* What U-Boot subsytems do you want enabled? */
-#define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
- CFG_CMD_ELF | \
- CFG_CMD_ASKENV | \
- CFG_CMD_REGINFO | \
- CFG_CMD_MEMTEST | \
- CFG_CMD_MII | \
- CFG_CMD_IMMAP)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_IMMAP
+
+#undef CONFIG_CMD_KGDB
/* Where do the internal registers live? */
@@ -298,13 +307,10 @@
#define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -477,7 +483,7 @@
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/purple.h b/include/configs/purple.h
index 2ecb7fb2bf7..6eb618ed6d3 100644
--- a/include/configs/purple.h
+++ b/include/configs/purple.h
@@ -81,8 +81,23 @@
""
#define CONFIG_BOOTCOMMAND "run flash_self"
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF)
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+
#define CFG_SDRAM_BASE 0x80000000
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index e5e27724e18..0e884fc114c 100644
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -102,10 +102,25 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_DHCP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_DHCP
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND "bootm 40000"
@@ -192,7 +207,7 @@
/* "protect off" */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/quantum.h b/include/configs/quantum.h
index 21ec5acadef..f49e2b0716e 100644
--- a/include/configs/quantum.h
+++ b/include/configs/quantum.h
@@ -92,18 +92,28 @@
#define CFG_NVRAM_SIZE 2048
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
@@ -113,7 +123,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -172,7 +182,7 @@
#endif
/*%%% #define CFG_FLASH_BASE 0xFFF00000 */
-#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
@@ -222,7 +232,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/r5200.h b/include/configs/r5200.h
index e1e406bf9b5..fc7658b9f2d 100644
--- a/include/configs/r5200.h
+++ b/include/configs/r5200.h
@@ -39,13 +39,10 @@
#define CONFIG_M5271 /* define processor type */
#define CONFIG_R5200 /* define board type */
-#define FEC_ENET
-#define CONFIG_NET_RETRY_COUNT 5
-
-#define CONFIG_IPADDR 192.168.0.172
-#define CONFIG_SERVERIP 192.168.0.148
-#define CONFIG_ETHADDR 00:06:3b:00:44:55
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
@@ -66,10 +63,48 @@
#define CFG_ENV_IS_IN_FLASH 1
#endif
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_NET ) & ~(CFG_CMD_LOADS | CFG_CMD_LOADB))
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NET
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
/* Note: We only copy one sectors worth of application code from location
* 10200000 for speed purposes. Increase the size if necessary */
@@ -79,7 +114,7 @@
#define CFG_PROMPT "u-boot> "
#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/rmu.h b/include/configs/rmu.h
index b319cf497d3..2ca60b731ea 100644
--- a/include/configs/rmu.h
+++ b/include/configs/rmu.h
@@ -87,17 +87,28 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
@@ -108,7 +119,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -152,7 +163,7 @@
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE (0-flash_info[0].size) /* Put flash at end */
-#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
@@ -193,7 +204,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h
index 6c9e392c36b..814082ccc63 100644
--- a/include/configs/rsdproto.h
+++ b/include/configs/rsdproto.h
@@ -64,8 +64,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
@@ -102,7 +101,23 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_KGDB)
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_KGDB
+
/* Define this if you want to boot from 0x00000100. If you don't define
* this, you will need to program the bootloader to 0xfff00000, and
@@ -112,15 +127,12 @@
*/
#define CFG_RSD_BOOT_LOW 1
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOTARGS "devfs=mount root=ramfs"
#define CONFIG_ETHADDR 08:00:3e:26:0a:5a
#define CONFIG_NETMASK 255.255.0.0
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -130,7 +142,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -287,7 +299,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index 97b52fa1ae7..c474acd70ec 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -159,8 +159,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC
@@ -470,16 +469,18 @@
#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */
-/* Add support for a few extra bootp options like:
- * - File size
- * - DNS (up to 2 servers)
- * - Send hostname to DHCP server
+/*
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME)
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
/* undef this to save memory */
#define CFG_LONGHELP
@@ -502,31 +503,28 @@
*/
#define CONFIG_VERSION_VARIABLE
-/* What U-Boot subsytems do you want enabled? */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_KGDB
+
#ifdef CONFIG_ETHER_ON_FCC
-# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
- CFG_CMD_ELF | \
- CFG_CMD_ASKENV | \
- CFG_CMD_I2C | \
- CFG_CMD_SPI | \
- CFG_CMD_SDRAM | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_IRQ | \
- CFG_CMD_PING | \
- CFG_CMD_MII )
-#else
-# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
- CFG_CMD_ELF | \
- CFG_CMD_ASKENV | \
- CFG_CMD_I2C | \
- CFG_CMD_SPI | \
- CFG_CMD_SDRAM | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_IRQ | \
- CFG_CMD_PING )
-#endif /* CONFIG_ETHER_ON_FCC */
+#define CONFIG_CMD_MII
+#endif
+
/* Where do the internal registers live? */
#define CFG_IMMR 0xF0000000
@@ -544,10 +542,6 @@
#define CONFIG_SACSng 1 /* munged for the SACSng */
#define CONFIG_CPM2 1 /* Has a CPM2 */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-
/*
* Miscellaneous configurable options
*/
@@ -589,7 +583,7 @@
#define CFG_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */
/* before it gives up. */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -732,7 +726,7 @@
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
index 866f7b04261..b4a063a1d4c 100644
--- a/include/configs/sbc2410x.h
+++ b/include/configs/sbc2410x.h
@@ -82,24 +82,29 @@
#define CONFIG_BAUDRATE 115200
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_CACHE | \
- /*CFG_CMD_NAND |*/ \
- /*CFG_CMD_EEPROM |*/ \
- /*CFG_CMD_I2C |*/ \
- /*CFG_CMD_USB |*/ \
- CFG_CMD_REGINFO | \
- CFG_CMD_DATE | \
- CFG_CMD_PING | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
@@ -110,7 +115,7 @@
/*#define CONFIG_BOOTFILE "elinos-lart" */
#define CONFIG_BOOTCOMMAND "dhcp; bootm"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
@@ -193,7 +198,7 @@
/*-----------------------------------------------------------------------
* NAND flash settings
*/
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
@@ -219,7 +224,7 @@
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
-#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
+#endif /* CONFIG_CMD_NAND */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h
index beff28ab32f..dc906b15006 100644
--- a/include/configs/sbc405.h
+++ b/include/configs/sbc405.h
@@ -84,23 +84,33 @@
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BSP | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_SDRAM | \
- 0 )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -123,7 +133,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -229,7 +239,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/sbc8240.h b/include/configs/sbc8240.h
index d891e07b314..0e878f054ff 100644
--- a/include/configs/sbc8240.h
+++ b/include/configs/sbc8240.h
@@ -75,24 +75,33 @@
#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BSP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_SDRAM | \
- 0 )
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+
+/*
+ * Command line configuration.
*/
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+
/*
* Miscellaneous configurable options
@@ -340,7 +349,7 @@ typedef unsigned int led_id_t;
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h
index 9cf0654be10..b1d41a6d42b 100644
--- a/include/configs/sbc8260.h
+++ b/include/configs/sbc8260.h
@@ -182,8 +182,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC
@@ -412,16 +411,18 @@
"bootm"
#endif /* CONFIG_BOOT_ROOT_NFS */
-/* Add support for a few extra bootp options like:
- * - File size
- * - DNS (up to 2 servers)
- * - Send hostname to DHCP server
+/*
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME)
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
/* undef this to save memory */
#define CFG_LONGHELP
@@ -444,27 +445,26 @@
*/
#define CONFIG_VERSION_VARIABLE
-/* What U-Boot subsytems do you want enabled? */
-#ifdef CONFIG_ETHER_ON_FCC
-# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
- CFG_CMD_ASKENV | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IMMAP | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM )
-#else
-# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
- CFG_CMD_ASKENV | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IMMAP | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM )
-#endif /* CONFIG_ETHER_ON_FCC */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+#undef CONFIG_CMD_KGDB
+
+#if defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_CMD_CMD_MII
+#endif
+
#undef CONFIG_WATCHDOG /* disable the watchdog */
@@ -481,13 +481,11 @@
#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -627,7 +625,7 @@
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 65aac5cefd3..e7d8a5a6627 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -313,9 +313,6 @@
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8349@0"
#define OF_SOC "soc8349@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
@@ -328,7 +325,7 @@
#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C1_OFFSET 0x3000
#define CFG_I2C2_OFFSET 0x3100
#define CFG_I2C_OFFSET CFG_I2C2_OFFSET
@@ -401,15 +398,17 @@
#define CONFIG_NET_MULTI 1
#endif
-#define CONFIG_MPC83XX_TSEC1 1
-#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC83XX_TSEC2 1
-#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_PHY_BCM5421S 1
#define TSEC1_PHY_ADDR 0x19
#define TSEC2_PHY_ADDR 0x1a
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
@@ -439,40 +438,34 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#if defined(CFG_RAMBOOT)
-#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#endif
-#else
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- )
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII \
- )
+ #define CONFG_CMD_PCI
#endif
+
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -483,7 +476,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -504,7 +497,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -655,7 +648,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -666,6 +659,7 @@
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:a0:1e:a0:13:8d
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index 6e4fdb2498e..defc428819b 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -320,28 +320,37 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_CMD_MII
+#endif
+
#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV | \
- CFG_CMD_LOADS ))
- #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C)
- #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C)
- #endif
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -350,7 +359,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -371,7 +380,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -383,7 +392,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
new file mode 100644
index 00000000000..54eac38b86f
--- /dev/null
+++ b/include/configs/sbc8641d.h
@@ -0,0 +1,606 @@
+/*
+ * Copyright 2007 Wind River Systems <www.windriver.com>
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Joe Hamman <joe.hamman@embeddedspecialties.com>
+ *
+ * Copyright 2006 Freescale Semiconductor.
+ *
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * SBC8641D board configuration file
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_MPC86xx 1 /* MPC86xx */
+#define CONFIG_MPC8641 1 /* MPC8641 specific */
+#define CONFIG_SBC8641D 1 /* SBC8641D board specific */
+#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
+#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
+
+#ifdef RUN_DIAG
+#define CFG_DIAG_ADDR 0xff800000
+#endif
+
+#define CFG_RESET_ADDRESS 0xfff00100
+
+#define CONFIG_PCI 1 /* Enable PCIE */
+#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
+#undef CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CACHE_LINE_INTERLEAVING 0x20000000
+#define PAGE_INTERLEAVING 0x21000000
+#define BANK_INTERLEAVING 0x22000000
+#define SUPER_BANK_INTERLEAVING 0x23000000
+
+
+#define CONFIG_ALTIVEC 1
+
+/*
+ * L2CR setup -- make sure this is right for your board!
+ */
+#define CFG_L2
+#define L2_INIT 0
+#define L2_ENABLE (L2CR_L2E)
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest region */
+#define CFG_MEMTEST_END 0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CFG_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+#define CFG_SDRAM_BASE2 CFG_DDR_SDRAM_BASE2
+#define CONFIG_VERY_BIG_RAM
+
+#define MPC86xx_DDR_SDRAM_CLK_CNTL
+
+#if defined(CONFIG_SPD_EEPROM)
+ /*
+ * Determine DDR configuration from I2C interface.
+ */
+ #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
+
+#else
+ /*
+ * Manually set up DDR1 & DDR2 parameters
+ */
+
+ #define CFG_SDRAM_SIZE 512 /* DDR is 512MB */
+
+ #define CFG_DDR_CS0_BNDS 0x0000000F
+ #define CFG_DDR_CS1_BNDS 0x00000000
+ #define CFG_DDR_CS2_BNDS 0x00000000
+ #define CFG_DDR_CS3_BNDS 0x00000000
+ #define CFG_DDR_CS0_CONFIG 0x80010102
+ #define CFG_DDR_CS1_CONFIG 0x00000000
+ #define CFG_DDR_CS2_CONFIG 0x00000000
+ #define CFG_DDR_CS3_CONFIG 0x00000000
+ #define CFG_DDR_EXT_REFRESH 0x00000000
+ #define CFG_DDR_TIMING_0 0x00220802
+ #define CFG_DDR_TIMING_1 0x38377322
+ #define CFG_DDR_TIMING_2 0x002040c7
+ #define CFG_DDR_CFG_1A 0x43008008
+ #define CFG_DDR_CFG_2 0x24401000
+ #define CFG_DDR_MODE_1 0x23c00542
+ #define CFG_DDR_MODE_2 0x00000000
+ #define CFG_DDR_MODE_CTL 0x00000000
+ #define CFG_DDR_INTERVAL 0x05080100
+ #define CFG_DDR_DATA_INIT 0x00000000
+ #define CFG_DDR_CLK_CTRL 0x03800000
+ #define CFG_DDR_CFG_1B 0xC3008008
+
+ #define CFG_DDR2_CS0_BNDS 0x0010001F
+ #define CFG_DDR2_CS1_BNDS 0x00000000
+ #define CFG_DDR2_CS2_BNDS 0x00000000
+ #define CFG_DDR2_CS3_BNDS 0x00000000
+ #define CFG_DDR2_CS0_CONFIG 0x80010102
+ #define CFG_DDR2_CS1_CONFIG 0x00000000
+ #define CFG_DDR2_CS2_CONFIG 0x00000000
+ #define CFG_DDR2_CS3_CONFIG 0x00000000
+ #define CFG_DDR2_EXT_REFRESH 0x00000000
+ #define CFG_DDR2_TIMING_0 0x00220802
+ #define CFG_DDR2_TIMING_1 0x38377322
+ #define CFG_DDR2_TIMING_2 0x002040c7
+ #define CFG_DDR2_CFG_1A 0x43008008
+ #define CFG_DDR2_CFG_2 0x24401000
+ #define CFG_DDR2_MODE_1 0x23c00542
+ #define CFG_DDR2_MODE_2 0x00000000
+ #define CFG_DDR2_MODE_CTL 0x00000000
+ #define CFG_DDR2_INTERVAL 0x05080100
+ #define CFG_DDR2_DATA_INIT 0x00000000
+ #define CFG_DDR2_CLK_CTRL 0x03800000
+ #define CFG_DDR2_CFG_1B 0xC3008008
+
+
+#endif
+
+/* #define CFG_ID_EEPROM 1
+#define ID_EEPROM_ADDR 0x57 */
+
+/*
+ * The SBC8641D contains 16MB flash space at ff000000.
+ */
+#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
+
+/* Flash */
+#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */
+#define CFG_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */
+
+/* 64KB EEPROM */
+#define CFG_BR1_PRELIM 0xf0000801 /* port size 16bit */
+#define CFG_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */
+
+/* EPLD - User switches, board id, LEDs */
+#define CFG_BR2_PRELIM 0xf1000801 /* port size 16bit */
+#define CFG_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */
+
+/* Local bus SDRAM 128MB */
+#define CFG_BR3_PRELIM 0xe0001861 /* port size ?bit */
+#define CFG_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
+#define CFG_BR4_PRELIM 0xe4001861 /* port size ?bit */
+#define CFG_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
+
+/* Disk on Chip (DOC) 128MB */
+#define CFG_BR5_PRELIM 0xe8001001 /* port size ?bit */
+#define CFG_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
+
+/* LCD */
+#define CFG_BR6_PRELIM 0xf4000801 /* port size ?bit */
+#define CFG_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
+
+/* Control logic & misc peripherals */
+#define CFG_BR7_PRELIM 0xf2000801 /* port size ?bit */
+#define CFG_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 131 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_WRITE_SWAPPED_DATA
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_PROTECTION
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#ifndef CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
+#else
+#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
+#endif
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree to kernel
+ */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,8641@0"
+#define OF_SOC "soc@f8000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc@f8000000/serial@4500"
+
+#define CFG_64BIT_VSPRINTF 1
+#define CFG_64BIT_STRTOUL 1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3100
+
+/*
+ * RapidIO MMU
+ */
+#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
+#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0xe2000000
+#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
+
+#define CFG_PCI2_MEM_BASE 0xa0000000
+#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI2_IO_BASE 0xe3000000
+#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
+#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#undef CFG_SCSI_SCAN_BUS_REVERSE
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xe0000000
+ #define PCI_ENET0_MEMADDR 0xe0000000
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#define CONFIG_DOS_PARTITION
+#undef CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CFG_SCSI_MAX_SCSI_ID 4
+#define CFG_SCSI_MAX_LUN 1
+#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
+#endif
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+/* #define CONFIG_MII 1 */ /* MII PHY management */
+
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
+#define CONFIG_TSEC4 1
+#define CONFIG_TSEC4_NAME "eTSEC4"
+
+#define TSEC1_PHY_ADDR 0x1F
+#define TSEC2_PHY_ADDR 0x00
+#define TSEC3_PHY_ADDR 0x01
+#define TSEC4_PHY_ADDR 0x02
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+#define TSEC4_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC3_FLAGS TSEC_GIGABIT
+#define TSEC4_FLAGS TSEC_GIGABIT
+
+#define CFG_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * BAT0 2G Cacheable, non-guarded
+ * 0x0000_0000 2G DDR
+ */
+#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
+#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
+#define CFG_IBAT0U CFG_DBAT0U
+
+/*
+ * BAT1 1G Cache-inhibited, guarded
+ * 0x8000_0000 512M PCI-Express 1 Memory
+ * 0xa000_0000 512M PCI-Express 2 Memory
+ * Changed it for operating from 0xd0000000
+ */
+#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U CFG_DBAT1U
+
+/*
+ * BAT2 512M Cache-inhibited, guarded
+ * 0xc000_0000 512M RapidIO Memory
+ */
+#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U CFG_DBAT2U
+
+/*
+ * BAT3 4M Cache-inhibited, guarded
+ * 0xf800_0000 4M CCSR
+ */
+#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U CFG_DBAT3U
+
+/*
+ * BAT4 32M Cache-inhibited, guarded
+ * 0xe200_0000 16M PCI-Express 1 I/O
+ * 0xe300_0000 16M PCI-Express 2 I/0
+ * Note that this is at 0xe0000000
+ */
+#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT4U CFG_DBAT4U
+
+/*
+ * BAT5 128K Cacheable, non-guarded
+ * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_IBAT5L CFG_DBAT5L
+#define CFG_IBAT5U CFG_DBAT5U
+
+/*
+ * BAT6 32M Cache-inhibited, guarded
+ * 0xfe00_0000 32M FLASH
+ */
+#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U CFG_DBAT6U
+
+#define CFG_DBAT7L 0x00000000
+#define CFG_DBAT7U 0x00000000
+#define CFG_IBAT7L 0x00000000
+#define CFG_IBAT7U 0x00000000
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+#define CFG_ENV_SIZE 0x2000
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#include <config_cmd_default.h>
+ #define CONFIG_CMD_PING
+ #define CONFIG_CMD_I2C
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR 02:E0:0C:00:00:01
+#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
+#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD
+#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD
+#endif
+
+#define CONFIG_HAS_ETH0 1
+#define CONFIG_HAS_ETH1 1
+#define CONFIG_HAS_ETH2 1
+#define CONFIG_HAS_ETH3 1
+
+#define CONFIG_IPADDR 192.168.0.50
+
+#define CONFIG_HOSTNAME sbc8641d
+#define CONFIG_ROOTPATH /opt/eldk/ppc_74xx
+#define CONFIG_BOOTFILE uImage
+
+#define CONFIG_SERVERIP 192.168.0.2
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_NETMASK 255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=uRamdisk\0" \
+ "dtbaddr=400000\0" \
+ "dtbfile=sbc8641d.dtb\0" \
+ "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+ "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+ "maxcpus=1"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr $ramdiskaddr $dtbaddr"
+
+#define CONFIG_FLASHBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "bootm ffd00000 ffb00000 ffa00000"
+
+#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index 6b6acfa8758..cb225369871 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -58,7 +58,7 @@
* 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB)
*/
-#define CONFIG_SOLIDCARD3 1
+#define CONFIG_SC3 1
#define CONFIG_4xx 1
#define CONFIG_405GP 1
@@ -68,8 +68,7 @@
* Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range
* If undefined, IDE access uses a seperat emulation with higher access speed.
* Consider to inform your Linux IDE driver about the different addresses!
- * IDE_USES_ISA_EMULATION is only used if your CONFIG_COMMANDS macro includes
- * the CFG_CMD_IDE macro!
+ * IDE_USES_ISA_EMULATION is only used if you define CONFIG_CMD_IDE!
*/
#define IDE_USES_ISA_EMULATION
@@ -134,7 +133,8 @@
#if 1 /* feel free to disable for development */
#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
#define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with ENTER\n"
-#define CONFIG_AUTOBOOT_DELAY_STR "\n" /* 1st "password" */
+#define CONFIG_AUTOBOOT_DELAY_STR "\r" /* 1st "password" */
+#define CONFIG_AUTOBOOT_DELAY_STR2 "\n" /* 1st "password" */
#endif
/*
@@ -168,25 +168,36 @@
#define CONFIG_MII 1 /* add 405GP MII PHY management */
#define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_AUTOSCRIPT | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_NET | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_NAND | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_CACHE | \
- CFG_CMD_ELF )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_ELF
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -276,7 +287,7 @@
* External peripheral base address
*-----------------------------------------------------------------------
*/
-#if !(CONFIG_COMMANDS & CFG_CMD_IDE)
+#if !defined(CONFIG_CMD_IDE)
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
@@ -285,7 +296,7 @@
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
-#else /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
+#else
#define CONFIG_START_IDE 1 /* check, if use IDE */
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
@@ -345,7 +356,7 @@
#endif /* IDE_USES_ISA_EMULATION */
-#endif /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
+#endif
/*
#define CFG_KEY_REG_BASE_ADDR 0xF0100000
@@ -436,7 +447,7 @@ extern unsigned long offsetOfEnvironment;
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index d7d07a62fc9..8491d97ae42 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -64,24 +64,37 @@
*/
#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)
-
#define CONFIG_BAUDRATE 9600
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_EEPROM)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_EEPROM
#define CONFIG_BOOTDELAY 15
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
-
/*
* Miscellaneous configurable options
*/
@@ -104,7 +117,6 @@
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
@@ -113,8 +125,6 @@
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
-
-
#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
@@ -125,11 +135,9 @@
#define CONFIG_SPI_EEPROM /* Support for SPI EEPROMs (AT25128) */
#define CONFIG_MW_EEPROM /* Support for MicroWire EEPROMs (AT93LC46) */
-
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-
/* Environment in EEPROM */
#define CFG_ENV_IS_IN_EEPROM 1
#define CONFIG_SPI
@@ -182,6 +190,15 @@
#undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */
/************************************************************
+*SATA/Native Stuff
+************************************************************/
+#define CFG_SATA_SUPPORTED 1
+#define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */
+#define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */
+#define CFG_SATA_MAXDEVICES (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
+#define CFG_ATA_PIIX 1 /*Supports ata_piix driver */
+
+/************************************************************
* ATAPI support (experimental)
************************************************************/
#define CONFIG_ATAPI /* enable ATAPI Support */
@@ -200,7 +217,6 @@
#define CONFIG_I8042_KBD
#define CFG_ISA_IO 0
-
/************************************************************
* RTC
***********************************************************/
diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h
index a8e355508b1..c6f7f1526c6 100644
--- a/include/configs/sc520_spunk.h
+++ b/include/configs/sc520_spunk.h
@@ -64,16 +64,34 @@
#define CONFIG_BAUDRATE 9600
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_PCMCIA | CFG_CMD_EEPROM)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_EEPROM
+
#define CONFIG_BOOTDELAY 15
#define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7936k(root),256k(uboot) "
#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h
index a4249c47c62..d140241bff4 100644
--- a/include/configs/scb9328.h
+++ b/include/configs/scb9328.h
@@ -36,20 +36,27 @@
/*
- * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
- * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
- * functionality or size of u-boot code.
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- & ~CFG_CMD_LOADS \
- & ~CFG_CMD_CONSOLE \
- & ~CFG_CMD_AUTOSCRIPT \
- | CFG_CMD_NET \
- | CFG_CMD_PING \
- | CFG_CMD_DHCP \
- )
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_AUTOSCRIPT
-#include <cmd_confdefs.h>
/*
* Boot options. Setting delay to -1 stops autostart count down.
@@ -182,7 +189,7 @@
* Right now there is no gain for user, but later on booting kernel might be
* possible. Consider using XIP kernel running from flash to save RAM
* footprint.
- * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_FIRST_SECTOR 5
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index b7f79c26eb9..c2e1386217f 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -37,10 +37,11 @@
#else
#define CONFIG_440GRX 1 /* Specific PPC440GRx */
#endif
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
/* Detect Sequoia PLL input clock automatically via CPLD bit */
#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
- 3333333 : 33000000)
+ 33333333 : 33000000)
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
@@ -58,6 +59,7 @@
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
@@ -80,7 +82,7 @@
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
/*-----------------------------------------------------------------------
* Serial Port
@@ -125,7 +127,7 @@
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -168,12 +170,19 @@
/*
* Now the NAND chip has to be defined (no autodetection used!)
*/
-#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */
+#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
-#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */
-#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */
+#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
+#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
+#define CFG_NAND_ECCSIZE 256
+#define CFG_NAND_ECCBYTES 3
+#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+#define CFG_NAND_OOBSIZE 16
+#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
+
#ifdef CFG_ENV_IS_IN_NAND
/*
* For NAND booting the environment is embedded in the U-Boot image. Please take
@@ -290,9 +299,6 @@
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE
-#define CMD_USB CFG_CMD_USB
-#else
-#define CMD_USB 0 /* no USB on 440GRx */
#endif /* CONFIG_440EPX */
/* Partitions */
@@ -300,37 +306,73 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DTT | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NAND | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CMD_USB)
-#define CONFIG_SUPPORT_VFAT
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+#ifdef CONFIG_440EPX
+#define CONFIG_CMD_USB
+#endif
+
+#ifndef CONFIG_RAINIER
+#define CFG_POST_FPU_ON CFG_POST_FPU
+#else
+#define CFG_POST_FPU_ON 0
+#endif
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_UART | \
+ CFG_POST_I2C | \
+ CFG_POST_CACHE | \
+ CFG_POST_FPU_ON | \
+ CFG_POST_ETHER | \
+ CFG_POST_SPR)
+
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_LOGBUFFER
+#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+#define CONFIG_SUPPORT_VFAT
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -358,12 +400,12 @@
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
-#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
@@ -421,7 +463,7 @@
*----------------------------------------------------------------------*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -433,7 +475,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/shannon.h b/include/configs/shannon.h
index 572985b051b..c1fa53f1a8a 100644
--- a/include/configs/shannon.h
+++ b/include/configs/shannon.h
@@ -66,21 +66,28 @@
#define CONFIG_BAUDRATE 115200
-#if 0 /* XXX - cannot test IDE anyway, so disabled for now - wd */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_IDE)
-#endif /* 0 */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200"
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_BOOTCOMMAND "help"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h
index a137f9d7c99..05f60537270 100644
--- a/include/configs/smdk2400.h
+++ b/include/configs/smdk2400.h
@@ -86,24 +86,32 @@
/* Use s3c2400's RTC */
#define CONFIG_RTC_S3C24X0 1
-#ifndef USE_920T_MMU
-#define CONFIG_COMMANDS_tmp ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
- CFG_CMD_DATE | \
- CFG_CMD_SNTP )
-#else
-#define CONFIG_COMMANDS_tmp (CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_SNTP )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_SNTP
+
+#if defined(CONFIG_HWFLOW)
+ #define CONFIG_CONFIG_HWFLOW
#endif
-#ifdef CONFIG_HWFLOW
-#define CONFIG_COMMANDS (CONFIG_COMMANDS_tmp | CFG_CMD_HWFLOW)
-#else
-#define CONFIG_COMMANDS CONFIG_COMMANDS_tmp
+#if !defined(USE_920T_MMU)
+ #undef CONFIG_CMD_CACHE
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
#if 0
@@ -118,7 +126,7 @@
#define CONFIG_BOOTCOMMAND "tftp; bootm"
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index 7edec0db43d..ca404ff452a 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -72,22 +72,26 @@
#define CONFIG_BAUDRATE 115200
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_CACHE | \
- /*CFG_CMD_NAND |*/ \
- /*CFG_CMD_EEPROM |*/ \
- /*CFG_CMD_I2C |*/ \
- /*CFG_CMD_USB |*/ \
- CFG_CMD_REGINFO | \
- CFG_CMD_DATE | \
- CFG_CMD_ELF)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+
#define CONFIG_BOOTDELAY 3
/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
@@ -98,7 +102,7 @@
/*#define CONFIG_BOOTFILE "elinos-lart" */
/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h
index e106b3b5746..ad68c751c89 100644
--- a/include/configs/smmaco4.h
+++ b/include/configs/smmaco4.h
@@ -42,11 +42,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -65,33 +60,41 @@
CFG_POST_I2C)
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#else
-#define CFG_CMD_POST_DIAG 0
#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
+#ifdef CONFIG_POST
+#define CONFIG_CMD_DIAG
+#endif
+
#define CONFIG_TIMESTAMP /* display image timestamps */
@@ -138,17 +141,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@@ -319,7 +322,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -338,9 +341,13 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -357,7 +364,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h
index 4937638820b..fe014eabcbc 100644
--- a/include/configs/sorcery.h
+++ b/include/configs/sorcery.h
@@ -39,12 +39,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -69,30 +63,35 @@
#define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS
#define CONFIG_PCI_CFG_SIZE 0x01000000
+
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BOOTD | \
- CFG_CMD_CACHE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP | \
- 0)
-
-/* CFG_CMD_MII | \ */
-/* CFG_CMD_USB | \ */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
/*
* Default Environment
@@ -268,7 +267,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -284,6 +283,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
index 09bbebdce89..2efc8f10ec1 100644
--- a/include/configs/spc1920.h
+++ b/include/configs/spc1920.h
@@ -31,14 +31,9 @@
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_MII
-/* #define MII_DEBUG */
-/* #define CONFIG_FEC_ENET */
#undef CONFIG_ETHER_ON_FEC1
#define CONFIG_ETHER_ON_FEC2
#define FEC_ENET
-/* #define CONFIG_FEC2_PHY_NORXERR */
-/* #define CFG_DISCOVER_PHY */
-/* #define CONFIG_PHY_ADDR 0x1 */
#define CONFIG_FEC2_PHY 1
#define CONFIG_BAUDRATE 19200
@@ -80,24 +75,31 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#ifndef CONFIG_COMMANDS
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_ASKENV \
- | CFG_CMD_DATE \
- | CFG_CMD_ECHO \
- | CFG_CMD_IMMAP \
- | CFG_CMD_JFFS2 \
- | CFG_CMD_PING \
- | CFG_CMD_DHCP \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
- /* & ~( CFG_CMD_NET)) */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#endif /* !CONFIG_COMMANDS */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
/*
* Miscellaneous configurable options
@@ -107,7 +109,7 @@
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -194,7 +196,7 @@
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#ifdef CFG_CMD_DATE
+#ifdef CONFIG_CMD_DATE
# define CONFIG_RTC_DS3231
# define CFG_I2C_RTC_ADDR 0x68
#endif
@@ -202,7 +204,7 @@
/*-----------------------------------------------------------------------
* I2C configuration
*/
-#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#if defined(CONFIG_CMD_I2C)
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index f40dde2ac83..4b618f36a87 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -44,11 +44,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -88,12 +83,6 @@
#define CONFIG_NS8382X 1
#endif /* CONFIG_STK52XX */
-#ifdef CONFIG_PCI
-#define ADD_PCI_CMD CFG_CMD_PCI
-#else
-#define ADD_PCI_CMD 0
-#endif
-
/*
* Video console
*/
@@ -110,12 +99,6 @@
#define CFG_CONSOLE_IS_IN_ENV
#endif
-#ifdef CONFIG_VIDEO
-#define ADD_BMP_CMD CFG_CMD_BMP
-#else
-#define ADD_BMP_CMD 0
-#endif
-
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -124,10 +107,7 @@
/* USB */
#ifdef CONFIG_STK52XX
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
#endif
/* POST support */
@@ -136,43 +116,60 @@
CFG_POST_I2C)
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#else
-#define CFG_CMD_POST_DIAG 0
#endif
-/* IDE */
-#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
-#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
-#else
-#define ADD_IDE_CMD 0
-#endif
/*
- * Supported commands
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- ADD_BMP_CMD | \
- ADD_IDE_CMD | \
- ADD_PCI_CMD | \
- ADD_USB_CMD | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
+#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
+ #define CONFIG_CMD_IDE
+ #define CONFIG_CMD_FAT
+ #define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_STK52XX
+ #define CONFIG_CMD_USB
+ #define CONFIG_CMD_FAT
+#endif
+
+#ifdef CONFIG_VIDEO
+ #define CONFIG_CMD_BMP
+#endif
+
+#ifdef CONFIG_PCI
+ #define CONFIG_CMD_PCI
+#endif
+
+#ifdef CONFIG_POST
+#define CONFIG_CMD_DIAG
+#endif
+
#define CONFIG_TIMESTAMP /* display image timestamps */
@@ -219,17 +216,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@@ -406,7 +403,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -425,9 +422,13 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -444,7 +445,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 625cf20144f..c5ae0cde361 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -230,16 +230,17 @@
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPS85XX_FEC
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 4
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#define CONFIG_ETHPRIME "TSEC0"
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
@@ -298,34 +299,38 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
#if defined(CFG_RAMBOOT)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV | \
- CFG_CMD_LOADS ))
- #elif defined(CONFIG_TSEC_ENET)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \
- CFG_CMD_MII | CFG_CMD_I2C ) & \
- ~(CFG_CMD_ENV))
- #elif defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV))
- #endif
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
- #elif defined(CONFIG_TSEC_ENET)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \
- CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C)
- #elif defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
- #endif
+ #define CONFIG_CMD_ELF
+#endif
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
#endif
-#include <cmd_confdefs.h>
+
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_CMD_MII
+#endif
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -334,7 +339,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "GPPP=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -355,7 +360,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -367,13 +372,14 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*Note: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 8624f4b74b8..b41dafaf986 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -42,20 +42,20 @@
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
-#undef CONFIG_PCI /* pci ethernet support */
-#define CONFIG_TSEC_ENET /* tsec ethernet support*/
-#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
+#define CONFIG_PCI /* PCI ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support*/
+#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#undef CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
/* sysclk for MPC85xx
*/
-#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
+#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
/* Blinkin' LEDs for Robert :-)
*/
@@ -64,36 +64,40 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#undef CFG_DRAM_TEST /* memory test, takes time */
-#define CFG_MEMTEST_START 0x00200000 /* memtest region */
-#define CFG_MEMTEST_END 0x00400000
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest region */
+#define CFG_MEMTEST_END 0x00400000
-/* Localbus connector. There are many options that can be
+/* Localbus connector. There are many options that can be
* connected here, including sdram or lots of flash.
* This address, however, is used to configure a 256M local bus
* window that includes the Config latch below.
*/
-#define CFG_LBC_OPTION_BASE 0xf0000000 /* Localbus Extension */
+#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
#define CFG_LBC_OPTION_SIZE 256 /* 256MB */
/* There are various flash options used, we configure for the largest,
* which is 64Mbytes. The CFI works fine and will discover the proper
* sizes.
*/
-#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH 64M */
-#define CFG_BR0_PRELIM 0xFC001801 /* port size 32bit */
-#define CFG_OR0_PRELIM 0xFC000FF7 /* 64 MB Flash */
+#ifdef CONFIG_STXSSA_4M
+#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
+#else
+#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
+#endif
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x1801) /* port size 32bit */
+#define CFG_OR0_PRELIM (CFG_FLASH_BASE | 0x0FF7)
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
-#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
+#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
@@ -104,24 +108,24 @@
/* The configuration latch is Chip Select 1.
* It's an 8-bit latch in the lower 8 bits of the word.
*/
-#define CFG_LBC_CFGLATCH_BASE 0xfb000000 /* Base of config latch */
-#define CFG_BR1_PRELIM 0xfb001801 /* 32-bit port */
-#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
+#define CFG_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
+#define CFG_BR1_PRELIM 0xFB001801 /* 32-bit port */
+#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
-#undef CFG_RAMBOOT
+#undef CFG_RAMBOOT
#endif
#ifdef CFG_RAMBOOT
-#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
+#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
#else
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#endif
-#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
+#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -136,14 +140,14 @@
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
-#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
+#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
#undef CONFIG_CLOCKS_IN_MHZ
/* local bus definitions */
-#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
+#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
#define CFG_OR2_PRELIM 0xfc006901
-#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
+#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
#define CFG_LBC_LBCR 0x00000000
#define CFG_LBC_LSRT 0x20000000
#define CFG_LBC_MRTPR 0x20000000
@@ -154,52 +158,52 @@
#define CFG_LBC_LSDMR_5 0x4061b723
#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
-#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 2
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
-#ifdef CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* I2C */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#if 0
-#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
#else
/* I did the 'if 0' so we could keep the syntax above if ever needed. */
#undef CFG_I2C_NOPROBES
#endif
#define CFG_I2C_OFFSET 0x3000
-/* I2C EEPROM. AT24C32, we keep our environment in here.
+/* I2C EEPROM. AT24C32, we keep our environment in here.
*/
#define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */
#define CFG_I2C_EEPROM_ADDR_LEN 2
@@ -226,49 +230,50 @@
#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */
#if defined(CONFIG_PCI) /* PCI Ethernet card */
-
+#define CONFIG_MPC85XX_PCI2 1
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
+#define CONFIG_EEPRO100
+#define CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
- #define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+ #define PCI_ENET0_IOADDR 0xe0000000
+ #define PCI_ENET0_MEMADDR 0xe0000000
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
-#undef CONFIG_PCI_SCAN_SHOW
-#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+#define CONFIG_PCI_SCAN_SHOW
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPS85XX_FEC
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 4
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#define CONFIG_ETHPRIME "TSEC0"
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
-#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
+#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
+#undef CONFIG_ETHER_NONE /* define if ether on something else */
+#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
#if (CONFIG_ETHER_INDEX == 2)
/*
@@ -277,19 +282,19 @@
* - Select bus for bd/buffers
* - Full duplex
*/
- #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
- #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
- #define CFG_CPMFCR_RAMTYPE 0
+ #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+ #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+ #define CFG_CPMFCR_RAMTYPE 0
#if 0
- #define CFG_FCC_PSMR (FCC_PSMR_FDE)
+ #define CFG_FCC_PSMR (FCC_PSMR_FDE)
#else
- #define CFG_FCC_PSMR 0
+ #define CFG_FCC_PSMR 0
#endif
#define FETH2_RST 0x01
#elif (CONFIG_ETHER_INDEX == 3)
/* need more definitions here for FE3 */
#define FETH3_RST 0x80
-#endif /* CONFIG_ETHER_INDEX */
+#endif /* CONFIG_ETHER_INDEX */
/* MDIO is done through the TSEC0 control.
*/
@@ -300,17 +305,20 @@
/* Environment - default config is in flash, see below */
#if 0 /* in EEPROM */
-#define CFG_ENV_IS_IN_EEPROM 1
-#define CFG_ENV_OFFSET 0
-#define CFG_ENV_SIZE 2048
+# define CFG_ENV_IS_IN_EEPROM 1
+# define CFG_ENV_OFFSET 0
+# define CFG_ENV_SIZE 2048
#else /* in flash */
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_SECT_SIZE 0x40000
-
-#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE 0x4000
-#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+# define CFG_ENV_IS_IN_FLASH 1
+# ifdef CONFIG_STXSSA_4M
+# define CFG_ENV_SECT_SIZE 0x20000
+# else /* default configuration - 64 MiB flash */
+# define CFG_ENV_SECT_SIZE 0x40000
+# endif
+# define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
+# define CFG_ENV_SIZE 0x4000
+# define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
+# define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
@@ -318,34 +326,39 @@
#define CONFIG_TIMESTAMP /* Print image info with ts */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_CMD_MII
+#endif
+
#if defined(CFG_RAMBOOT)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV | \
- CFG_CMD_LOADS ))
- #elif defined(CONFIG_TSEC_ENET)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \
- CFG_CMD_MII | CFG_CMD_I2C ) & \
- ~(CFG_CMD_ENV))
- #elif defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV))
- #endif
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
- #elif defined(CONFIG_TSEC_ENET)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \
- CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C)
- #elif defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
- #endif
+ #define CONFIG_CMD_ELF
#endif
-#include <cmd_confdefs.h>
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -354,7 +367,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "SSA=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -375,7 +388,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -387,13 +400,14 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*Note: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
@@ -408,13 +422,13 @@
*/
#ifdef CFG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
-#define CONFIG_BAUDRATE 38400
+#define CONFIG_BAUDRATE 38400
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
#define CONFIG_SERVERIP 192.168.85.1
-#define CONFIG_IPADDR 192.168.85.60
+#define CONFIG_IPADDR 192.168.85.60
#define CONFIG_GATEWAYIP 192.168.85.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_HOSTNAME STX_SSA
@@ -424,7 +438,7 @@
#else /* ENV IS IN FLASH -- use a full-blown envionment */
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index 614a046105c..b035857dcea 100644
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -77,7 +77,16 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
@@ -100,19 +109,22 @@
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_NAND | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_MII | \
- CFG_CMD_NFS)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
@@ -122,7 +134,7 @@
#define CFG_HUSH_PARSER 1
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -213,7 +225,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
@@ -580,9 +592,6 @@ typedef unsigned int led_id_t;
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,MPC870@0"
#define OF_TBCLK (MPC8XX_HZ / 16)
#define CONFIG_OF_HAS_BD_T 1
diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h
index 82245558961..08ac9cbd58b 100644
--- a/include/configs/suzaku.h
+++ b/include/configs/suzaku.h
@@ -55,10 +55,21 @@
#define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000
#define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0)
-#define CONFIG_COMMANDS (CONFIG__CMD_DFL)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#define CFG_UART1_BASE (0xFFFF2000)
#define CONFIG_SERIAL_BASE CFG_UART1_BASE
diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h
index 92ee8cb3331..3b90f3ceb1d 100644
--- a/include/configs/svm_sc8xx.h
+++ b/include/configs/svm_sc8xx.h
@@ -125,22 +125,32 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
-/* CFG_CMD_IDE |*/ \
- CFG_CMD_DATE )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_DATE
+
+
#define CFG_NAND_LEGACY
/*
@@ -153,7 +163,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -246,7 +256,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/taihu.h b/include/configs/taihu.h
new file mode 100644
index 00000000000..d623e56009a
--- /dev/null
+++ b/include/configs/taihu.h
@@ -0,0 +1,476 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2005-2007
+ * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+#define CONFIG_405EP 1 /* this is a PPC405 CPU */
+#define CONFIG_4xx 1 /* member of PPC4xx family */
+#define CONFIG_TAIHU 1 /* on a taihu board */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */
+
+#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
+
+#define CONFIG_NO_SERIAL_EEPROM
+
+/*----------------------------------------------------------------------------*/
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+/*
+!-------------------------------------------------------------------------------
+! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
+! assuming a 33MHz input clock to the 405EP from the C9531.
+!-------------------------------------------------------------------------------
+*/
+#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_1)
+#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+
+#define PLLMR0_DEFAULT PLLMR0_333_111_55_37
+#define PLLMR1_DEFAULT PLLMR1_333_111_55_37
+#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111
+#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111
+
+#endif
+/*----------------------------------------------------------------------------*/
+
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootfile=/tftpboot/taihu/uImage\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "kernel_addr=FC000000\0" \
+ "ramdisk_addr=FC180000\0" \
+ "load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \
+ "update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \
+ "cp.b 200000 FFFC0000 40000\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0x14 /* PHY address */
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
+#define CONFIG_NET_MULTI 1
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_PHY_RESET 1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SPI
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */
+#define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
+#define CFG_SDRAM_BANKS 2
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
+
+/* SDRAM timings used in datasheet */
+#define CFG_SDRAM_CL 3 /* CAS latency */
+#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
+#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD 691200
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_UART1_CONSOLE 1
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * I2C stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
+
+#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+
+#define CONFIG_SOFT_SPI
+#define SPI_SCL spi_scl
+#define SPI_SDA spi_sda
+#define SPI_READ spi_read()
+#define SPI_DELAY udelay(2)
+#ifndef __ASSEMBLY__
+void spi_scl(int);
+void spi_sda(int);
+unsigned char spi_read(void);
+#endif
+
+/* standard dtt sensor configuration */
+#define CONFIG_DTT_DS1775 1
+#define CONFIG_DTT_SENSORS { 0 }
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+ /* resource configuration */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
+#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+#define CONFIG_EEPRO100 1
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFFE00000
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_ADDR0 0x555
+#define CFG_FLASH_ADDR1 0x2aa
+#define CFG_FLASH_WORD_SIZE unsigned short
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
+#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
+#define CFG_ENV_ADDR \
+ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * PPC405 GPIO Configuration
+ */
+#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 */ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
+} \
+}
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
+#define CFG_CACHELINE_SIZE 32
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x1000
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash/SRAM) initialization */
+#define CFG_EBC_PB0AP 0x03815600
+#define CFG_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (NVRAM/RTC) initialization */
+#define CFG_EBC_PB1AP 0x05815600
+#define CFG_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (USB device) initialization */
+#define CFG_EBC_PB2AP 0x03016600
+#define CFG_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 3 (LCM and D-flip-flop) initialization */
+#define CFG_EBC_PB3AP 0x158FF600
+#define CFG_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 4 (not install) initialization */
+#define CFG_EBC_PB4AP 0x158FF600
+#define CFG_EBC_PB4CR 0x5021A000
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0] - External Bus Controller BLAST output
+ * GPIO0[1-9] - Instruction trace outputs
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH 0x15555550 /* output select high/low */
+#define CFG_GPIO0_OSRL 0x00000110
+#define CFG_GPIO0_ISR1H 0x00000001 /* input select high/low */
+#define CFG_GPIO0_ISR1L 0x15545440
+#define CFG_GPIO0_TSRH 0x00000000 /* three-state select high/low */
+#define CFG_GPIO0_TSRL 0x00000000
+#define CFG_GPIO0_TCR 0xFFFE8117 /* three-state control */
+#define CFG_GPIO0_ODR 0x00000000 /* open drain */
+
+#define GPIO0 0 /* GPIO controller 0 */
+
+/* the GPIO macros in include/ppc405.h for High/Low registers are backwards */
+
+#define GPIOx_OSL (GPIO0_OSRH-GPIO_BASE)
+#define GPIOx_TSL (GPIO0_TSRH-GPIO_BASE)
+#define GPIOx_IS1L (GPIO0_ISR1H-GPIO_BASE)
+#define GPIOx_IS2L (GPIO0_ISR1H-GPIO_BASE)
+#define GPIOx_IS3L (GPIO0_ISR1H-GPIO_BASE)
+
+#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO output select */
+#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO three-state select */
+#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO input select */
+#define GPIO_IS2(x) (x+GPIOx_IS1L)
+#define GPIO_IS3(x) (x+GPIOx_IS1L)
+
+#define CPLD_REG0_ADDR 0x50100000
+#define CPLD_REG1_ADDR 0x50100001
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/taishan.h b/include/configs/taishan.h
index 2b28f93a071..baa4fbd312b 100644
--- a/include/configs/taishan.h
+++ b/include/configs/taishan.h
@@ -30,6 +30,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_TAISHAN 1 /* Board is taishan */
#define CONFIG_440GX 1 /* Specifc GX support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
@@ -217,8 +218,8 @@
#define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1
-#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
-#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
+#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
+#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
#define CONFIG_PHY2_ADDR 0x1
#define CONFIG_PHY3_ADDR 0x3
#define CONFIG_ET1011C_PHY 1
@@ -233,27 +234,36 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
-/*-----------------------------------------------------------------------
- * Console/Commands/Parser
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_DTT | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -262,7 +272,7 @@
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -297,7 +307,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
@@ -315,7 +324,7 @@
*----------------------------------------------------------------------*/
#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -327,7 +336,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h
index dac1eb736d8..a21af219a7e 100644
--- a/include/configs/tb0229.h
+++ b/include/configs/tb0229.h
@@ -87,13 +87,27 @@
/*#define CONFIG_BOOTCOMMAND "run flash_local" */
#define CONFIG_BOOTCOMMAND "run netboot"
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_PCI | \
- CFG_CMD_ELF )
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_ELF
+
/*
* Miscellaneous configurable options
diff --git a/include/configs/trab.h b/include/configs/trab.h
index a2dc8e7bff8..b9088a89abd 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -80,10 +80,17 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
/* USB stuff */
-#define CONFIG_USB_OHCI 1
+#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_USB_STORAGE 1
#define CONFIG_DOS_PARTITION 1
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT 1
+
+#define CFG_USB_OHCI_REGS_BASE 0x14200000
+#define CFG_USB_OHCI_SLOT_NAME "s3c2400"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
/*
* Size of malloc() pool
*/
@@ -130,60 +137,50 @@
/* Use s3c2400's RTC */
#define CONFIG_RTC_S3C24X0 1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
#ifdef CONFIG_HWFLOW
-#define CONFIG_COMMANDS_ADD_HWFLOW CFG_CMD_HWFLOW
-#else
-#define CONFIG_COMMANDS_ADD_HWFLOW 0
+ #define CONFIG_CMD_HWFLOW
#endif
#ifdef CONFIG_VFD
-#define CONFIG_COMMANDS_ADD_VFD CFG_CMD_VFD
-#else
-#define CONFIG_COMMANDS_ADD_VFD 0
+ #define CONFIG_CMD_VFD
#endif
#ifdef CONFIG_DRIVER_S3C24X0_I2C
-#define CONFIG_COMMANDS_ADD_EEPROM CFG_CMD_EEPROM
-#define CONFIG_COMMANDS_I2C CFG_CMD_I2C
-#else
-#define CONFIG_COMMANDS_ADD_EEPROM 0
-#define CONFIG_COMMANDS_I2C 0
+ #define CONFIG_CMD_EEPROM
+ #define CONFIG_CMD_I2C
#endif
#ifndef USE_920T_MMU
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
- CONFIG_COMMANDS_ADD_HWFLOW | \
- CONFIG_COMMANDS_ADD_VFD | \
- CONFIG_COMMANDS_ADD_EEPROM | \
- CONFIG_COMMANDS_I2C | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_FAT | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP | \
- CFG_CMD_USB )
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CONFIG_COMMANDS_ADD_HWFLOW | \
- CONFIG_COMMANDS_ADD_VFD | \
- CONFIG_COMMANDS_ADD_EEPROM | \
- CONFIG_COMMANDS_I2C | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_FAT | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP | \
- CFG_CMD_USB )
+ #undef CONFIG_CMD_CACHE
#endif
+
/* moved up */
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#define CONFIG_BOOTDELAY 5
#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
#define CONFIG_PREBOOT "echo;echo *** booting ***;echo"
@@ -296,7 +293,7 @@
#define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
@@ -422,6 +419,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/* Initial value of the on-board touch screen brightness */
#define CFG_BRIGHTNESS 0x20
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
new file mode 100644
index 00000000000..84998d4392a
--- /dev/null
+++ b/include/configs/trizepsiv.h
@@ -0,0 +1,325 @@
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ *
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the LUBBOCK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
+
+#define LITTLEENDIAN 1 /* used by usb_ohci.c */
+
+#define CONFIG_MMC 1
+#define BOARD_LATE_INIT 1
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define RTC
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_FFUART 1 /* we use FFUART on Conxs */
+#define CONFIG_BTUART 1 /* we use BTUART on Conxs */
+#define CONFIG_STUART 1 /* we use STUART on Conxs */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 38400
+
+#define CONFIG_DOS_PARTITION 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IMLS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_SERVERIP 192.168.1.99
+#define CONFIG_BOOTCOMMAND "run boot_flash"
+#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\
+ " rw root=/dev/ram initrd=0xa0800000,5m"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "program_boot_mmc=" \
+ "mw.b 0xa0010000 0xff 0x20000; " \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0010000 u-boot.bin; " \
+ "then " \
+ "protect off 0x0 0x1ffff; " \
+ "erase 0x0 0x1ffff; " \
+ "cp.b 0xa0010000 0x0 0x20000; " \
+ "fi\0" \
+ "program_uzImage_mmc=" \
+ "mw.b 0xa0010000 0xff 0x180000; " \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0010000 uzImage; " \
+ "then " \
+ "protect off 0x40000 0x1bffff; " \
+ "erase 0x40000 0x1bffff; " \
+ "cp.b 0xa0010000 0x40000 0x180000; " \
+ "fi\0" \
+ "program_ramdisk_mmc=" \
+ "mw.b 0xa0010000 0xff 0x500000; " \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0010000 ramdisk.gz; " \
+ "then " \
+ "protect off 0x1c0000 0x6bffff; " \
+ "erase 0x1c0000 0x6bffff; " \
+ "cp.b 0xa0010000 0x1c0000 0x500000; " \
+ "fi\0" \
+ "boot_mmc=" \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0030000 uzImage && " \
+ "fatload mmc 0 0xa0800000 ramdisk.gz; " \
+ "then " \
+ "bootm 0xa0030000; " \
+ "fi\0" \
+ "boot_flash=" \
+ "cp.b 0x1c0000 0xa0800000 0x500000; " \
+ "bootm 0x40000\0" \
+
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+/* #define CONFIG_INITRD_TAG 1 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER 1
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CFG_LONGHELP /* undef to save memory */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_DEVICE_NULLDEV 1
+
+#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0xa1000000 /* default load address */
+
+#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_MMC_BASE 0xF0000000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+
+#define CFG_DRAM_BASE 0xa0000000
+#define CFG_DRAM_SIZE 0x04000000
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/*
+ * GPIO settings
+ */
+#define CFG_GPSR0_VAL 0x00018000
+#define CFG_GPSR1_VAL 0x00000000
+#define CFG_GPSR2_VAL 0x400dc000
+#define CFG_GPSR3_VAL 0x00000000
+#define CFG_GPCR0_VAL 0x00000000
+#define CFG_GPCR1_VAL 0x00000000
+#define CFG_GPCR2_VAL 0x00000000
+#define CFG_GPCR3_VAL 0x00000000
+#define CFG_GPDR0_VAL 0x00018000
+#define CFG_GPDR1_VAL 0x00028801
+#define CFG_GPDR2_VAL 0x520dc000
+#define CFG_GPDR3_VAL 0x0001E000
+#define CFG_GAFR0_L_VAL 0x801c0000
+#define CFG_GAFR0_U_VAL 0x00000013
+#define CFG_GAFR1_L_VAL 0x6990100A
+#define CFG_GAFR1_U_VAL 0x00000008
+#define CFG_GAFR2_L_VAL 0xA0000000
+#define CFG_GAFR2_U_VAL 0x010900F2
+#define CFG_GAFR3_L_VAL 0x54000003
+#define CFG_GAFR3_U_VAL 0x00002401
+#define CFG_GRER0_VAL 0x00000000
+#define CFG_GRER1_VAL 0x00000000
+#define CFG_GRER2_VAL 0x00000000
+#define CFG_GRER3_VAL 0x00000000
+#define CFG_GFER0_VAL 0x00000000
+#define CFG_GFER1_VAL 0x00000000
+#define CFG_GFER2_VAL 0x00000000
+#define CFG_GFER3_VAL 0x00000020
+
+
+#define CFG_PSSR_VAL 0x20 /* CHECK */
+
+/*
+ * Clock settings
+ */
+#define CFG_CKEN 0x01FFFFFF /* CHECK */
+#define CFG_CCCR 0x02000290 /* 520Mhz */
+
+/*
+ * Memory settings
+ */
+
+#define CFG_MSC0_VAL 0x4df84df0
+#define CFG_MSC1_VAL 0x7ff87ff4
+#define CFG_MSC2_VAL 0xa26936d4
+#define CFG_MDCNFG_VAL 0x880009C9
+#define CFG_MDREFR_VAL 0x20ca201e
+#define CFG_MDMRS_VAL 0x00220022
+
+#define CFG_FLYCNFG_VAL 0x00000000
+#define CFG_SXCNFG_VAL 0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL 0x00000001
+#define CFG_MCMEM0_VAL 0x00004204
+#define CFG_MCMEM1_VAL 0x00010204
+#define CFG_MCATT0_VAL 0x00010504
+#define CFG_MCATT1_VAL 0x00010504
+#define CFG_MCIO0_VAL 0x00008407
+#define CFG_MCIO1_VAL 0x0000c108
+
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x08000000
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
+/* #define CONFIG_DM9000_USE_8BIT */
+/* #define CONFIG_DM9000_USE_16BIT */
+#define CONFIG_DM9000_USE_32BIT
+
+#define CONFIG_USB_OHCI_NEW 1
+#define CFG_USB_OHCI_BOARD_INIT 1
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 3
+#define CFG_USB_OHCI_REGS_BASE 0x4C000000
+#define CFG_USB_OHCI_SLOT_NAME "trizepsiv"
+#define CONFIG_USB_STORAGE 1
+#define CFG_USB_OHCI_CPU_INIT 1
+
+/*
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER 1
+
+#define CFG_MONITOR_BASE 0
+#define CFG_MONITOR_LEN 0x40000
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
+
+/* write flash less slowly */
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+
+/* Flash environment locations */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */
+#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */
+#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/uc100.h b/include/configs/uc100.h
index c4e629ade2b..92148e20543 100644
--- a/include/configs/uc100.h
+++ b/include/configs/uc100.h
@@ -98,7 +98,15 @@
#undef CONFIG_STATUS_LED /* no status-led */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -117,32 +125,32 @@
CFG_POST_SPR )
#undef CONFIG_POST
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
-#else
-#define CFG_CMD_POST_DIAG 0
+#define CONFIG_CMD_DIAG
#endif
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_SNTP )
#define CONFIG_NETCONSOLE
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
@@ -156,7 +164,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -246,7 +254,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/uc101.h b/include/configs/uc101.h
index 8cd8e9be709..aed80ec1e51 100644
--- a/include/configs/uc101.h
+++ b/include/configs/uc101.h
@@ -38,11 +38,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
#define CONFIG_BOARD_EARLY_INIT_R
/*
@@ -55,25 +50,34 @@
/* Partitions */
#define CONFIG_DOS_PARTITION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DISPLAY | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_DTT | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_NFS | \
- CFG_CMD_MII | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DISPLAY
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SNTP
+
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
@@ -114,7 +118,7 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
@@ -245,7 +249,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -264,9 +268,13 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -324,7 +332,6 @@
#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
#define CONFIG_IDE_PREINIT 1
-/* #define CONFIG_IDE_RESET 1 beispile siehe tqm5200.c */
#define CFG_ATA_IDE0_OFFSET 0x0000
diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h
index e5d4397d2c7..cd00c49fc22 100644
--- a/include/configs/utx8245.h
+++ b/include/configs/utx8245.h
@@ -86,18 +86,36 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_BDI | CFG_CMD_PCI \
- | CFG_CMD_FLASH | CFG_CMD_MEMORY \
- | CFG_CMD_ENV | CFG_CMD_CONSOLE \
- | CFG_CMD_LOADS | CFG_CMD_LOADB \
- | CFG_CMD_IMI | CFG_CMD_CACHE \
- | CFG_CMD_REGINFO | CFG_CMD_NET\
- | CFG_CMD_DHCP | CFG_CMD_I2C \
- | CFG_CMD_DATE)
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
*/
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
/*
@@ -403,7 +421,7 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/v37.h b/include/configs/v37.h
index a2e99b59e2a..04072534810 100644
--- a/include/configs/v37.h
+++ b/include/configs/v37.h
@@ -76,16 +76,30 @@
#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_DATE )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_DATE
+
/*
* JFFS2 partitions
@@ -105,15 +119,12 @@
#define MTDPARTS_DEFAULT "mtdparts=v37-1:-(jffs2)"
*/
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -194,7 +205,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index e19591d2993..c0b1a15e6b2 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -46,11 +46,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -89,28 +84,37 @@
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00001000
+
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_PING | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_IRQ | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_SDRAM | \
- CFG_CMD_DATE | \
- CFG_CMD_USB | \
- CFG_CMD_FAT)
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
* Boot low with 16 MB Flash
@@ -167,7 +171,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
@@ -254,7 +258,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -270,6 +274,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/versatile.h b/include/configs/versatile.h
index 16db43bb938..d2501501276 100644
--- a/include/configs/versatile.h
+++ b/include/configs/versatile.h
@@ -96,14 +96,29 @@
#define CFG_SERIAL0 0x101F1000
#define CFG_SERIAL1 0x101F2000
-#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV)
-/*#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) */
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_ENV
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=25,0,0xf1010000,0xf1010010,eth0"
diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h
index 06d8536ec31..edae6f4b984 100644
--- a/include/configs/virtlab2.h
+++ b/include/configs/virtlab2.h
@@ -89,34 +89,38 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#ifdef CONFIG_SPLASH_SCREEN
-# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BMP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#else
-# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#if defined(CONFIG_SPLASH_SCREEN)
+ #define CONFIG_CMD_BMP
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -131,7 +135,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -203,6 +207,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -214,7 +220,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h
index 4e97b01aa1a..7cab31dee4d 100644
--- a/include/configs/voiceblue.h
+++ b/include/configs/voiceblue.h
@@ -131,33 +131,38 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#ifdef VOICEBLUE_SMALL_FLASH
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_LOADB | \
- CFG_CMD_IMI | \
- CFG_CMD_FLASH | \
- CFG_CMD_MEMORY | \
- CFG_CMD_NET | \
- CFG_CMD_BOOTD | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_RUN)
-#else
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_LOADB | \
- CFG_CMD_IMI | \
- CFG_CMD_FLASH | \
- CFG_CMD_MEMORY | \
- CFG_CMD_NET | \
- CFG_CMD_ENV | \
- CFG_CMD_BOOTD | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_RUN | \
- CFG_CMD_JFFS2)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+
+#if !defined(VOICEBLUE_SMALL_FLASH)
+ #define CONFIG_CMD_ENV
+ #define CONFIG_CMD_JFFS2
#endif
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+
#define CONFIG_LOOPW
#ifdef VOICEBLUE_SMALL_FLASH
@@ -220,8 +225,6 @@
#endif /* VOICEBLUE_SMALL_FLASH */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
diff --git a/include/configs/walnut.h b/include/configs/walnut.h
index b34dc71d23f..180549efad3 100644
--- a/include/configs/walnut.h
+++ b/include/configs/walnut.h
@@ -98,26 +98,38 @@
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -128,7 +140,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -283,7 +295,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -340,7 +352,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h
index 47251bbb641..c67b3012276 100644
--- a/include/configs/wepep250.h
+++ b/include/configs/wepep250.h
@@ -36,18 +36,24 @@
/*
- * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
- * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
- * functionality or size of u-boot code.
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- & ~CFG_CMD_NET \
- & ~CFG_CMD_LOADS \
- & ~CFG_CMD_CONSOLE \
- & ~CFG_CMD_AUTOSCRIPT \
-/* | CFG_CMD_JFFS2 */ \
- )
-#include <cmd_confdefs.h>
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_AUTOSCRIPT
+
/*
* Boot options. Setting delay to -1 stops autostart count down.
@@ -152,7 +158,7 @@
* Right now there is no gain for user, but later on booting kernel might be
* possible. Consider using XIP kernel running from flash to save RAM
* footprint.
- * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_FIRST_SECTOR 5
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index 10397628301..7418986caac 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -64,15 +64,29 @@
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_DTT) | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_NFS | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+#undef CONFIG_CMD_DTT
+
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.255.0
@@ -86,7 +100,7 @@
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
index 825bfd14e93..bcd16ec5da0 100644
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -81,14 +81,26 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+
#define CONFIG_BOOTDELAY 3
diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h
index dc702cf4458..5733933d616 100644
--- a/include/configs/xsengine.h
+++ b/include/configs/xsengine.h
@@ -102,10 +102,26 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_PING | CFG_CMD_JFFS2)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_JFFS2
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h
index a2f48102f0c..35001d7ada3 100644
--- a/include/configs/xupv2p.h
+++ b/include/configs/xupv2p.h
@@ -118,25 +118,39 @@
#define CFG_ENV_IS_NOWHERE 1
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
-#define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
- CFG_CMD_MEMORY |\
- CFG_CMD_IRQ |\
- CFG_CMD_BDI |\
- CFG_CMD_NET |\
- CFG_CMD_IMI |\
- CFG_CMD_ECHO |\
- CFG_CMD_CACHE |\
- CFG_CMD_RUN |\
- CFG_CMD_AUTOSCRIPT |\
- CFG_CMD_ASKENV |\
- CFG_CMD_LOADS |\
- CFG_CMD_LOADB |\
- CFG_CMD_MISC |\
- CFG_CMD_PING \
- )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_PING
+
/* Miscellaneous configurable options */
#define CFG_PROMPT "U-Boot-mONStR> "
@@ -163,12 +177,12 @@
"base 0;" \
"echo"
-
/* system ace */
-/*#define CONFIG_SYSTEMACE
-#define DEBUG_SYSTEMACE
-#define CFG_SYSTEMACE_BASE 0xCF000000
-#define CFG_SYSTEMACE_WIDTH 16
-#define CONFIG_DOS_PARTITION*/
+#define CONFIG_SYSTEMACE
+/* #define DEBUG_SYSTEMACE */
+#define SYSTEMACE_CONFIG_FPGA
+#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
+#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
+#define CONFIG_DOS_PARTITION
#endif /* __CONFIG_H */
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index b68ae54b94d..6a5b7f1eaac 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -38,6 +38,7 @@
#define CONFIG_440GR 1 /* Specific PPC440GR support */
#define CONFIG_HOSTNAME yellowstone
#endif
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
@@ -122,7 +123,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -232,17 +233,20 @@
#ifdef CONFIG_440EP
/* USB */
-#define CONFIG_USB_OHCI
+#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
+#define CFG_OHCI_BE_CONTROLLER
+
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE (CFG_PERIPHERAL_BASE | 0x1000)
+#define CFG_USB_OHCI_SLOT_NAME "ppc440"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE
-#define CMD_USB (CFG_CMD_USB | CFG_CMD_FAT | CFG_CMD_EXT2)
-
#define CONFIG_SUPPORT_VFAT
-#else
-#define CMD_USB 0 /* no USB on 440GR */
#endif /* CONFIG_440EP */
#ifdef DEBUG
@@ -251,32 +255,49 @@
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CMD_USB)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+#ifdef CONFIG_440EP
+ #define CONFIG_CMD_USB
+ #define CONFIG_CMD_FAT
+ #define CONFIG_CMD_EXT2
+#endif
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -311,7 +332,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
@@ -344,7 +364,7 @@
*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -356,7 +376,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 7f8b0228aec..74033b4aef4 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -46,7 +46,6 @@
#define EXTCLK_83 83333333
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
-#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
#undef CONFIG_SHOW_BOOT_PROGRESS
#undef CONFIG_STRESS
@@ -69,11 +68,11 @@
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
-#define CFG_PCIE0_XCFGBASE 0xc0000400
-#define CFG_PCIE1_CFGBASE 0xc0001000
-#define CFG_PCIE1_XCFGBASE 0xc0001400
-#define CFG_PCIE2_CFGBASE 0xc0002000
-#define CFG_PCIE2_XCFGBASE 0xc0002400
+#define CFG_PCIE1_CFGBASE 0xc1000000
+#define CFG_PCIE2_CFGBASE 0xc2000000
+#define CFG_PCIE0_XCFGBASE 0xc3000000
+#define CFG_PCIE1_XCFGBASE 0xc3001000
+#define CFG_PCIE2_XCFGBASE 0xc3002000
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
@@ -136,7 +135,7 @@
/* Don't probe these addrs */
#define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54}
-/* #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
+/* #if defined(CONFIG_CMD_EEPROM) */
/* #define CFG_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
/* #endif */
@@ -183,6 +182,7 @@
"cp.b ${fileaddr} FFFB0000 ${filesize};" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
+ "pciconfighost=1\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -191,24 +191,36 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
@@ -232,7 +244,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -286,10 +298,9 @@
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#undef CFG_PCI_MASTER_INIT
@@ -314,7 +325,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -326,7 +337,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/zeus.h b/include/configs/zeus.h
new file mode 100644
index 00000000000..605755a87e8
--- /dev/null
+++ b/include/configs/zeus.h
@@ -0,0 +1,382 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * zeus.h - configuration for Zeus board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_ZEUS 1 /* Board is Zeus */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405EP 1 /* Specifc 405EP support*/
+
+#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+#define PLLMR0_DEFAULT PLLMR0_333_111_55_111
+#define PLLMR1_DEFAULT PLLMR1_333_111_55_111
+
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0x01 /* PHY address */
+#define CONFIG_HAS_ETH1 1
+#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */
+#define CONFIG_NET_MULTI 1
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_PHY_RESET 1
+#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_CACHE | \
+ CFG_POST_UART | \
+ CFG_POST_ETHER)
+
+#define CFG_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
+
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CFG_POST_UART_TABLE {UART0_BASE}
+
+#define CONFIG_LOGBUFFER
+#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
+
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*-----------------------------------------------------------------------
+ * SDRAM
+ *----------------------------------------------------------------------*/
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
+
+/* SDRAM timings used in datasheet */
+#define CFG_SDRAM_CL 3 /* CAS latency */
+#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
+#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#define CFG_BASE_BAUD 691200
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/* these are for the ST M24C02 2kbit serial i2c eeprom */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+
+#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */
+#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+
+/*
+ * The layout of the I2C EEPROM, used for bootstrap setup and for board-
+ * specific values, like ethaddr... that can be restored via the sw-reset
+ * button
+ */
+#define FACTORY_RESET_I2C_EEPROM 0x50
+#define FACTORY_RESET_ENV_OFFS 0x80
+#define FACTORY_RESET_ENV_SIZE 0x80
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFF000000
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x1000
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+/* reserve some memory for POST and BOOT limit info */
+#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
+
+/* extra data in OCM */
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
+#define CFG_POST_MAGIC (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 8)
+#define CFG_POST_VAL (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 12)
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash 16M) initialization */
+#define CFG_EBC_PB0AP 0x05815600
+#define CFG_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0] - External Bus Controller BLAST output
+ * GPIO0[1-9] - Instruction trace outputs
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH 0x15555550 /* Chip selects */
+#define CFG_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */
+#define CFG_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */
+#define CFG_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
+#define CFG_GPIO0_TSRH 0x00000000
+#define CFG_GPIO0_TSRL 0x00000000
+#define CFG_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
+#define CFG_GPIO0_ODR 0x00000000
+
+#define CFG_GPIO_SW_RESET 1
+#define CFG_GPIO_ZEUS_PE 12
+#define CFG_GPIO_LED_RED 22
+#define CFG_GPIO_LED_GREEN 23
+
+/* Time in milli-seconds */
+#define CFG_TIME_POST 5000
+#define CFG_TIME_FACTORY_RESET 10000
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/* ENVIRONMENT VARS */
+
+#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"
+#define CONFIG_IPADDR 192.168.1.10
+#define CONFIG_SERVERIP 192.168.1.100
+#define CONFIG_GATEWAYIP 192.168.1.100
+#define CONFIG_ETHADDR 50:00:00:00:06:00
+#define CONFIG_ETH1ADDR 50:00:00:00:06:01
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "logversion=2\0" \
+ "hostname=zeus\0" \
+ "netdev=eth0\0" \
+ "ethact=ppc_4xx_eth0\0" \
+ "netmask=255.255.255.0\0" \
+ "ramdisk_size=50000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw" \
+ " nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw" \
+ " ramdisk=${ramdisk_size}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0," \
+ "${baudrate}\0" \
+ "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
+ "run nfsargs addip addtty;bootm\0" \
+ "net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
+ "tftp ${ramdisk_mem_addr} ${file_fs};" \
+ "run ramargs addip addtty;" \
+ "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
+ "rootpath=/target_fs/zeus\0" \
+ "kernel_fl_addr=ff000000\0" \
+ "kernel_mem_addr=200000\0" \
+ "ramdisk_fl_addr=ff300000\0" \
+ "ramdisk_mem_addr=4000000\0" \
+ "uboot_fl_addr=fffc0000\0" \
+ "uboot_mem_addr=100000\0" \
+ "file_uboot=/zeus/u-boot.bin\0" \
+ "tftp_uboot=tftp 100000 ${file_uboot}\0" \
+ "update_uboot=protect off fffc0000 ffffffff;" \
+ "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
+ "protect on fffc0000 ffffffff\0" \
+ "upd_uboot=run tftp_uboot;run update_uboot\0" \
+ "file_kernel=/zeus/uImage_ba\0" \
+ "tftp_kernel=tftp 100000 ${file_kernel}\0" \
+ "update_kernel=protect off ff000000 ff17ffff;" \
+ "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
+ "upd_kernel=run tftp_kernel;run update_kernel\0" \
+ "file_fs=/zeus/rootfs_ba.img\0" \
+ "tftp_fs=tftp 100000 ${file_fs}\0" \
+ "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
+ "cp.b 100000 ff300000 580000\0" \
+ "upd_fs=run tftp_fs;run update_fs\0" \
+ "bootcmd=chkreset;run ramargs addip addtty addmisc;" \
+ "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
+ ""
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
index 1e8ed7abdfc..517ecb13b7f 100644
--- a/include/configs/zylonite.h
+++ b/include/configs/zylonite.h
@@ -76,19 +76,32 @@
#define CONFIG_BAUDRATE 115200
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#ifdef TURN_ON_ETHERNET
-# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
+ #define CONFIG_CMD_PING
#else
-# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_ENV \
- | CFG_CMD_NAND) \
- & ~(CFG_CMD_NET \
- | CFG_CMD_FLASH \
- | CFG_CMD_IMLS))
+ #define CONFIG_CMD_ENV
+ #define CONFIG_CMD_NAND
+
+ #undef CONFIG_CMD_NET
+ #undef CONFIG_CMD_FLASH
+ #undef CONFIG_CMD_IMLS
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY -1
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
@@ -100,7 +113,7 @@
#define CONFIG_CMDLINE_TAG
#define CONFIG_TIMESTAMP
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif