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-rw-r--r--include/configs/bmips_bcm6318.h2
-rw-r--r--include/configs/bmips_bcm63268.h2
-rw-r--r--include/configs/bmips_bcm6328.h2
-rw-r--r--include/configs/bmips_bcm6348.h2
-rw-r--r--include/configs/bmips_bcm6358.h2
-rw-r--r--include/configs/bmips_bcm6362.h2
-rw-r--r--include/configs/bmips_bcm6368.h2
-rw-r--r--include/configs/gardena-smart-gateway-mt7688.h21
-rw-r--r--include/configs/hsdk-4xd.h120
-rw-r--r--include/configs/linkit-smart-7688.h22
-rw-r--r--include/configs/mt7628.h56
-rw-r--r--include/configs/vocore2.h54
12 files changed, 285 insertions, 2 deletions
diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h
index c7e7119aafd..45eb931c257 100644
--- a/include/configs/bmips_bcm6318.h
+++ b/include/configs/bmips_bcm6318.h
@@ -19,7 +19,9 @@
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
#define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h
index 45f26bb3097..eed321eb6fc 100644
--- a/include/configs/bmips_bcm63268.h
+++ b/include/configs/bmips_bcm63268.h
@@ -19,7 +19,9 @@
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
#define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h
index 8d594387853..c78099a49dc 100644
--- a/include/configs/bmips_bcm6328.h
+++ b/include/configs/bmips_bcm6328.h
@@ -19,7 +19,9 @@
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
#define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h
index 061d6b25b71..547cf857ceb 100644
--- a/include/configs/bmips_bcm6348.h
+++ b/include/configs/bmips_bcm6348.h
@@ -17,7 +17,9 @@
/* USB */
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
#define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h
index 583217d2621..116e9705b6b 100644
--- a/include/configs/bmips_bcm6358.h
+++ b/include/configs/bmips_bcm6358.h
@@ -19,7 +19,9 @@
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
#define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h
index 570bc3b33d3..e5e8b15e187 100644
--- a/include/configs/bmips_bcm6362.h
+++ b/include/configs/bmips_bcm6362.h
@@ -19,7 +19,9 @@
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
#define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h
index ab5bdac7268..4d4403f8d21 100644
--- a/include/configs/bmips_bcm6368.h
+++ b/include/configs/bmips_bcm6368.h
@@ -19,7 +19,9 @@
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
#define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h
index 59c60743d24..6412efcbf88 100644
--- a/include/configs/gardena-smart-gateway-mt7688.h
+++ b/include/configs/gardena-smart-gateway-mt7688.h
@@ -16,10 +16,29 @@
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-#ifdef CONFIG_BOOT_RAM
+/* SPL */
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPL_BSS_START_ADDR 0x80010000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
+#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_PAD_TO 0
+
+/* Dummy value */
+#define CONFIG_SYS_UBOOT_BASE 0
+
+/* Serial SPL */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_CLK 40000000
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM1 0xb0000c00
+#define CONFIG_CONS_INDEX 1
+#endif
+
/* UART */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }
diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h
new file mode 100644
index 00000000000..4628108075e
--- /dev/null
+++ b/include/configs/hsdk-4xd.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ */
+
+#ifndef _CONFIG_HSDK_H_
+#define _CONFIG_HSDK_H_
+
+#include <linux/sizes.h>
+
+/*
+ * CPU configuration
+ */
+#define NR_CPUS 4
+#define ARC_PERIPHERAL_BASE 0xF0000000
+#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
+#define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE SZ_1G
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN SZ_2M
+#define CONFIG_SYS_BOOTM_LEN SZ_128M
+#define CONFIG_SYS_LOAD_ADDR 0x82000000
+
+/*
+ * UART configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK 33330000
+#define CONFIG_SYS_NS16550_MEM32
+
+/*
+ * Ethernet PHY configuration
+ */
+
+/*
+ * USB 1.1 configuration
+ */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+
+/*
+ * Environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "upgrade=if mmc rescan && " \
+ "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
+ "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
+ "\"Fail to upgrade.\n" \
+ "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \
+ "; fi\0" \
+ "core_mask=0xF\0" \
+ "hsdk_hs45d=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x0; setenv icache_ena 0x0; setenv csm_location 0x10; \
+setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
+ "hsdk_hs47d=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
+ "hsdk_hs47d_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
+ "hsdk_hs48=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
+ "hsdk_hs48_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
+ "hsdk_hs48x2=run hsdk_hs47dx2;\0" \
+ "hsdk_hs47dx2=setenv core_mask 0x3; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
+ "hsdk_hs48x3=run hsdk_hs47dx3;\0" \
+ "hsdk_hs47dx3=setenv core_mask 0x7; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
+setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
+ "hsdk_hs48x4=run hsdk_hs47dx4;\0" \
+ "hsdk_hs47dx4=setenv core_mask 0xF; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
+setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
+setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Cli configuration */
+#define CONFIG_SYS_CBSIZE SZ_2K
+
+/*
+ * Callback configuration
+ */
+#define CONFIG_BOARD_LATE_INIT
+
+#endif /* _CONFIG_HSDK_H_ */
diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h
index ca5b693e4cc..4276e95dee2 100644
--- a/include/configs/linkit-smart-7688.h
+++ b/include/configs/linkit-smart-7688.h
@@ -16,10 +16,30 @@
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-#ifdef CONFIG_BOOT_RAM
+/* SPL */
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPL_BSS_START_ADDR 0x80010000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
+#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_PAD_TO 0
+
+/* Dummy value */
+#define CONFIG_SYS_UBOOT_BASE 0
+
+/* Serial SPL */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_CLK 40000000
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM3 0xb0000e00
+#define CONFIG_CONS_INDEX 3
+
+#endif
+
/* UART */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }
diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h
new file mode 100644
index 00000000000..9b9218d2967
--- /dev/null
+++ b/include/configs/mt7628.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef __CONFIG_MT7628_H
+#define __CONFIG_MT7628_H
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN 0x100000
+#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_LOAD_ADDR 0x80010000
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x80000
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000
+
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_CBSIZE 1024
+
+/* Serial SPL */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_CLK 40000000
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM1 0xb0000c00
+#define CONFIG_CONS_INDEX 1
+#endif
+
+/* Serial common */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+ 230400, 460800, 921600 }
+
+/* SPL */
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPL_BSS_START_ADDR 0x80010000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
+#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_PAD_TO 0
+
+/* Dummy value */
+#define CONFIG_SYS_UBOOT_BASE 0
+
+#endif /* __CONFIG_MT7628_H */
diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h
new file mode 100644
index 00000000000..8100e4dca7b
--- /dev/null
+++ b/include/configs/vocore2.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Mauro Condarelli <mc5686@mclink.it>
+ */
+
+#ifndef __VOCORE2_CONFIG_H__
+#define __VOCORE2_CONFIG_H__
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+
+/* SPL */
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPL_BSS_START_ADDR 0x80010000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
+#define CONFIG_SPL_MAX_SIZE 0x10000
+
+/* Dummy value */
+#define CONFIG_SYS_UBOOT_BASE 0
+
+/* Serial SPL */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_CLK 40000000
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM3 0xb0000e00
+#define CONFIG_CONS_INDEX 3
+
+/* RAM */
+#define CONFIG_SYS_MEMTEST_START 0x80100000
+#define CONFIG_SYS_MEMTEST_END 0x80400000
+
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
+#define CONFIG_SYS_CBSIZE 512
+
+/* U-Boot */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+/* Environment settings */
+
+#endif //__VOCORE2_CONFIG_H__
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-14 04:15:27 +0000