diff options
Diffstat (limited to 'include/configs')
30 files changed, 0 insertions, 300 deletions
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index dc7a8b8aa8..1953d18e87 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -176,9 +176,6 @@ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -218,9 +215,6 @@ | OR_FCM_EHTR) /* 0xFFFF8396 */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - #ifdef CONFIG_VSC7385_ENET #define CONFIG_TSEC2 /* VSC7385 Base address on CS2 */ @@ -239,10 +233,6 @@ | OR_GPCM_TRLX_SET \ | OR_GPCM_EHTR_SET) /* 0xFFFE09FF */ -/* Access window base at VSC7385 base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE -/* Access window size 128K */ -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 #define CONFIG_VSC7385_IMAGE_SIZE 8192 diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 596d39ee5e..79c7f12bae 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -180,10 +180,6 @@ | OR_GPCM_EHTR \ | OR_GPCM_EAD) /* 0xFF006FF7 TODO SLOW 16 MB flash size */ - /* window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE - /* 16 MB window size */ -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ @@ -253,12 +249,6 @@ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM - /* local bus write LED / read status buffer (BCSR) mapping */ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ @@ -277,9 +267,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xFFFF8FF7 */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* Vitesse 7385 */ #ifdef CONFIG_VSC7385_ENET @@ -301,11 +288,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xFFFE09FF */ - - /* Access window base at VSC7385 base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) - #endif #define CONFIG_MPC83XX_GPIO 1 diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 9d1ce200ec..1b2bba96d3 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -153,10 +153,6 @@ | OR_GPCM_EHTR \ | OR_GPCM_EAD) /* 0xFF006FF7 TODO SLOW 16 MB flash size */ - /* window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE - /* 16 MB window size */ -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ @@ -222,12 +218,6 @@ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM - /* local bus write LED / read status buffer (BCSR) mapping */ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ @@ -246,9 +236,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xFFFF8FF7 */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* Vitesse 7385 */ #ifdef CONFIG_VSC7385_ENET @@ -270,11 +257,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xFFFE09FF */ - - /* Access window base at VSC7385 base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) - #endif #define CONFIG_MPC83XX_GPIO 1 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index fb568efe2d..86491b41d6 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -146,10 +146,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ /* 127 64KB sectors and 8 8KB top sectors per device */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -213,12 +209,6 @@ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM - #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ !defined(CONFIG_NAND_SPL) #define CONFIG_SYS_RAMBOOT diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 489e7c3368..cb17c7644d 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -141,9 +141,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 15fca456cc..d51d5ce06d 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -133,10 +133,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -162,8 +158,6 @@ */ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | BR_PS_8 \ @@ -185,8 +179,6 @@ /* PIB window base 0xF8008000 */ #define CONFIG_SYS_PIB_BASE 0xF8008000 #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) /* * CS2 on Local Bus, to PIB diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index e4d90589e9..06017a81bc 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -137,10 +137,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) - /* window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -161,8 +157,6 @@ */ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | BR_PS_8 \ | BR_MS_GPCM \ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index a24a2011d2..708a21f164 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -137,10 +137,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) - /* window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -161,8 +157,6 @@ */ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | BR_PS_8 \ | BR_MS_GPCM \ @@ -222,8 +216,6 @@ | BR_MS_SDRAM /* MSEL = SDRAM */ \ | BR_V) /* Valid */ /* 0xF0001861 */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) /* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index aeee6e0408..16d615dcc6 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -226,9 +226,6 @@ boards, we say we have two, but don't display a message if we find only one. */ | OR_GPCM_TRLX_SET \ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) - /* Vitesse 7385 */ #define CONFIG_SYS_VSC7385_BASE 0xF8000000 @@ -247,10 +244,6 @@ boards, we say we have two, but don't display a message if we find only one. */ | OR_GPCM_TRLX_SET \ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) - -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) - #endif /* LED */ @@ -281,9 +274,6 @@ boards, we say we have two, but don't display a message if we find only one. */ | BR_V) #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) - #endif /* diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 01a3a77e99..9d6dc767ef 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -162,10 +162,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -193,9 +189,6 @@ */ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | BR_PS_8 \ | BR_MS_GPCM \ @@ -233,9 +226,6 @@ | OR_FCM_EHTR) /* 0xFFFF919E */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* * Serial Port */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 9a4eeb6390..a1de8acc5c 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -188,10 +188,6 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -226,9 +222,6 @@ | OR_FCM_SCY_1 \ | OR_FCM_TRLX \ | OR_FCM_EHTR) -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* Vitesse 7385 */ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 @@ -249,11 +242,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xfffe09ff */ - - /* Access Base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) - #endif /* diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index c5a6203001..4479000d25 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -93,26 +93,15 @@ #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) - - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE - /* disable remaining mappings */ #define CONFIG_SYS_BR1_PRELIM 0x00000000 #define CONFIG_SYS_OR1_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 #define CONFIG_SYS_BR2_PRELIM 0x00000000 #define CONFIG_SYS_OR2_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 #define CONFIG_SYS_BR3_PRELIM 0x00000000 #define CONFIG_SYS_OR3_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 /* * Monitor config diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index f4ee222808..b355e56355 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -84,8 +84,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xffc06ff7 */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ @@ -96,8 +94,6 @@ #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ | OR_GPCM_SETA) /* 0xfffc0208 */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index c8fabf9da5..d86de800db 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -170,9 +170,6 @@ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -199,9 +196,6 @@ #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ /* Window base at FPGA base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 120eb0a6b7..e930c65637 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -142,9 +142,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 #define CONFIG_SYS_FLASH_SIZE 8 -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ BR_PS_8 |\ BR_MS_GPCM |\ @@ -173,11 +170,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) #define NAND_CACHE_PAGES 64 -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM - #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ (2<<BR_DECC_SHIFT) |\ BR_PS_8 |\ @@ -199,8 +191,6 @@ */ #define CONFIG_SYS_MRAM_BASE 0xE2000000 #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */ #define CONFIG_SYS_OR_TIMING_MRAM @@ -216,8 +206,6 @@ */ #define CONFIG_SYS_CPLD_BASE 0xE3000000 #define CONFIG_SYS_CPLD_SIZE 0x8000 -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E #define CONFIG_SYS_OR_TIMING_MRAM diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index a4a0fb222b..dcabac5666 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -108,9 +108,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -129,9 +126,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -353,10 +347,6 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256 -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE - -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ - #define CONFIG_SYS_BR3_PRELIM (\ CONFIG_SYS_PAXE_BASE | \ (1 << BR_PS_SHIFT) | \ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index f6c7cfce43..1da8df3931 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -93,9 +93,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -114,9 +111,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -333,10 +327,6 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256 -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE - -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ - #define CONFIG_SYS_BR3_PRELIM (\ CONFIG_SYS_PAXE_BASE | \ (1 << BR_PS_SHIFT) | \ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 6ac36c0f92..e732c2ad02 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -134,9 +131,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -367,11 +361,6 @@ /* * Configuration for C2 on the local bus */ -/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -/* Window size: 256 MB */ -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ BR_PS_8 | \ BR_MS_GPCM | \ @@ -388,8 +377,6 @@ /* * Configuration for C3 on the local bus */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ BR_PS_16 | \ BR_MS_GPCM | \ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 7ee9a914a4..42fbdbf947 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -134,9 +131,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -365,11 +359,6 @@ /* * Configuration for C2 on the local bus */ -/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -/* Window size: 256 MB */ -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ BR_PS_8 | \ BR_MS_GPCM | \ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 53017faa1c..222eb72f8e 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -120,9 +120,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -141,9 +138,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -427,9 +421,6 @@ OR_GPCM_TRLX_CLEAR | \ OR_GPCM_EHTR_CLEAR) -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - /* ethernet port connected to piggy (UEC2) */ #define CONFIG_HAS_ETH1 #define CONFIG_UEC_ETH2 diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 8f2be980a0..e542158022 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -134,9 +131,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -367,11 +361,6 @@ /* * Configuration for C2 on the local bus */ -/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -/* Window size: 256 MB */ -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ BR_PS_8 | \ BR_MS_GPCM | \ @@ -388,8 +377,6 @@ /* * Configuration for C3 on the local bus */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ BR_PS_16 | \ BR_MS_GPCM | \ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 172a28e850..3e2cc60f3e 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -112,9 +112,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -133,9 +130,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -409,9 +403,6 @@ /* * APP1 on the local bus CS2 */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ BR_PS_16 | \ BR_MS_UPMA | \ @@ -431,10 +422,6 @@ #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ MxMR_WLFx_2X) - -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - /* * QE UEC ethernet configuration */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 1bca11bd6e..aa9710f9c2 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -180,9 +180,6 @@ #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -217,9 +214,6 @@ | OR_GPCM_EHTR_SET) /* 0xFFFF8052 */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* * CPLD on Local Bus */ @@ -233,9 +227,6 @@ | OR_GPCM_EHTR_SET) /* 0xFFFF8042 */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* * Serial Port */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 8179147bc2..edf76e5851 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -114,10 +114,6 @@ | OR_GPCM_EAD) /* 0xFF806FF7 */ - /* window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ @@ -180,9 +176,6 @@ | BR_MS_SDRAM \ | BR_V) /* 0xF0001861 */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) - /* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. * diff --git a/include/configs/strider.h b/include/configs/strider.h index a716096bed..3b0207488f 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -168,9 +168,6 @@ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -197,9 +194,6 @@ #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ /* Window base at FPGA base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 6a4006ef6a..987b2d77cc 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -110,9 +110,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -131,9 +128,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -362,9 +356,6 @@ /* * APP1 on the local bus CS2 */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ BR_PS_16 | \ BR_MS_UPMA | \ @@ -384,8 +375,4 @@ #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ MxMR_WLFx_2X) - -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #endif /* __CONFIG_H */ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 5bb74fd9ae..5fceac7ae1 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -134,9 +131,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -365,11 +359,6 @@ /* * Configuration for C2 on the local bus */ -/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -/* Window size: 256 MB */ -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ BR_PS_8 | \ BR_MS_GPCM | \ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 49f77efa74..1b97d0fecb 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -134,9 +131,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -367,11 +361,6 @@ /* * Configuration for C2 on the local bus */ -/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -/* Window size: 256 MB */ -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ BR_PS_8 | \ BR_MS_GPCM | \ @@ -388,11 +377,6 @@ /* * Configuration for C3 on the local bus */ -/* Access window base at PINC3 base */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE -/* Window size: 256 MB */ -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ BR_PS_8 | \ BR_MS_GPCM | \ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 84d2c897d7..7dcc150f19 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -111,9 +111,6 @@ #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ @@ -186,12 +183,6 @@ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM - /* CS2 NvRAM */ #define CONFIG_SYS_BR2_PRELIM (0x60000000 \ | BR_PS_8 \ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 249783720c..ed02661f82 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -84,8 +84,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xf8006ff7 */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ @@ -96,8 +94,6 @@ #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ | OR_GPCM_SETA) /* 0xfffc0208 */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ |