diff options
Diffstat (limited to 'include/configs')
33 files changed, 284 insertions, 256 deletions
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 1537b45cc1..1c615acb3b 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -57,7 +57,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index e9371a025b..5a1a29bd9e 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -66,7 +66,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 819129033f..7697e8d3e0 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -36,7 +36,6 @@ #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 280b873aee..2cbe855235 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -16,7 +16,6 @@ #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index be600becfe..b37601c794 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -20,7 +20,6 @@ #undef CONFIG_PCI2 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 5515b9232c..01ee69c013 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -16,7 +16,6 @@ #define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 3c6661fc83..de187bf9a4 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -15,7 +15,6 @@ #define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 13fbbb3044..e3952f423b 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -27,7 +27,6 @@ #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 025aa33083..1152bca03b 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -115,7 +115,6 @@ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 62943a3b0c..4b2eb6525b 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -81,7 +81,6 @@ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENABLE_36BIT_PHYS diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 7fe34c332e..9535a7bbb2 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -24,7 +24,6 @@ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #ifndef __ASSEMBLY__ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 98bb3342b9..54ec1abd66 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -491,50 +491,51 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 4b53e19fd4..ab92ca3b68 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -476,7 +476,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index b518c222d4..268a41c82c 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ + * Copyright 2013-2019 Arcturus Networks, Inc. + * https://www.arcturusnetworks.com/products/ucp1020/ * based on include/configs/p1_p2_rdb_pc.h * original copyright follows: * Copyright 2009-2011 Freescale Semiconductor, Inc. @@ -13,11 +13,66 @@ #ifndef __CONFIG_H #define __CONFIG_H +/*** Arcturus FirmWare Environment */ + +#define MAX_SERIAL_SIZE 15 +#define MAX_HWADDR_SIZE 17 + +#define MAX_FWENV_ADDR 4 + +#define FWENV_MMC 1 +#define FWENV_SPI_FLASH 2 +#define FWENV_NOR_FLASH 3 +/* + #define FWENV_TYPE FWENV_MMC + #define FWENV_TYPE FWENV_SPI_FLASH +*/ +#define FWENV_TYPE FWENV_NOR_FLASH + +#if (FWENV_TYPE == FWENV_MMC) +#ifndef CONFIG_SYS_MMC_ENV_DEV +#define CONFIG_SYS_MMC_ENV_DEV 1 +#endif +#define FWENV_ADDR1 -1 +#define FWENV_ADDR2 -1 +#define FWENV_ADDR3 -1 +#define FWENV_ADDR4 -1 +#define EMPY_CHAR 0 +#endif + +#if (FWENV_TYPE == FWENV_SPI_FLASH) +#ifndef CONFIG_SF_DEFAULT_SPEED +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#endif +#ifndef CONFIG_SF_DEFAULT_MODE +#define CONFIG_SF_DEFAULT_MODE SPI_MODE0 +#endif +#ifndef CONFIG_SF_DEFAULT_CS +#define CONFIG_SF_DEFAULT_CS 0 +#endif +#ifndef CONFIG_SF_DEFAULT_BUS +#define CONFIG_SF_DEFAULT_BUS 0 +#endif +#define FWENV_ADDR1 (0x200 - sizeof(smac)) +#define FWENV_ADDR2 (0x400 - sizeof(smac)) +#define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac)) +#define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac)) +#define EMPY_CHAR 0xff +#endif + +#if (FWENV_TYPE == FWENV_NOR_FLASH) +#define FWENV_ADDR1 0xEC080000 +#define FWENV_ADDR2 -1 +#define FWENV_ADDR3 -1 +#define FWENV_ADDR4 -1 +#define EMPY_CHAR 0xff +#endif +/***********************************/ + #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #if defined(CONFIG_TARTGET_UCP1020T1) @@ -38,8 +93,6 @@ #define CONFIG_NETMASK 255.255.252.0 #define CONFIG_ETHPRIME "eTSEC3" -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - #define CONFIG_SYS_L2_SIZE (256 << 10) #endif @@ -52,7 +105,6 @@ #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" #define CONFIG_TSEC1 -#define CONFIG_TSEC2 #define CONFIG_TSEC3 #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 @@ -68,7 +120,7 @@ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_ETHPRIME "eTSEC1" -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#undef CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_SYS_L2_SIZE (256 << 10) diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index f1c3522c68..19223e2947 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -204,7 +204,6 @@ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 5581cfd1c9..dd2a679b79 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -43,7 +43,6 @@ #define CONFIG_FSL_SPI_INTERFACE #define CONFIG_SF_DATAFLASH -#define CONFIG_FSL_QSPI #define QSPI0_AMBA_BASE 0x40000000 #define CONFIG_SPI_FLASH_SPANSION diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 0db86396e9..d3d787f14d 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -197,4 +197,8 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#ifdef CONFIG_SECURE_BOOT +#include <asm/fsl_secure_boot.h> +#endif + #endif /* __L1028A_COMMON_H */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 34b4756ed8..59c43f1ae1 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor + * Copyright 2019 NXP */ #ifndef __LS1046A_COMMON_H @@ -202,6 +203,15 @@ #include <config_distro_bootcmd.h> #endif +#if defined(CONFIG_TARGET_LS1046AFRWY) +#define LS1046A_BOOT_SRC_AND_HDR\ + "boot_scripts=ls1046afrwy_boot.scr\0" \ + "boot_script_hdr=hdr_ls1046afrwy_bs.out\0" +#else +#define LS1046A_BOOT_SRC_AND_HDR\ + "boot_scripts=ls1046ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls1046ardb_bs.out\0" +#endif #ifndef SPL_NO_MISC /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -232,8 +242,7 @@ "console=ttyS0,115200\0" \ CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ - "boot_scripts=ls1046ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \ + LS1046A_BOOT_SRC_AND_HDR \ "scan_dev_for_boot_part=" \ "part list ${devtype} ${devnum} devplist; " \ "env exists devplist || setenv devplist 1; " \ diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h new file mode 100644 index 0000000000..791bb8dc47 --- /dev/null +++ b/include/configs/ls1046afrwy.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __LS1046AFRWY_H__ +#define __LS1046AFRWY_H__ + +#include "ls1046a_common.h" + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define CONFIG_LAYERSCAPE_NS_ACCESS + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_SYS_UBOOT_BASE 0x40100000 + +/* IFC */ +#define CONFIG_FSL_IFC +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* IFC Timing Params */ +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#define I2C_RETIMER_ADDR 0x18 + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_CH_DEFAULT 0x1 /* Channel 0*/ +#define I2C_MUX_CH_RTC 0x1 /* Channel 0*/ + +/* RTC */ +#define RTC +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ +#define CONFIG_SYS_RTC_BUS_NUM 0 + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ + +/* FMan */ +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET + +#define QSGMII_PORT1_PHY_ADDR 0x1c +#define QSGMII_PORT2_PHY_ADDR 0x1d +#define QSGMII_PORT3_PHY_ADDR 0x1e +#define QSGMII_PORT4_PHY_ADDR 0x1f + +#define FDT_SEQ_MACADDR_FROM_ENV + +#define CONFIG_ETHPRIME "FM1@DTSEC3" + +#endif + +/* QSPI device */ +#ifdef CONFIG_FSL_QSPI +#define FSL_QSPI_FLASH_SIZE SZ_64M +#define FSL_QSPI_FLASH_NUM 1 +#endif + +#undef CONFIG_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" + +#include <asm/fsl_secure_boot.h> + +#endif /* __LS1046AFRWY_H__ */ diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 831767235e..2d20f15683 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor + * Copyright 2019 NXP */ #ifndef __LS1046ARDB_H__ @@ -162,6 +163,8 @@ #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CONFIG_ENV_ADDR CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET #else #if defined(CONFIG_SD_BOOT) #define CONFIG_SYS_MMC_ENV_DEV 0 diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 74c7dc4f8a..18f30b585c 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017, 2019 NXP * Copyright 2015 Freescale Semiconductor */ @@ -368,9 +368,9 @@ unsigned long get_board_ddr_clk(void); #else #ifdef CONFIG_TFABOOT #define SD_MC_INIT_CMD \ - "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ - "mmc read 0x80100000 0x7000 0x800;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" + "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ + "mmc read 0x80e00000 0x7000 0x800;" \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" #define IFC_MC_INIT_CMD \ "fsl_mc start mc 0x580a00000" \ " 0x580e00000 \0" @@ -378,8 +378,8 @@ unsigned long get_board_ddr_clk(void); "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ "loadaddr_sd=0x90100000\0" \ - "kernel_addr=0x100000\0" \ - "kernel_addr_sd=0x800\0" \ + "kernel_addr=0x581000000\0" \ + "kernel_addr_sd=0x8000\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ @@ -389,9 +389,23 @@ unsigned long get_board_ddr_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernel_size_sd=0x14000\0" \ - "mcinitcmd=fsl_mc start mc 0x580a00000" \ - " 0x580e00000 \0" \ - "mcmemsize=0x70000000 \0" + "load_addr=0xa0000000\0" \ + "kernelheader_addr=0x580800000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernelheader_size=0x40000\0" \ + "BOARD=ls2088aqds\0" \ + "mcmemsize=0x70000000 \0" \ + IFC_MC_INIT_CMD \ + "nor_bootcmd=echo Trying load from nor..;" \ + "cp.b $kernel_addr $load_addr " \ + "$kernel_size ; env exists secureboot && " \ + "cp.b $kernelheader_addr $kernelheader_addr_r " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + "bootm $load_addr#$BOARD\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "bootm $load_addr#$BOARD\0" #elif defined(CONFIG_SD_BOOT) #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ @@ -426,6 +440,25 @@ unsigned long get_board_ddr_clk(void); #endif /* CONFIG_TFABOOT */ #endif /* CONFIG_SECURE_BOOT */ +#ifdef CONFIG_TFABOOT +#define SD_BOOTCOMMAND \ + "env exists mcinitcmd && env exists secureboot "\ + "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ + "&& esbc_validate $load_addr; " \ + "env exists mcinitcmd && run mcinitcmd " \ + "&& mmc read 0x80d00000 0x6800 0x800 " \ + "&& fsl_mc lazyapply dpl 0x80d00000; " \ + "run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" + +#define IFC_NOR_BOOTCOMMAND \ + "env exists mcinitcmd && env exists secureboot "\ + "&& esbc_validate 0x580780000; env exists mcinitcmd "\ + "&& fsl_mc lazyapply dpl 0x580d00000;" \ + "run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#endif + #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) #define CONFIG_FSL_MEMAC #define CONFIG_PHYLIB_10G diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 2e8a8bbdb7..bfb54be79b 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017, 2019 NXP * Copyright 2015 Freescale Semiconductor */ @@ -342,14 +342,14 @@ unsigned long get_board_sys_clk(void); "esbc_validate 0x20740000;" \ "fsl_mc start mc 0x20a00000 0x20e00000 \0" #define SD_MC_INIT_CMD \ - "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ - "mmc read 0x80100000 0x7000 0x800;" \ + "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ + "mmc read 0x80e00000 0x7000 0x800;" \ "env exists secureboot && " \ "mmc read 0x80700000 0x3800 0x10 && " \ "mmc read 0x80740000 0x3A00 0x10 && " \ "esbc_validate 0x80700000 && " \ "esbc_validate 0x80740000 ;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" + "fsl_mc start mc 0x80a00000 0x80e00000\0" #define IFC_MC_INIT_CMD \ "env exists secureboot && " \ "esbc_validate 0x580700000 && " \ @@ -528,8 +528,8 @@ unsigned long get_board_sys_clk(void); "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ "&& esbc_validate $load_addr; " \ "env exists mcinitcmd && run mcinitcmd " \ - "&& mmc read 0x88000000 0x6800 0x800 " \ - "&& fsl_mc lazyapply dpl 0x88000000; " \ + "&& mmc read 0x80d00000 0x6800 0x800 " \ + "&& fsl_mc lazyapply dpl 0x80d00000; " \ "run distro_bootcmd;run sd_bootcmd; " \ "env exists secureboot && esbc_halt;" diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index eb0b1766aa..711b434baf 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -246,12 +246,6 @@ unsigned long get_board_ddr_clk(void); "run scan_dev_for_boot; " \ "fi; " \ "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;\0" \ "boot_a_script=" \ "load ${devtype} ${devnum}:${distro_bootpart} " \ "${scriptaddr} ${prefix}${script}; " \ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index d9312bd149..e07d2a178f 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -209,7 +209,6 @@ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index e42b9b0cb9..1e0708a71b 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -34,7 +34,6 @@ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 71aad7029a..2a81c803b6 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -16,6 +16,10 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x2000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 9df8604af7..ba613672eb 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -49,7 +49,6 @@ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #endif #ifdef CONFIG_PCIE1 -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #endif #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index 1f29e3d221..c90d8e0e9a 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -63,7 +63,6 @@ #define CONFIG_SH_MMCIF_CLK 48000000 /* ENV setting */ -#define CONFIG_ENV_IS_EMBEDDED #define CONFIG_ENV_SECT_SIZE (64 * 1024) #define CONFIG_ENV_ADDR (0x00080000) #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h index 0693fb5a3c..83d123f33a 100644 --- a/include/configs/sh7753evb.h +++ b/include/configs/sh7753evb.h @@ -63,7 +63,6 @@ #define CONFIG_SH_MMCIF_CLK 48000000 /* ENV setting */ -#define CONFIG_ENV_IS_EMBEDDED #define CONFIG_ENV_SECT_SIZE (64 * 1024) #define CONFIG_ENV_ADDR (0x00080000) #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index 05b2f01c15..f92f066494 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -75,7 +75,6 @@ #define SH7757LCR_PCIEBRG_SIZE (96 * 1024) /* ENV setting */ -#define CONFIG_ENV_IS_EMBEDDED #define CONFIG_ENV_SECT_SIZE (64 * 1024) #define CONFIG_ENV_ADDR (0x00080000) #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 22dd3c036e..0a87f226f8 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -22,7 +22,6 @@ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ /* * Multicore config diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index a7c8dc4e33..0389874609 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -22,7 +22,6 @@ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ /* * Multicore config diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h deleted file mode 100644 index 24fea68a11..0000000000 --- a/include/configs/zipitz2.h +++ /dev/null @@ -1,186 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Aeronix Zipit Z2 configuration file - * - * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ - -#undef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_PREBOOT - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_ADDR 0x40000 -#define CONFIG_ENV_SIZE 0x10000 - -#define CONFIG_SYS_MALLOC_LEN (128*1024) -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_BOOTCOMMAND \ - "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\ - "then " \ - "source 0xa0000000; " \ - "else " \ - "bootm 0x50000; " \ - "fi; " -#define CONFIG_TIMESTAMP -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -/* - * Serial Console Configuration - * STUART - the lower serial port on Colibri board - */ -#define CONFIG_STUART 1 - -/* - * Bootloader Components Configuration - */ - -/* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#endif - -/* - * SPI and LCD - */ -#ifdef CONFIG_CMD_SPI -#define CONFIG_SOFT_SPI -#define CONFIG_LCD_ROTATION -#define CONFIG_PXA_LCD -#define CONFIG_LMS283GF05 - -#define SPI_DELAY udelay(10) -#define SPI_SDA(val) zipitz2_spi_sda(val) -#define SPI_SCL(val) zipitz2_spi_scl(val) -#define SPI_READ zipitz2_spi_read() -#ifndef __ASSEMBLY__ -void zipitz2_spi_sda(int); -void zipitz2_spi_scl(int); -unsigned char zipitz2_spi_read(void); -#endif -#endif - -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ - -/* - * SRAM Map - */ -#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */ -#define PHYS_SRAM_SIZE 0x00040000 /* 256k */ - -/* - * DRAM Map - */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048) - -/* - * NOR FLASH - */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ -#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 -#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 - -/* - * GPIO settings - */ -#define CONFIG_SYS_GAFR0_L_VAL 0x02000140 -#define CONFIG_SYS_GAFR0_U_VAL 0x59188000 -#define CONFIG_SYS_GAFR1_L_VAL 0x63900002 -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950 -#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x29000308 -#define CONFIG_SYS_GAFR3_L_VAL 0x54000000 -#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5 -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000020 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -#define CONFIG_SYS_GPCR3_VAL 0x00000000 -#define CONFIG_SYS_GPDR0_VAL 0xdafcee00 -#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab -#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff -#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a -#define CONFIG_SYS_GPSR0_VAL 0x06080400 -#define CONFIG_SYS_GPSR1_VAL 0x007f0000 -#define CONFIG_SYS_GPSR2_VAL 0x032a0000 -#define CONFIG_SYS_GPSR3_VAL 0x00000180 - -#define CONFIG_SYS_PSSR_VAL 0x30 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x00511220 -#define CONFIG_SYS_CCCR 0x00000190 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8 -#define CONFIG_SYS_MSC1_VAL 0x0000ccd1 -#define CONFIG_SYS_MSC2_VAL 0x0000b884 -#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9 -#define CONFIG_SYS_MDREFR_VAL 0x2011a01e -#define CONFIG_SYS_MDMRS_VAL 0x00000000 -#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000001 -#define CONFIG_SYS_MCMEM0_VAL 0x00014307 -#define CONFIG_SYS_MCMEM1_VAL 0x00014307 -#define CONFIG_SYS_MCATT0_VAL 0x0001c787 -#define CONFIG_SYS_MCATT1_VAL 0x0001c787 -#define CONFIG_SYS_MCIO0_VAL 0x0001430f -#define CONFIG_SYS_MCIO1_VAL 0x0001430f - -#include "pxa-common.h" - -#endif /* __CONFIG_H */ |