diff options
Diffstat (limited to 'include/configs/p1_p2_rdb_pc.h')
| -rw-r--r-- | include/configs/p1_p2_rdb_pc.h | 48 |
1 files changed, 20 insertions, 28 deletions
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 523af5265f..77f3d81593 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -10,9 +10,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#if defined(CONFIG_P1020MBG) +#if defined(CONFIG_TARGET_P1020MBG) #define CONFIG_BOARDNAME "P1020MBG-PC" -#define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -21,19 +20,17 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1020UTM) +#if defined(CONFIG_TARGET_P1020UTM) #define CONFIG_BOARDNAME "P1020UTM-PC" -#define CONFIG_P1020 #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xe0 #define __SW_BOOT_SD 0x50 #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1020RDB_PC) +#if defined(CONFIG_TARGET_P1020RDB_PC) #define CONFIG_BOARDNAME "P1020RDB-PC" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -58,10 +55,9 @@ * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off */ -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_BOARDNAME "P1020RDB-PD" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -83,10 +79,9 @@ "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" #endif -#if defined(CONFIG_P1021RDB) +#if defined(CONFIG_TARGET_P1021RDB) #define CONFIG_BOARDNAME "P1021RDB-PC" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1021 #define CONFIG_QE #define CONFIG_VSC7385_ENET #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of @@ -118,10 +113,9 @@ #endif #endif -#if defined(CONFIG_P1024RDB) +#if defined(CONFIG_TARGET_P1024RDB) #define CONFIG_BOARDNAME "P1024RDB" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1024 #define CONFIG_SLIC #define __SW_BOOT_MASK 0xf3 #define __SW_BOOT_NOR 0x00 @@ -131,10 +125,9 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1025RDB) +#if defined(CONFIG_TARGET_P1025RDB) #define CONFIG_BOARDNAME "P1025RDB" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1025 #define CONFIG_QE #define CONFIG_SLIC @@ -148,10 +141,9 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P2020RDB) -#define CONFIG_BOARDNAME "P2020RDB-PCA" +#if defined(CONFIG_TARGET_P2020RDB) +#define CONFIG_BOARDNAME "P2020RDB-PC" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P2020 #define CONFIG_VSC7385_ENET #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xc8 @@ -292,7 +284,7 @@ #define CONFIG_LIBATA #define CONFIG_LBA48 -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_TARGET_P2020RDB) #define CONFIG_SYS_CLK_FREQ 100000000 #else #define CONFIG_SYS_CLK_FREQ 66666666 @@ -336,7 +328,7 @@ #define SPD_EEPROM_ADDRESS 0x52 #undef CONFIG_FSL_DDR_INTERACTIVE -#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) +#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G #define CONFIG_CHIP_SELECTS_PER_CTRL 2 #else @@ -351,7 +343,7 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Default settings for DDR3 */ -#ifndef CONFIG_P2020RDB +#ifndef CONFIG_TARGET_P2020RDB #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 @@ -406,10 +398,10 @@ /* * Local Bus Definitions */ -#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) +#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ #define CONFIG_SYS_FLASH_BASE 0xec000000 -#elif defined(CONFIG_P1020UTM) +#elif defined(CONFIG_TARGET_P1020UTM) #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ #define CONFIG_SYS_FLASH_BASE 0xee000000 #else @@ -455,7 +447,7 @@ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) #else #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) @@ -466,7 +458,7 @@ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ | OR_FCM_PGS /* Large Page*/ \ | OR_FCM_CSCT \ @@ -584,7 +576,7 @@ #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_TARGET_P2020RDB) #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) #else #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) @@ -755,7 +747,7 @@ #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #endif /* CONFIG_QE */ -#ifdef CONFIG_P1025RDB +#ifdef CONFIG_TARGET_P1025RDB /* * QE UEC ethernet configuration */ @@ -789,7 +781,7 @@ #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 #endif /* CONFIG_UEC_ETH5 */ -#endif /* CONFIG_P1025RDB */ +#endif /* CONFIG_TARGET_P1025RDB */ /* * Environment @@ -853,7 +845,7 @@ #endif #endif -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif |