diff options
Diffstat (limited to 'include/configs/SCM.h')
| -rw-r--r-- | include/configs/SCM.h | 278 |
1 files changed, 139 insertions, 139 deletions
diff --git a/include/configs/SCM.h b/include/configs/SCM.h index 50cf499b76b..c6fb0749921 100644 --- a/include/configs/SCM.h +++ b/include/configs/SCM.h @@ -75,8 +75,8 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F /* * Software (bit-bang) I2C driver configuration @@ -92,10 +92,10 @@ else iop->pdat &= ~0x00020000 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CONFIG_I2C_X @@ -151,10 +151,10 @@ * - RAM for BD/Buffers is on the 60x Bus (see 28-13) * - Enable Full Duplex in FSMR */ -# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) +# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) +# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11) +# define CONFIG_SYS_CPMFCR_RAMTYPE 0 +# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) @@ -164,10 +164,10 @@ * - RAM for BD/Buffers is on the 60x Bus (see 28-13) * - Enable Full Duplex in FSMR */ -# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) +# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) +# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) +# define CONFIG_SYS_CPMFCR_RAMTYPE 0 +# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ @@ -186,7 +186,7 @@ #endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -214,27 +214,27 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ +#define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ #define CONFIG_MISC_INIT_R /* have misc_init_r() function */ @@ -243,35 +243,35 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* What should the base address of the main FLASH be and how big is * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk * The main FLASH is whichever is connected to *CS0. */ -#define CFG_FLASH0_BASE 0x40000000 -#define CFG_FLASH1_BASE 0x60000000 -#define CFG_FLASH0_SIZE 32 -#define CFG_FLASH1_SIZE 32 +#define CONFIG_SYS_FLASH0_BASE 0x40000000 +#define CONFIG_SYS_FLASH1_BASE 0x60000000 +#define CONFIG_SYS_FLASH0_SIZE 32 +#define CONFIG_SYS_FLASH1_SIZE 32 /* Flash bank size (for preliminary settings) */ -#define CFG_FLASH_SIZE CFG_FLASH0_SIZE +#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ #if 0 /* Start port with environment in flash; switch to EEPROM later */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CFG_FLASH_BASE+0x40000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000) #define CONFIG_ENV_SIZE 0x40000 #define CONFIG_ENV_SECT_SIZE 0x40000 #else @@ -284,63 +284,63 @@ /*----------------------------------------------------------------------- * Hardware Information Block */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ +#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ /*----------------------------------------------------------------------- * Hard Reset Configuration Words * - * if you change bits in the HRCW, you must also change the CFG_* + * if you change bits in the HRCW, you must also change the CONFIG_SYS_* * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. */ #if defined(CONFIG_266MHz) -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ +#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ HRCW_MODCK_H0111) #elif defined(CONFIG_300MHz) -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ +#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ HRCW_MODCK_H0110) #else -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) +#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) #endif /* no slaves so just fill with zeros */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CONFIG_SYS_HRCW_SLAVE1 0 +#define CONFIG_SYS_HRCW_SLAVE2 0 +#define CONFIG_SYS_HRCW_SLAVE3 0 +#define CONFIG_SYS_HRCW_SLAVE4 0 +#define CONFIG_SYS_HRCW_SLAVE5 0 +#define CONFIG_SYS_HRCW_SLAVE6 0 +#define CONFIG_SYS_HRCW_SLAVE7 0 /*----------------------------------------------------------------------- * Internal Memory Mapped Register */ -#define CFG_IMMR 0xFFF00000 +#define CONFIG_SYS_IMMR 0xFFF00000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR +#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 * - * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM + * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM * is mapped at SDRAM_BASE2_PRELIM. */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ /* * Internal Definitions @@ -354,16 +354,16 @@ /*----------------------------------------------------------------------- * Hardware Information Block */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ +#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ #if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /*----------------------------------------------------------------------- @@ -376,28 +376,28 @@ * * HID1 has only read-only information - nothing to set. */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ +#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ HID0_IFEM|HID0_ABE) -#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CFG_HID2 0 +#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) +#define CONFIG_SYS_HID2 0 /*----------------------------------------------------------------------- * RMR - Reset Mode Register 5-5 *----------------------------------------------------------------------- * turn on Checkstop Reset Enable */ -#define CFG_RMR RMR_CSRE +#define CONFIG_SYS_RMR RMR_CSRE /*----------------------------------------------------------------------- * BCR - Bus Configuration 4-25 *----------------------------------------------------------------------- */ #ifdef CONFIG_BUSMODE_60x -#define CFG_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ +#define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ #else #define BCR_APD01 0x10000000 -#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ +#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ #endif /*----------------------------------------------------------------------- @@ -405,9 +405,9 @@ *----------------------------------------------------------------------- */ #if 0 -#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) +#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) #else -#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) +#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) #endif @@ -418,10 +418,10 @@ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable */ #if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ +#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) #else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ +#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ SYPCR_SWRI|SYPCR_SWP) #endif /* CONFIG_WATCHDOG */ @@ -431,7 +431,7 @@ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, * and enable Time Counter */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) +#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 4-42 @@ -439,20 +439,20 @@ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable * Periodic timer */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) +#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) /*----------------------------------------------------------------------- * SCCR - System Clock Control 9-8 *----------------------------------------------------------------------- * Ensure DFBRG is Divide by 16 */ -#define CFG_SCCR 0 +#define CONFIG_SYS_SCCR 0 /*----------------------------------------------------------------------- * RCCR - RISC Controller Configuration 13-7 *----------------------------------------------------------------------- */ -#define CFG_RCCR 0 +#define CONFIG_SYS_RCCR 0 /* * Init Memory Controller: @@ -467,17 +467,17 @@ /* Initialize SDRAM on local bus */ -#define CFG_INIT_LOCAL_SDRAM +#define CONFIG_SYS_INIT_LOCAL_SDRAM #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ /* Minimum mask to separate preliminary * address ranges for CS[0:2] */ -#define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ -#define CFG_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ +#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ +#define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ -#define CFG_MPTPR 0x4000 +#define CONFIG_SYS_MPTPR 0x4000 /*----------------------------------------------------------------------------- * Address for Mode Register Set (MRS) command @@ -494,17 +494,17 @@ * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | *----------------------------------------------------------------------------- */ -#define CFG_MRS_OFFS 0x00000110 +#define CONFIG_SYS_MRS_OFFS 0x00000110 /* Bank 0 - FLASH */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ +#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ BRx_PS_64 |\ BRx_MS_GPCM_P |\ BRx_V) -#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ ORxG_CSNT |\ ORxG_ACS_DIV1 |\ ORxG_SCY_3_CLK |\ @@ -517,25 +517,25 @@ /* Bank 1 - 60x bus SDRAM */ -#define CFG_PSRT 0x20 -#define CFG_LSRT 0x20 -#ifndef CFG_RAMBOOT -#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ +#define CONFIG_SYS_PSRT 0x20 +#define CONFIG_SYS_LSRT 0x20 +#ifndef CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ BRx_PS_64 |\ BRx_MS_SDRAM_P |\ BRx_V) -#define CFG_OR1_PRELIM CFG_OR1_8COL +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL /* SDRAM initialization values for 8-column chips */ -#define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ +#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ ORxS_BPD_4 |\ ORxS_ROWST_PBI1_A7 |\ ORxS_NUMR_12) -#define CFG_PSDMR_8COL (PSDMR_PBI |\ +#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ PSDMR_SDAM_A15_IS_A5 |\ PSDMR_BSMA_A12_A14 |\ PSDMR_SDA10_PBI1_A8 |\ @@ -549,12 +549,12 @@ /* SDRAM initialization values for 9-column chips */ -#define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ +#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ ORxS_BPD_4 |\ ORxS_ROWST_PBI1_A5 |\ ORxS_NUMR_13) -#define CFG_PSDMR_9COL (PSDMR_PBI |\ +#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ PSDMR_SDAM_A16_IS_A5 |\ PSDMR_BSMA_A12_A14 |\ PSDMR_SDA10_PBI1_A7 |\ @@ -568,24 +568,24 @@ /* Bank 2 - Local bus SDRAM */ -#ifdef CFG_INIT_LOCAL_SDRAM -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ +#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM +#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ BRx_PS_32 |\ BRx_MS_SDRAM_L |\ BRx_V) -#define CFG_OR2_PRELIM CFG_OR2_8COL +#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL #define SDRAM_BASE2_PRELIM 0x80000000 /* SDRAM initialization values for 8-column chips */ -#define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ +#define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ ORxS_BPD_4 |\ ORxS_ROWST_PBI1_A8 |\ ORxS_NUMR_12) -#define CFG_LSDMR_8COL (PSDMR_PBI |\ +#define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\ PSDMR_SDAM_A15_IS_A5 |\ PSDMR_BSMA_A13_A15 |\ PSDMR_SDA10_PBI1_A9 |\ @@ -599,12 +599,12 @@ /* SDRAM initialization values for 9-column chips */ -#define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ +#define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ ORxS_BPD_4 |\ ORxS_ROWST_PBI1_A6 |\ ORxS_NUMR_13) -#define CFG_LSDMR_9COL (PSDMR_PBI |\ +#define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\ PSDMR_SDAM_A16_IS_A5 |\ PSDMR_BSMA_A13_A15 |\ PSDMR_SDA10_PBI1_A8 |\ @@ -616,53 +616,53 @@ PSDMR_WRC_2C |\ PSDMR_CL_2) -#endif /* CFG_INIT_LOCAL_SDRAM */ +#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ -#define CFG_CAN0_BASE 0xc0000000 -#define CFG_CAN1_BASE 0xc0008000 -#define CFG_FIOX_BASE 0xc0010000 -#define CFG_FDOHM_BASE 0xc0018000 -#define CFG_EXTPROM_BASE 0xc2000000 +#define CONFIG_SYS_CAN0_BASE 0xc0000000 +#define CONFIG_SYS_CAN1_BASE 0xc0008000 +#define CONFIG_SYS_FIOX_BASE 0xc0010000 +#define CONFIG_SYS_FDOHM_BASE 0xc0018000 +#define CONFIG_SYS_EXTPROM_BASE 0xc2000000 -#define CFG_CAN_SIZE 0x00000100 -#define CFG_FIOX_SIZE 0x00000020 -#define CFG_FDOHM_SIZE 0x00002000 -#define CFG_EXTPROM_BANK_SIZE 0x01000000 +#define CONFIG_SYS_CAN_SIZE 0x00000100 +#define CONFIG_SYS_FIOX_SIZE 0x00000020 +#define CONFIG_SYS_FDOHM_SIZE 0x00002000 +#define CONFIG_SYS_EXTPROM_BANK_SIZE 0x01000000 #define EXT_EEPROM_MAX_FLASH_BANKS 0x02 /* CS3 - CAN 0 */ -#define CFG_CAN0_BR3 ((CFG_CAN0_BASE & BRx_BA_MSK) |\ +#define CONFIG_SYS_CAN0_BR3 ((CONFIG_SYS_CAN0_BASE & BRx_BA_MSK) |\ BRx_PS_8 |\ BRx_MS_UPMA |\ BRx_V) -#define CFG_CAN0_OR3 (P2SZ_TO_AM(CFG_CAN_SIZE) |\ +#define CONFIG_SYS_CAN0_OR3 (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE) |\ ORxU_BI |\ ORxU_EHTR_4IDLE) /* CS4 - CAN 1 */ -#define CFG_CAN1_BR4 ((CFG_CAN1_BASE & BRx_BA_MSK) |\ +#define CONFIG_SYS_CAN1_BR4 ((CONFIG_SYS_CAN1_BASE & BRx_BA_MSK) |\ BRx_PS_8 |\ BRx_MS_UPMA |\ BRx_V) -#define CFG_CAN1_OR4 (P2SZ_TO_AM(CFG_CAN_SIZE) |\ +#define CONFIG_SYS_CAN1_OR4 (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE) |\ ORxU_BI |\ ORxU_EHTR_4IDLE) /* CS5 - Extended PROM (16MB optional) */ -#define CFG_EXTPROM_BR5 ((CFG_EXTPROM_BASE & BRx_BA_MSK)|\ +#define CONFIG_SYS_EXTPROM_BR5 ((CONFIG_SYS_EXTPROM_BASE & BRx_BA_MSK)|\ BRx_PS_32 |\ BRx_MS_GPCM_P |\ BRx_V) -#define CFG_EXTPROM_OR5 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\ +#define CONFIG_SYS_EXTPROM_OR5 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\ ORxG_CSNT |\ ORxG_ACS_DIV4 |\ ORxG_SCY_5_CLK |\ @@ -670,13 +670,13 @@ /* CS6 - Extended PROM (16MB optional) */ -#define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE + \ - CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\ +#define CONFIG_SYS_EXTPROM_BR6 (((CONFIG_SYS_EXTPROM_BASE + \ + CONFIG_SYS_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\ BRx_PS_32 |\ BRx_MS_GPCM_P |\ BRx_V) -#define CFG_EXTPROM_OR6 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\ +#define CONFIG_SYS_EXTPROM_OR6 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\ ORxG_CSNT |\ ORxG_ACS_DIV4 |\ ORxG_SCY_5_CLK |\ @@ -684,37 +684,37 @@ /* CS7 - FPGA FIOX: Glue Logic */ -#define CFG_FIOX_BR7 ((CFG_FIOX_BASE & BRx_BA_MSK) |\ +#define CONFIG_SYS_FIOX_BR7 ((CONFIG_SYS_FIOX_BASE & BRx_BA_MSK) |\ BRx_PS_32 |\ BRx_MS_GPCM_P |\ BRx_V) -#define CFG_FIOX_OR7 (P2SZ_TO_AM(CFG_FIOX_SIZE) |\ +#define CONFIG_SYS_FIOX_OR7 (P2SZ_TO_AM(CONFIG_SYS_FIOX_SIZE) |\ ORxG_ACS_DIV4 |\ ORxG_SCY_5_CLK |\ ORxG_TRLX) /* CS8 - FPGA DOH Master */ -#define CFG_FDOHM_BR8 ((CFG_FDOHM_BASE & BRx_BA_MSK) |\ +#define CONFIG_SYS_FDOHM_BR8 ((CONFIG_SYS_FDOHM_BASE & BRx_BA_MSK) |\ BRx_PS_16 |\ BRx_MS_GPCM_P |\ BRx_V) -#define CFG_FDOHM_OR8 (P2SZ_TO_AM(CFG_FDOHM_SIZE) |\ +#define CONFIG_SYS_FDOHM_OR8 (P2SZ_TO_AM(CONFIG_SYS_FDOHM_SIZE) |\ ORxG_ACS_DIV4 |\ ORxG_SCY_5_CLK |\ ORxG_TRLX) /* FPGA configuration */ -#define CFG_PD_FIOX_PROG (1 << (31- 5)) /* PD 5 */ -#define CFG_PD_FIOX_DONE (1 << (31-28)) /* PD 28 */ -#define CFG_PD_FIOX_INIT (1 << (31-29)) /* PD 29 */ +#define CONFIG_SYS_PD_FIOX_PROG (1 << (31- 5)) /* PD 5 */ +#define CONFIG_SYS_PD_FIOX_DONE (1 << (31-28)) /* PD 28 */ +#define CONFIG_SYS_PD_FIOX_INIT (1 << (31-29)) /* PD 29 */ -#define CFG_PD_FDOHM_PROG (1 << (31- 4)) /* PD 4 */ -#define CFG_PD_FDOHM_DONE (1 << (31-26)) /* PD 26 */ -#define CFG_PD_FDOHM_INIT (1 << (31-27)) /* PD 27 */ +#define CONFIG_SYS_PD_FDOHM_PROG (1 << (31- 4)) /* PD 4 */ +#define CONFIG_SYS_PD_FDOHM_DONE (1 << (31-26)) /* PD 26 */ +#define CONFIG_SYS_PD_FDOHM_INIT (1 << (31-27)) /* PD 27 */ #endif /* __CONFIG_H */ |