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-rw-r--r--include/asm-sh/cpu_sh7750.h212
-rw-r--r--include/asm-sh/ptrace.h2
-rw-r--r--include/asm-sh/system.h32
3 files changed, 123 insertions, 123 deletions
diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h
index 3c3c30980aa..4e43a465e6a 100644
--- a/include/asm-sh/cpu_sh7750.h
+++ b/include/asm-sh/cpu_sh7750.h
@@ -32,108 +32,108 @@
#endif
/* OCN */
-#define PTEH 0xFF000000
-#define PTEL 0xFF000004
-#define TTB 0xFF000008
-#define TEA 0xFF00000C
-#define MMUCR 0xFF000010
-#define BASRA 0xFF000014
+#define PTEH 0xFF000000
+#define PTEL 0xFF000004
+#define TTB 0xFF000008
+#define TEA 0xFF00000C
+#define MMUCR 0xFF000010
+#define BASRA 0xFF000014
#define BASRB 0xFF000018
#define CCR 0xFF00001C
-#define TRA 0xFF000020
-#define EXPEVT 0xFF000024
-#define INTEVT 0xFF000028
-#define PTEA 0xFF000034
-#define QACR0 0xFF000038
-#define QACR1 0xFF00003C
+#define TRA 0xFF000020
+#define EXPEVT 0xFF000024
+#define INTEVT 0xFF000028
+#define PTEA 0xFF000034
+#define QACR0 0xFF000038
+#define QACR1 0xFF00003C
/* UBC */
-#define BARA 0xFF200000
-#define BAMRA 0xFF200004
-#define BBRA 0xFF200008
-#define BARB 0xFF20000C
-#define BAMRB 0xFF200010
-#define BBRB 0xFF200014
-#define BDRB 0xFF200018
-#define BDMRB 0xFF20001C
-#define BRCR 0xFF200020
+#define BARA 0xFF200000
+#define BAMRA 0xFF200004
+#define BBRA 0xFF200008
+#define BARB 0xFF20000C
+#define BAMRB 0xFF200010
+#define BBRB 0xFF200014
+#define BDRB 0xFF200018
+#define BDMRB 0xFF20001C
+#define BRCR 0xFF200020
/* BSC */
#define BCR1 0xFF800000
#define BCR2 0xFF800004
-#define BCR3 0xFF800050
+#define BCR3 0xFF800050
#define BCR4 0xFE0A00F0
-#define WCR1 0xFF800008
-#define WCR2 0xFF80000C
-#define WCR3 0xFF800010
-#define MCR 0xFF800014
-#define PCR 0xFF800018
-#define RTCSR 0xFF80001C
-#define RTCNT 0xFF800020
-#define RTCOR 0xFF800024
-#define RFCR 0xFF800028
-#define PCTRA 0xFF80002C
-#define PDTRA 0xFF800030
-#define PCTRB 0xFF800040
-#define PDTRB 0xFF800044
-#define GPIOIC 0xFF800048
+#define WCR1 0xFF800008
+#define WCR2 0xFF80000C
+#define WCR3 0xFF800010
+#define MCR 0xFF800014
+#define PCR 0xFF800018
+#define RTCSR 0xFF80001C
+#define RTCNT 0xFF800020
+#define RTCOR 0xFF800024
+#define RFCR 0xFF800028
+#define PCTRA 0xFF80002C
+#define PDTRA 0xFF800030
+#define PCTRB 0xFF800040
+#define PDTRB 0xFF800044
+#define GPIOIC 0xFF800048
/* DMAC */
-#define SAR0 0xFFA00000
-#define DAR0 0xFFA00004
+#define SAR0 0xFFA00000
+#define DAR0 0xFFA00004
#define DMATCR0 0xFFA00008
#define CHCR0 0xFFA0000C
-#define SAR1 0xFFA00010
-#define DAR1 0xFFA00014
+#define SAR1 0xFFA00010
+#define DAR1 0xFFA00014
#define DMATCR1 0xFFA00018
-#define CHCR1 0xFFA0001C
-#define SAR2 0xFFA00020
-#define DAR2 0xFFA00024
+#define CHCR1 0xFFA0001C
+#define SAR2 0xFFA00020
+#define DAR2 0xFFA00024
#define DMATCR2 0xFFA00028
-#define CHCR2 0xFFA0002C
-#define SAR3 0xFFA00030
-#define DAR3 0xFFA00034
+#define CHCR2 0xFFA0002C
+#define SAR3 0xFFA00030
+#define DAR3 0xFFA00034
#define DMATCR3 0xFFA00038
-#define CHCR3 0xFFA0003C
-#define DMAOR 0xFFA00040
+#define CHCR3 0xFFA0003C
+#define DMAOR 0xFFA00040
#define SAR4 0xFFA00050
-#define DAR4 0xFFA00054
+#define DAR4 0xFFA00054
#define DMATCR4 0xFFA00058
/* CPG */
-#define FRQCR 0xFFC00000
-#define STBCR 0xFFC00004
-#define WTCNT 0xFFC00008
-#define WTCSR 0xFFC0000C
-#define STBCR2 0xFFC00010
+#define FRQCR 0xFFC00000
+#define STBCR 0xFFC00004
+#define WTCNT 0xFFC00008
+#define WTCSR 0xFFC0000C
+#define STBCR2 0xFFC00010
/* RTC */
#define R64CNT 0xFFC80000
#define RSECCNT 0xFFC80004
#define RMINCNT 0xFFC80008
-#define RHRCNT 0xFFC8000C
-#define RWKCNT 0xFFC80010
+#define RHRCNT 0xFFC8000C
+#define RWKCNT 0xFFC80010
#define RDAYCNT 0xFFC80014
#define RMONCNT 0xFFC80018
-#define RYRCNT 0xFFC8001C
-#define RSECAR 0xFFC80020
-#define RMINAR 0xFFC80024
-#define RHRAR 0xFFC80028
-#define RWKAR 0xFFC8002C
-#define RDAYAR 0xFFC80030
-#define RMONAR 0xFFC80034
-#define RCR1 0xFFC80038
-#define RCR2 0xFFC8003C
-#define RCR3 0xFFC80050
-#define RYRAR 0xFFC80054
+#define RYRCNT 0xFFC8001C
+#define RSECAR 0xFFC80020
+#define RMINAR 0xFFC80024
+#define RHRAR 0xFFC80028
+#define RWKAR 0xFFC8002C
+#define RDAYAR 0xFFC80030
+#define RMONAR 0xFFC80034
+#define RCR1 0xFFC80038
+#define RCR2 0xFFC8003C
+#define RCR3 0xFFC80050
+#define RYRAR 0xFFC80054
/* ICR */
-#define ICR 0xFFD00000
-#define IPRA 0xFFD00004
-#define IPRB 0xFFD00008
+#define ICR 0xFFD00000
+#define IPRA 0xFFD00004
+#define IPRB 0xFFD00008
#define IPRC 0xFFD0000C
-#define IPRD 0xFFD00010
-#define INTPRI 0xFE080000
+#define IPRD 0xFFD00010
+#define INTPRI 0xFE080000
#define INTREQ 0xFE080020
#define INTMSK 0xFE080040
#define INTMSKCL 0xFE080060
@@ -143,54 +143,54 @@
#define CLKSTPCLR 0xFE0A0008
/* TMU */
-#define TSTR2 0xFE100004
-#define TCOR3 0xFE100008
-#define TCNT3 0xFE10000C
-#define TCR3 0xFE100010
-#define TCOR4 0xFE100014
-#define TCNT4 0xFE100018
-#define TCR4 0xFE10001C
-#define TOCR 0xFFD80000
-#define TSTR0 0xFFD80004
+#define TSTR2 0xFE100004
+#define TCOR3 0xFE100008
+#define TCNT3 0xFE10000C
+#define TCR3 0xFE100010
+#define TCOR4 0xFE100014
+#define TCNT4 0xFE100018
+#define TCR4 0xFE10001C
+#define TOCR 0xFFD80000
+#define TSTR0 0xFFD80004
#define TCOR0 0xFFD80008
-#define TCNT0 0xFFD8000C
-#define TCR0 0xFFD80010
-#define TCOR1 0xFFD80014
-#define TCNT1 0xFFD80018
-#define TCR1 0xFFD8001C
-#define TCOR2 0xFFD80020
-#define TCNT2 0xFFD80024
-#define TCR2 0xFFD80028
-#define TCPR2 0xFFD8002C
+#define TCNT0 0xFFD8000C
+#define TCR0 0xFFD80010
+#define TCOR1 0xFFD80014
+#define TCNT1 0xFFD80018
+#define TCR1 0xFFD8001C
+#define TCOR2 0xFFD80020
+#define TCNT2 0xFFD80024
+#define TCR2 0xFFD80028
+#define TCPR2 0xFFD8002C
#define TSTR TSTR0
/* SCI */
-#define SCSMR1 0xFFE00000
-#define SCBRR1 0xFFE00004
-#define SCSCR1 0xFFE00008
-#define SCTDR1 0xFFE0000C
-#define SCSSR1 0xFFE00010
-#define SCRDR1 0xFFE00014
+#define SCSMR1 0xFFE00000
+#define SCBRR1 0xFFE00004
+#define SCSCR1 0xFFE00008
+#define SCTDR1 0xFFE0000C
+#define SCSSR1 0xFFE00010
+#define SCRDR1 0xFFE00014
#define SCSCMR1 0xFFE00018
#define SCSPTR1 0xFFE0001C
#define SCF0_BASE SCSMR1
/* SCIF */
-#define SCSMR2 0xFFE80000
-#define SCBRR2 0xFFE80004
-#define SCSCR2 0xFFE80008
+#define SCSMR2 0xFFE80000
+#define SCBRR2 0xFFE80004
+#define SCSCR2 0xFFE80008
#define SCFTDR2 0xFFE8000C
-#define SCFSR2 0xFFE80010
+#define SCFSR2 0xFFE80010
#define SCFRDR2 0xFFE80014
-#define SCFCR2 0xFFE80018
-#define SCFDR2 0xFFE8001C
+#define SCFCR2 0xFFE80018
+#define SCFDR2 0xFFE8001C
#define SCSPTR2 0xFFE80020
-#define SCLSR2 0xFFE80024
+#define SCLSR2 0xFFE80024
#define SCIF1_BASE SCSMR2
/* H-UDI */
-#define SDIR 0xFFF00000
-#define SDDR 0xFFF00008
-#define SDINT 0xFFF00014
+#define SDIR 0xFFF00000
+#define SDDR 0xFFF00008
+#define SDINT 0xFFF00014
#endif /* _ASM_CPU_SH7750_H_ */
diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h
index 14cc1aca639..16252cc25b0 100644
--- a/include/asm-sh/ptrace.h
+++ b/include/asm-sh/ptrace.h
@@ -28,7 +28,7 @@
#define REG_PR 17
#define REG_SR 18
-#define REG_GBR 19
+#define REG_GBR 19
#define REG_MACH 20
#define REG_MACL 21
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
index b353bc5c3b8..a62c42261d7 100644
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@@ -23,21 +23,21 @@
register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \
register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \
register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \
- __asm__ __volatile__ (".balign 4\n\t" \
- "stc.l gbr, @-r15\n\t" \
- "sts.l pr, @-r15\n\t" \
- "mov.l r8, @-r15\n\t" \
- "mov.l r9, @-r15\n\t" \
- "mov.l r10, @-r15\n\t" \
- "mov.l r11, @-r15\n\t" \
- "mov.l r12, @-r15\n\t" \
- "mov.l r13, @-r15\n\t" \
- "mov.l r14, @-r15\n\t" \
+ __asm__ __volatile__ (".balign 4\n\t" \
+ "stc.l gbr, @-r15\n\t" \
+ "sts.l pr, @-r15\n\t" \
+ "mov.l r8, @-r15\n\t" \
+ "mov.l r9, @-r15\n\t" \
+ "mov.l r10, @-r15\n\t" \
+ "mov.l r11, @-r15\n\t" \
+ "mov.l r12, @-r15\n\t" \
+ "mov.l r13, @-r15\n\t" \
+ "mov.l r14, @-r15\n\t" \
"mov.l r15, @r1 ! save SP\n\t" \
"mov.l @r6, r15 ! change to new stack\n\t" \
- "mova 1f, %0\n\t" \
- "mov.l %0, @r2 ! save PC\n\t" \
- "mov.l 2f, %0\n\t" \
+ "mova 1f, %0\n\t" \
+ "mov.l %0, @r2 ! save PC\n\t" \
+ "mov.l 2f, %0\n\t" \
"jmp @%0 ! call __switch_to\n\t" \
" lds r7, pr ! with return to new PC\n\t" \
".balign 4\n" \
@@ -54,8 +54,8 @@
"lds.l @r15+, pr\n\t" \
"ldc.l @r15+, gbr\n\t" \
: "=z" (__last) \
- : "r" (__ts1), "r" (__ts2), "r" (__ts4), \
- "r" (__ts5), "r" (__ts6), "r" (__ts7) \
+ : "r" (__ts1), "r" (__ts2), "r" (__ts4), \
+ "r" (__ts5), "r" (__ts6), "r" (__ts7) \
: "r3", "t"); \
last = __last; \
} while (0)
@@ -145,7 +145,7 @@ do { \
"mov.l 1f, %0\n\t" \
"or %1, %0\n\t" \
"jmp @%0\n\t" \
- " nop\n\t" \
+ " nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-16 15:16:34 +0000