diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/fsl/ctrl_regs.c | 20 | ||||
| -rw-r--r-- | drivers/ddr/fsl/mpc85xx_ddr_gen1.c | 3 |
2 files changed, 4 insertions, 19 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index b80034478e1..b5122d1a1c3 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -1863,25 +1863,13 @@ static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) { - unsigned int clk_adjust; /* Clock adjust */ - unsigned int ss_en = 0; /* Source synchronous enable */ - -#if defined(CONFIG_ARCH_MPC8555) - /* Per FSL Application Note: AN2805 */ - ss_en = 1; -#endif - if (fsl_ddr_get_version(0) >= 0x40701) { + if (fsl_ddr_get_version(0) >= 0x40701) /* clk_adjust in 5-bits on T-series and LS-series */ - clk_adjust = (popts->clk_adjust & 0x1F) << 22; - } else { + ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0x1F) << 22; + else /* clk_adjust in 4-bits on earlier MPC85xx and P-series */ - clk_adjust = (popts->clk_adjust & 0xF) << 23; - } + ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0xF) << 23; - ddr->ddr_sdram_clk_cntl = (0 - | ((ss_en & 0x1) << 31) - | clk_adjust - ); debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); } diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c index c642a5b1eec..9c2ddeaf932 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c @@ -48,9 +48,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); -#if defined(CONFIG_ARCH_MPC8555) - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); -#endif /* * 200 painful micro-seconds must elapse between |