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-rw-r--r--drivers/i2c/Makefile1
-rw-r--r--drivers/i2c/s3c44b0_i2c.c299
-rw-r--r--drivers/mmc/fsl_esdhc.c2
-rw-r--r--drivers/mtd/nand/mxs_nand.c3
-rw-r--r--drivers/net/cpsw.c10
-rw-r--r--drivers/net/fec_mxc.c4
-rw-r--r--drivers/net/fec_mxc.h4
-rw-r--r--drivers/power/pmic/Makefile2
-rw-r--r--drivers/power/pmic/pmic_tps65217.c109
-rw-r--r--drivers/power/pmic/pmic_tps65910.c83
-rw-r--r--drivers/rtc/Makefile1
-rw-r--r--drivers/rtc/s3c44b0_rtc.c84
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/serial.c2
-rw-r--r--drivers/serial/serial_s3c44b0.c216
15 files changed, 212 insertions, 609 deletions
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 37ccbd1423..df3092eaf0 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -21,7 +21,6 @@ COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o
COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
-COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
diff --git a/drivers/i2c/s3c44b0_i2c.c b/drivers/i2c/s3c44b0_i2c.c
deleted file mode 100644
index 8445e01caf..0000000000
--- a/drivers/i2c/s3c44b0_i2c.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/hardware.h>
-
-/*
- * Initialization, must be called once on start up, may be called
- * repeatedly to change the speed and slave addresses.
- */
-void i2c_init(int speed, int slaveaddr)
-{
- /*
- setting up I2C support
- */
- unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF;
-
- save_F = PCONF;
- save_PF = PUPF;
-
- rPCONF = ((save_F & ~(0xF))| 0xa);
- rPUPF = (save_PF | 0x3);
- PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/
- PUPF = rPUPF; /* Disable pull-up */
-
- /* Configuring pin for WC pin of EEprom */
- rPCONA = PCONA;
- rPCONA &= ~(1<<9);
- PCONA = rPCONA;
-
- rPDATA = PDATA;
- rPDATA &= ~(1<<9);
- PDATA = rPDATA;
-
- /*
- Enable ACK, IICCLK=MCLK/16, enable interrupt
- 75MHz/16/(12+1) = 390625 Hz
- */
- rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC);
- IICCON = rIICCON;
-
- IICADD = slaveaddr;
-}
-
-/*
- * Probe the given I2C chip address. Returns 0 if a chip responded,
- * not 0 on failure.
- */
-int i2c_probe(uchar chip)
-{
- /*
- not implemented
- */
-
- printf("i2c_probe chip %d\n", (int) chip);
- return -1;
-}
-
-/*
- * Read/Write interface:
- * chip: I2C chip address, range 0..127
- * addr: Memory (register) address within the chip
- * alen: Number of bytes to use for addr (typically 1, 2 for larger
- * memories, 0 for register type devices with only one
- * register)
- * buffer: Where to read/write the data
- * len: How many bytes to read/write
- *
- * Returns: 0 on success, not 0 on failure
- */
-
-#define S3C44B0X_rIIC_INTPEND (1<<4)
-#define S3C44B0X_rIIC_LAST_RECEIV_BIT (1<<0)
-#define S3C44B0X_rIIC_INTERRUPT_ENABLE (1<<5)
-#define S3C44B0_IIC_TIMEOUT 100
-
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
-
- int k, j, temp;
- u32 rIICSTAT;
-
- /*
- send the device offset
- */
-
- rIICSTAT = 0xD0;
- IICSTAT = rIICSTAT;
-
- IICDS = chip; /* this is a write operation... */
-
- rIICSTAT |= (1<<5);
- IICSTAT = rIICSTAT;
-
- for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
- temp = IICCON;
- if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
- break;
- udelay(2000);
- }
- if (k==S3C44B0_IIC_TIMEOUT)
- return -1;
-
- /* wait and check ACK */
- temp = IICSTAT;
- if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
- return -1;
-
- IICDS = addr;
- IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
-
- /* wait and check ACK */
- for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
- temp = IICCON;
- if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
- break;
- udelay(2000);
- }
- if (k==S3C44B0_IIC_TIMEOUT)
- return -1;
-
- temp = IICSTAT;
- if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
- return -1;
-
- /*
- now we can start with the read operation...
- */
-
- IICDS = chip | 0x01; /* this is a read operation... */
-
- rIICSTAT = 0x90; /*master recv*/
- rIICSTAT |= (1<<5);
- IICSTAT = rIICSTAT;
-
- IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
-
- /* wait and check ACK */
- for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
- temp = IICCON;
- if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
- break;
- udelay(2000);
- }
- if (k==S3C44B0_IIC_TIMEOUT)
- return -1;
-
- temp = IICSTAT;
- if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
- return -1;
-
- for (j=0; j<len-1; j++) {
-
- /*clear pending bit to resume */
-
- temp = IICCON & ~(S3C44B0X_rIIC_INTPEND);
- IICCON = temp;
-
- /* wait and check ACK */
- for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
- temp = IICCON;
- if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
- break;
- udelay(2000);
- }
- if (k==S3C44B0_IIC_TIMEOUT)
- return -1;
-
-
- buffer[j] = IICDS; /*save readed data*/
-
- } /*end for(j)*/
-
- /*
- reading the last data
- unset ACK generation
- */
- temp = IICCON & ~(S3C44B0X_rIIC_INTPEND | (1<<7));
- IICCON = temp;
-
- /* wait but NOT check ACK */
- for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
- temp = IICCON;
- if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
- break;
- udelay(2000);
- }
- if (k==S3C44B0_IIC_TIMEOUT)
- return -1;
-
- buffer[j] = IICDS; /*save readed data*/
-
- rIICSTAT = 0x90; /*master recv*/
-
- /* Write operation Terminate sending STOP */
- IICSTAT = rIICSTAT;
- /*Clear Int Pending Bit to RESUME*/
- temp = IICCON;
- IICCON = temp & (~S3C44B0X_rIIC_INTPEND);
-
- IICCON = IICCON | (1<<7); /*restore ACK generation*/
-
- return 0;
-}
-
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
- int j, k;
- u32 rIICSTAT, temp;
-
-
- /*
- send the device offset
- */
-
- rIICSTAT = 0xD0;
- IICSTAT = rIICSTAT;
-
- IICDS = chip; /* this is a write operation... */
-
- rIICSTAT |= (1<<5);
- IICSTAT = rIICSTAT;
-
- IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
-
- /* wait and check ACK */
- for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
- temp = IICCON;
- if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
- break;
- udelay(2000);
- }
- if (k==S3C44B0_IIC_TIMEOUT)
- return -1;
-
- temp = IICSTAT;
- if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
- return -1;
-
- IICDS = addr;
- IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
-
- /* wait and check ACK */
- for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
- temp = IICCON;
- if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
- break;
- udelay(2000);
- }
- if (k==S3C44B0_IIC_TIMEOUT)
- return -1;
-
- temp = IICSTAT;
- if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
- return -1;
-
- /*
- now we can start with the read write operation
- */
- for (j=0; j<len; j++) {
-
- IICDS = buffer[j]; /*prerare data to write*/
-
- /*clear pending bit to resume*/
-
- temp = IICCON & ~(S3C44B0X_rIIC_INTPEND);
- IICCON = temp;
-
- /* wait but NOT check ACK */
- for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
- temp = IICCON;
- if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
- break;
-
- udelay(2000);
- }
-
- if (k==S3C44B0_IIC_TIMEOUT)
- return -1;
-
- } /* end for(j) */
-
- /* sending stop to terminate */
- rIICSTAT = 0xD0; /*master send*/
- IICSTAT = rIICSTAT;
- /*Clear Int Pending Bit to RESUME*/
- temp = IICCON;
- IICCON = temp & (~S3C44B0X_rIIC_INTPEND);
-
- return 0;
-}
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index f87e647881..a7170b49db 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -518,6 +518,8 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
return -1;
mmc = malloc(sizeof(struct mmc));
+ if (!mmc)
+ return -ENOMEM;
sprintf(mmc->name, "FSL_SDHC");
regs = (struct fsl_esdhc *)cfg->esdhc_base;
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 378f8c513a..036c113ad3 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -155,6 +155,9 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
if (page_oob_size == 218)
return 16;
+
+ if (page_oob_size == 224)
+ return 16;
}
return 0;
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 9bab71a212..39240d9662 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -568,9 +568,14 @@ static void cpsw_set_slave_mac(struct cpsw_slave *slave,
static void cpsw_slave_update_link(struct cpsw_slave *slave,
struct cpsw_priv *priv, int *link)
{
- struct phy_device *phy = priv->phydev;
+ struct phy_device *phy;
u32 mac_control = 0;
+ phy = priv->phydev;
+
+ if (!phy)
+ return;
+
phy_startup(phy);
*link = phy->link;
@@ -947,6 +952,9 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
dev,
slave->data->phy_if);
+ if (!phydev)
+ return -1;
+
phydev->supported &= supported;
phydev->advertising = phydev->supported;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 690e5724b4..107cd6ecc5 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -453,7 +453,7 @@ static int fec_open(struct eth_device *edev)
*/
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
&fec->eth->ecntrl);
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
udelay(100);
/*
* setup the MII gasket for RMII mode
@@ -794,7 +794,7 @@ static int fec_recv(struct eth_device *dev)
uint16_t bd_status;
uint32_t addr, size, end;
int i;
- uchar buff[FEC_MAX_PKT_SIZE] __aligned(ARCH_DMA_MINALIGN);
+ ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
/*
* Check if any critical events have happened
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 4b4f8b7983..0717cc6c31 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -135,7 +135,7 @@ struct ethernet_regs {
uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */
uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */
uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */
@@ -202,7 +202,7 @@ struct ethernet_regs {
#define FEC_X_DES_ACTIVE_TDAR 0x01000000
#define FEC_R_DES_ACTIVE_RDAR 0x01000000
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
/* defines for MIIGSK */
/* RMII frequency control: 0=50MHz, 1=5MHz */
#define MIIGSK_CFGR_FRCONT (1 << 6)
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index f054470552..11b3d030e4 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -13,6 +13,8 @@ COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
+COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
+COBJS-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/power/pmic/pmic_tps65217.c b/drivers/power/pmic/pmic_tps65217.c
new file mode 100644
index 0000000000..36e9024bf8
--- /dev/null
+++ b/drivers/power/pmic/pmic_tps65217.c
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+
+/**
+ * tps65217_reg_read() - Generic function that can read a TPS65217 register
+ * @src_reg: Source register address
+ * @src_val: Address of destination variable
+ * @return: 0 for success, not 0 on failure.
+ */
+int tps65217_reg_read(uchar src_reg, uchar *src_val)
+{
+ return i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1);
+}
+
+/**
+ * tps65217_reg_write() - Generic function that can write a TPS65217 PMIC
+ * register or bit field regardless of protection
+ * level.
+ *
+ * @prot_level: Register password protection. Use
+ * TPS65217_PROT_LEVEL_NONE,
+ * TPS65217_PROT_LEVEL_1 or TPS65217_PROT_LEVEL_2
+ * @dest_reg: Register address to write.
+ * @dest_val: Value to write.
+ * @mask: Bit mask (8 bits) to be applied. Function will only
+ * change bits that are set in the bit mask.
+ *
+ * @return: 0 for success, not 0 on failure, as per the i2c API
+ */
+int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
+ uchar mask)
+{
+ uchar read_val;
+ uchar xor_reg;
+ int ret;
+
+ /*
+ * If we are affecting only a bit field, read dest_reg and apply the
+ * mask
+ */
+ if (mask != TPS65217_MASK_ALL_BITS) {
+ ret = i2c_read(TPS65217_CHIP_PM, dest_reg, 1, &read_val, 1);
+ if (ret)
+ return ret;
+ read_val &= (~mask);
+ read_val |= (dest_val & mask);
+ dest_val = read_val;
+ }
+
+ if (prot_level > 0) {
+ xor_reg = dest_reg ^ TPS65217_PASSWORD_UNLOCK;
+ ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1,
+ &xor_reg, 1);
+ if (ret)
+ return ret;
+ }
+
+ ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1);
+ if (ret)
+ return ret;
+
+ if (prot_level == TPS65217_PROT_LEVEL_2) {
+ ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1,
+ &xor_reg, 1);
+ if (ret)
+ return ret;
+
+ ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * tps65217_voltage_update() - Function to change a voltage level, as this
+ * is a multi-step process.
+ * @dc_cntrl_reg: DC voltage control register to change.
+ * @volt_sel: New value for the voltage register
+ * @return: 0 for success, not 0 on failure.
+ */
+int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
+{
+ if ((dc_cntrl_reg != TPS65217_DEFDCDC1) &&
+ (dc_cntrl_reg != TPS65217_DEFDCDC2) &&
+ (dc_cntrl_reg != TPS65217_DEFDCDC3))
+ return 1;
+
+ /* set voltage level */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, dc_cntrl_reg, volt_sel,
+ TPS65217_MASK_ALL_BITS))
+ return 1;
+
+ /* set GO bit to initiate voltage transition */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFSLEW,
+ TPS65217_DCDC_GO, TPS65217_DCDC_GO))
+ return 1;
+
+ return 0;
+}
diff --git a/drivers/power/pmic/pmic_tps65910.c b/drivers/power/pmic/pmic_tps65910.c
new file mode 100644
index 0000000000..7ee1160e0d
--- /dev/null
+++ b/drivers/power/pmic/pmic_tps65910.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <power/tps65910.h>
+
+/*
+ * tps65910_set_i2c_control() - Set the TPS65910 to be controlled via the I2C
+ * interface.
+ * @return: 0 on success, not 0 on failure
+ */
+int tps65910_set_i2c_control(void)
+{
+ int ret;
+ uchar buf;
+
+ /* VDD1/2 voltage selection register access by control i/f */
+ ret = i2c_read(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1,
+ &buf, 1);
+
+ if (ret)
+ return ret;
+
+ buf |= TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
+
+ return i2c_write(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1,
+ &buf, 1);
+}
+
+/*
+ * tps65910_voltage_update() - Voltage switching for MPU frequency switching.
+ * @module: mpu - 0, core - 1
+ * @vddx_op_vol_sel: vdd voltage to set
+ * @return: 0 on success, not 0 on failure
+ */
+int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
+{
+ uchar buf;
+ unsigned int reg_offset;
+ int ret;
+
+ if (module == MPU)
+ reg_offset = TPS65910_VDD1_OP_REG;
+ else
+ reg_offset = TPS65910_VDD2_OP_REG;
+
+ /* Select VDDx OP */
+ ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
+ if (ret)
+ return ret;
+
+ buf &= ~TPS65910_OP_REG_CMD_MASK;
+
+ ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
+ if (ret)
+ return ret;
+
+ /* Configure VDDx OP Voltage */
+ ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
+ if (ret)
+ return ret;
+
+ buf &= ~TPS65910_OP_REG_SEL_MASK;
+ buf |= vddx_op_vol_sel;
+
+ ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
+ if (ret)
+ return ret;
+
+ ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
+ if (ret)
+ return ret;
+
+ if ((buf & TPS65910_OP_REG_SEL_MASK) != vddx_op_vol_sel)
+ return 1;
+
+ return 0;
+}
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index b477c23ebd..dcc0632ff2 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -53,7 +53,6 @@ COBJS-$(CONFIG_RTC_RTC4543) += rtc4543.o
COBJS-$(CONFIG_RTC_RV3029) += rv3029.o
COBJS-$(CONFIG_RTC_RX8025) += rx8025.o
COBJS-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
-COBJS-$(CONFIG_RTC_S3C44B0) += s3c44b0_rtc.o
COBJS-$(CONFIG_RTC_X1205) += x1205.o
COBJS := $(sort $(COBJS-y))
diff --git a/drivers/rtc/s3c44b0_rtc.c b/drivers/rtc/s3c44b0_rtc.c
deleted file mode 100644
index de7898cc34..0000000000
--- a/drivers/rtc/s3c44b0_rtc.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * S3C44B0 CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/hardware.h>
-#include <rtc.h>
-
-int rtc_get (struct rtc_time* tm)
-{
- RTCCON |= 1;
- tm->tm_year = bcd2bin(BCDYEAR);
- tm->tm_mon = bcd2bin(BCDMON);
- tm->tm_wday = bcd2bin(BCDDATE);
- tm->tm_mday = bcd2bin(BCDDAY);
- tm->tm_hour = bcd2bin(BCDHOUR);
- tm->tm_min = bcd2bin(BCDMIN);
- tm->tm_sec = bcd2bin(BCDSEC);
-
- if (tm->tm_sec==0) {
- /* we have to re-read the rtc data because of the "one second deviation" problem */
- /* see RTC datasheet for more info about it */
- tm->tm_year = bcd2bin(BCDYEAR);
- tm->tm_mon = bcd2bin(BCDMON);
- tm->tm_mday = bcd2bin(BCDDAY);
- tm->tm_wday = bcd2bin(BCDDATE);
- tm->tm_hour = bcd2bin(BCDHOUR);
- tm->tm_min = bcd2bin(BCDMIN);
- tm->tm_sec = bcd2bin(BCDSEC);
- }
-
- RTCCON &= ~1;
-
- if(tm->tm_year >= 70)
- tm->tm_year += 1900;
- else
- tm->tm_year += 2000;
-
- return 0;
-}
-
-int rtc_set (struct rtc_time* tm)
-{
- if(tm->tm_year < 2000)
- tm->tm_year -= 1900;
- else
- tm->tm_year -= 2000;
-
- RTCCON |= 1;
- BCDYEAR = bin2bcd(tm->tm_year);
- BCDMON = bin2bcd(tm->tm_mon);
- BCDDAY = bin2bcd(tm->tm_mday);
- BCDDATE = bin2bcd(tm->tm_wday);
- BCDHOUR = bin2bcd(tm->tm_hour);
- BCDMIN = bin2bcd(tm->tm_min);
- BCDSEC = bin2bcd(tm->tm_sec);
- RTCCON &= 1;
-
- return 0;
-}
-
-void rtc_reset (void)
-{
- RTCCON |= 1;
- BCDYEAR = 0;
- BCDMON = 0;
- BCDDAY = 0;
- BCDDATE = 0;
- BCDHOUR = 0;
- BCDMIN = 0;
- BCDSEC = 0;
- RTCCON &= 1;
-}
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 4c45bfa363..e1fd7a5dc8 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -31,7 +31,6 @@ COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
COBJS-$(CONFIG_PXA_SERIAL) += serial_pxa.o
COBJS-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o
COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
-COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 35dc61e020..df2b84aaaf 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -156,7 +156,6 @@ serial_initfunc(lh7a40x_serial_initialize);
serial_initfunc(max3100_serial_initialize);
serial_initfunc(mxc_serial_initialize);
serial_initfunc(pl01x_serial_initialize);
-serial_initfunc(s3c44b0_serial_initialize);
serial_initfunc(sa1100_serial_initialize);
serial_initfunc(sh_serial_initialize);
serial_initfunc(arm_dcc_initialize);
@@ -250,7 +249,6 @@ void serial_initialize(void)
max3100_serial_initialize();
mxc_serial_initialize();
pl01x_serial_initialize();
- s3c44b0_serial_initialize();
sa1100_serial_initialize();
sh_serial_initialize();
arm_dcc_initialize();
diff --git a/drivers/serial/serial_s3c44b0.c b/drivers/serial/serial_s3c44b0.c
deleted file mode 100644
index 2a07498c1e..0000000000
--- a/drivers/serial/serial_s3c44b0.c
+++ /dev/null
@@ -1,216 +0,0 @@
-pyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * ght 2002-2004
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* flush serial input queue. returns 0 on success or negative error
- * number otherwise
- */
-static int serial_flush_input(void)
-{
- volatile u32 tmp;
-
- /* keep on reading as long as the receiver is not empty */
- while(UTRSTAT0&0x01) {
- tmp = REGB(URXH0);
- }
-
- return 0;
-}
-
-
-/* flush output queue. returns 0 on success or negative error number
- * otherwise
- */
-static int serial_flush_output(void)
-{
- /* wait until the transmitter is no longer busy */
- while(!(UTRSTAT0 & 0x02)) {
- }
-
- return 0;
-}
-
-
-static void s3c44b0_serial_setbrg(void)
-{
- u32 divisor = 0;
-
- /* get correct divisor */
- switch(gd->baudrate) {
-
- case 1200:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
- divisor = 3124;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
- divisor = 3905;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
- break;
-
- case 9600:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
- divisor = 390;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
- divisor = 487;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
- break;
-
- case 19200:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
- divisor = 194;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
- divisor = 243;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
- break;
-
- case 38400:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
- divisor = 97;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
- divisor = 121;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif /* break; */
-
- case 57600:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
- divisor = 64;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
- divisor = 80;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif /* break; */
-
- case 115200:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
- divisor = 32;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
- divisor = 40;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif /* break; */
- }
-
- serial_flush_output();
- serial_flush_input();
- UFCON0 = 0x0;
- ULCON0 = 0x03;
- UCON0 = 0x05;
- UBRDIV0 = divisor;
-
- UFCON1 = 0x0;
- ULCON1 = 0x03;
- UCON1 = 0x05;
- UBRDIV1 = divisor;
-
- for(divisor=0; divisor<100; divisor++) {
- /* NOP */
- }
-}
-
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-static int s3c44b0_serial_init(void)
-{
- serial_setbrg ();
-
- return (0);
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-static void s3c44b0_serial_putc(const char c)
-{
- /* wait for room in the transmit FIFO */
- while(!(UTRSTAT0 & 0x02));
-
- UTXH0 = (unsigned char)c;
-
- /*
- to be polite with serial console add a line feed
- to the carriage return character
- */
- if (c=='\n')
- serial_putc('\r');
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int s3c44b0_serial_tstc(void)
-{
- return (UTRSTAT0 & 0x01);
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int s3c44b0_serial_getc(void)
-{
- int rv;
-
- for(;;) {
- rv = s3c44b0_serial_tstc();
-
- if(rv > 0)
- return URXH0;
- }
-}
-
-static struct serial_device s3c44b0_serial_drv = {
- .name = "s3c44b0_serial",
- .start = s3c44b0_serial_init,
- .stop = NULL,
- .setbrg = s3c44b0_serial_setbrg,
- .putc = s3c44b0_serial_putc,
- .puts = default_serial_puts,
- .getc = s3c44b0_serial_getc,
- .tstc = s3c44b0_serial_tstc,
-};
-
-void s3c44b0_serial_initialize(void)
-{
- serial_register(&s3c44b0_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &s3c44b0_serial_drv;
-}